CN220526907U - Packaging structure - Google Patents

Abstract

The application discloses packaging structure, this packaging structure includes: the first module at least comprises a first electronic element and a first packaging layer for packaging the first electronic element; a substrate including at least one cavity and electrically connected to the first module through a first solder; the second module comprises a second electronic element and is positioned in the cavity, and the second electronic element is electrically connected with the first module through a second solder; wherein the second solder has a size substantially equal to the size of the first solder. In the technical scheme, the first module is electrically connected with the substrate and the second module through the first solder and the second solder with the substantially same size, and the heating degrees of the first solder and the second solder in the reflow soldering process are basically the same, so that the first solder and the second solder can form good electrical connection after the reflow soldering process, and the problems of cracking, necking or cold joint caused by different heating degrees can be avoided.

Description

Packaging structure

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a packaging structure.

Background

Currently, because many I/Os need to be provided on a limited area of a chip, these I/O-providing pads/bumps need to be smaller in size. For example, in the FOCOS (Fan Out Chip on Substrate, fan-out on substrate chip) package structure shown in fig. 1A, a single chip 10 (e.g., an asic chip) includes differently sized pads 12a, 12b and differently sized bumps 16a, 16b, and a single chip 20 includes differently sized pads 22a, 22b and differently sized bumps 26a, 26b. The small-sized pads 12b, 22b may be used to provide I/O for high-speed operation and the large-sized pads 12a, 22a may be used to provide power or ground electrical connections. However, the amount of solder to be mated is different for various sizes, for example, the small-sized pads 12b, 22b are smaller in amount and thus the bumps 16b, 26b have small sizes, and the large-sized pads 12a, 22a are larger in amount and thus the bumps 16a, 26a have large sizes. Different amounts of solder, due to different degrees of heating during reflow, can cause problems after thermal processing or reliability testing. For example, as shown in fig. 1B, small-sized bumps 26B with a small amount of solder may neck due to overheating during the solder bonding process, and/or large-sized bumps 26a may fracture, cold joint, delaminate due to insufficient heating during the solder bonding process.

Disclosure of Invention

In view of the above, the present application proposes a packaging structure that can at least improve the above-mentioned problems in the prior art.

The technical scheme of the application is realized as follows:

according to one aspect of the present application, there is provided a package structure including: the first module at least comprises a first electronic element and a first packaging layer for packaging the first electronic element; a substrate including at least one cavity and electrically connected to the first module through a first solder; the second module comprises a second electronic element and is positioned in the cavity, and the second electronic element is electrically connected with the first module through a second solder; wherein the second solder has a size substantially equal to the size of the first solder.

In some embodiments, the size of the pads of the first electronic component is different from the size of the pads of the second electronic component.

In some embodiments, the size of the pads of the first electronic element is different than the size of the pads at the surface of the substrate facing the first module.

In some embodiments, the package structure further includes a third module including a third electronic component and the other cavity is electrically connected to the first module through a third solder, the third solder having a size substantially equal to the size of the first solder.

In some embodiments, the package structure further includes an underfill that encapsulates the first solder and the second solder, the underfill extending into the cavity.

In some embodiments, the first solder is connected to pads of substantially the same size at a surface of the substrate facing the first module.

In some embodiments, the first module further includes a first rewiring layer between the first electronic component and the first solder.

In some embodiments, the first redistribution layer has a plurality of pads of substantially the same size at a surface facing the substrate, wherein the first solder and the second solder physically connect the corresponding pads.

In some embodiments, the second module further comprises a second redistribution layer having a plurality of pads of substantially the same size at a surface facing the first module, wherein the pads of the second redistribution layer have a size substantially equal to the size of the pads of the first redistribution layer.

In some embodiments, the size of the pads of the second redistribution layer is substantially equal to the size of the pads at the surface of the substrate facing the first module.

The beneficial effects of the technical scheme include: the first solder and the second solder with substantially equal dimensions are used for electrically connecting the first module with the substrate and the second module, and the heating degree of the first solder and the second solder in the reflow soldering process is substantially the same, so that the first solder and the second solder can form good electrical connection after the reflow soldering process, and the problems of cracking, necking or cold joint caused by different heating degrees can be avoided.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1A is a schematic cross-sectional view of a conventional package structure.

Fig. 1B is a partially enlarged schematic view at a region A1 in fig. 1A.

Fig. 2 is a schematic cross-sectional view of a package structure according to one embodiment of the present application.

Fig. 3A to 3O are schematic cross-sectional views at a plurality of steps of forming a first module in the package structure shown in fig. 2.

Fig. 4A to 4L are schematic cross-sectional views at a plurality of steps of forming a second module in the package structure shown in fig. 2.

Fig. 5A to 5G are schematic cross-sectional views at a plurality of steps of forming a substrate in the package structure shown in fig. 2.

Fig. 6A to 6G are schematic views at a plurality of steps of forming a package structure using the first module, the second module, the third module, the fourth module, and the substrate.

Fig. 7-10 are schematic cross-sectional views of package structures according to various embodiments of the present application, respectively.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application are within the scope of the protection of the present application.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the utility model. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Moreover, the present utility model may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, embodiments and features of embodiments in this application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 2 is a schematic cross-sectional view of a package structure 100 according to one embodiment of the present application. Referring to fig. 2, the package structure 100 includes a substrate 110, and a first module 210 disposed above the substrate 110. The first module 210 includes a first electronic component 212 and a first encapsulation layer 214 encapsulating the first electronic component 212. The substrate 110 is electrically connected to the first module 210 through the first solder 131.

The substrate 110 includes a cavity 142. The package structure 100 further includes a second module 220 located in the cavity 142. The second module 220 includes a second electronic component 222 located within the cavity 142. The second electronic component 222 is electrically connected to the first module 210 through the second solder 132. The second solder 132 has a size substantially equal to the size of the first solder 131. The substantially equal size of the first solder 131 and the second solder 132 may mean that the width of the first solder 131 in the direction X is substantially equal to the width of the second solder 132. In some embodiments, the width of the first solder 131 is its diameter and the width of the second solder 132 is its diameter. In some embodiments, the height of the first solder 131 in the direction Z is substantially equal to the height of the second solder 132.

In the above package structure 100, the first module 210 is electrically connected to the substrate 110 and the second module 220 through the first solder 131 and the second solder 132 with substantially equal dimensions, and the heat degree of the first solder 131 and the heat degree of the second solder 132 in the reflow process are substantially the same, so that the first solder 131 and the second solder 132 can form good electrical connection after the reflow process, that is, the problems of cracking, necking or cold joint caused by different heat degrees of the solders with different dimensions in the prior art are avoided.

With continued reference to fig. 2, the first module 210 further includes a first redistribution layer 218 between the first electronic component 212 and the first solder 131. The first redistribution layer 218 may be electrically connected with the pads 212p of the first electronic element 212. The first re-wiring layer 218 may also be electrically connected with the first solder 131 and the second solder 132.

The second module 220 further includes a second redistribution layer 228, and the second electronic component 222 may be electrically connected to the first module 210 through the second redistribution layer 228 and the second solder 132. The second module 220 further includes a second encapsulation layer 224 encapsulating the second electronic component 222. The second redistribution layer 228 has a plurality of pads 229 having substantially the same dimensions at an upper surface thereof facing the first module 210. In this specification, the size of a pad (e.g., the pad 229) may refer to the width of the pad. The bottom of the second solder 132 is physically connected to the corresponding pad 229.

In some embodiments, the substrate 110 may also have a cavity 144. The package structure 100 may further include a third module 230 located in the cavity 144, the third module 230 including a third electronic component 232 located in the cavity 144, and a third rewiring layer 238. The third module 230 further includes a third encapsulation layer 234 encapsulating the third electronic component 232. The third module 230 may be electrically connected to the first module 210 through the third solder 133. The third electronic component 232 may be electrically connected to the first module 210 through the third redistribution layer 238 and the third solder 133.

In some embodiments, the first module 210 further includes a fourth electronic component 216 encapsulated by the first encapsulation layer 214. The pads 216p of the fourth electronic component 216 may be connected to the first rewiring layer 218 through vias 217. The via 217 passes through the first encapsulation layer 214 and may thus be referred to as an encapsulation via (MTV, molding Through Via). In some embodiments, the material of the via 217 may include any one of Cu (copper), au (gold), ag (silver), al (aluminum), pd (palladium), pt (platinum), and Ni (nickel), or an alloy of any plurality thereof.

The substrate 110 may also have a cavity 146. The fourth module 240 is disposed in the cavity 146. The fourth module 240 includes a fifth electronic component 242, a fourth rewiring layer 248 electrically connected to the fifth electronic component 242, and a fourth encapsulation layer 244 encapsulating the fifth electronic component 242. The fifth electronic component 242 is connected to the fourth solder 134 through the fourth redistribution layer 248, and the fourth module 240 can be electrically connected to the first module 210 through the fourth solder 134.

In some embodiments, the dimensions of any two of the pads 212p of the first electronic element 212, the pads 222p of the second electronic element 222, the pads 232p of the third electronic element 232, the pads 216p of the fourth electronic element 216, and/or the pads of the fifth electronic element 242 may be different. The size of the pad may refer to the width of the pad.

The lower surface of the first re-wiring layer 218 faces the substrate 110, and has a plurality of pads 219 of substantially the same size at the lower surface. The pad 212p of the first electronic component 212 and the pad 216p of the fourth electronic component 216 are connected to the pad 219 of the first rewiring layer 218 through the first rewiring layer 218. The pads 212p of the first electronic element 212 are connected to the pads 229 of the second redistribution layer 228 through the second redistribution layer 228. Pad 232p of third electronic element 232 is connected to pad 239 of third rewiring layer 238 through third rewiring layer 238. The dimensions of each pad 239 may be substantially equal. The pads of the fifth electronic component 242 are connected to the pads 249 of the fourth rewiring layer 248 through the fourth rewiring layer 248. The dimensions of the individual pads 249 may be substantially equal.

Pads 119 are provided at a surface of the substrate 110 facing the first module 210. The dimensions of pad 229, pad 239, pad 249, and pad 119 of substrate 110 may be the same, and may be equal to the dimensions of pad 219 of first redistribution layer 218. In some embodiments, the size of any of the pads 212p, 222p, 232p, 216p, and/or 242 of the first, second, third, fourth, and/or fifth electronic elements 212, 222 is different than the size of any of the pads 119, 219, 229, 239, 249.

The first solder 131 connects the pad 119 with the pad 219, the second solder 132 connects the pad 229 with the pad 219, the third solder 133 connects the pad 239 with the pad 219, and the fourth solder 134 connects the pad 249 with the pad 219. The first solder 131, the second solder 132, the third solder 133, and the fourth solder 134 may be substantially equal in size. In this way, the substrate 110, the second module 220, the third module 230, and the fourth module 240 may be electrically connected to the first module 210 by the first solder 131, the second solder 132, the third solder 133, and the fourth solder 134 having the same size to electrically connect the first electronic component 212, the second electronic component 222, the third electronic component 232, the fourth electronic component 216, and the fifth electronic component 242 having different pad sizes.

In some embodiments, the thickness in direction Z of any two of the second re-wiring layer 228, the third re-wiring layer 238, and the fourth re-wiring layer 248 may be different. The first solder 131, the second solder 132, the third solder 133, and the fourth solder 134 are located at substantially the same height level in the direction Z.

In the embodiment shown in fig. 2, the first electronic component 212, the second electronic component 222, and the third electronic component 232 are chips, and the fourth electronic component 216 and the fifth electronic component 242 may be passive components (e.g., resistors, capacitors, etc.). In other embodiments, the first electronic component 212, the second electronic component 222, the third electronic component 232, the fourth electronic component 216, and the fifth electronic component 242 may be other types of electronic components.

In some embodiments, the first, second, third and fourth encapsulation layers 214, 224, 234, 244 may be any one of Polyimide (PI), epoxy, ABF (Ajinomoto Build-up Film), polypropylene (PP) and acryl (acrylic), and may also be any one of organic photosensitive liquid, organic non-photosensitive liquid, dry Film material. In some embodiments, the material of each of the first to fourth solders 131 to 134 may be any one of solder, ACP (Anisotropic Conductive Paste, paste anisotropic conductive paste), ACF (Anisotropic Conductive Film, film anisotropic conductive paste).

With continued reference to fig. 2, the space between the first redistribution layer 218 and the substrate 110 is filled with an underfill 150. The underfill 150 encapsulates the first solder 131, the second solder 132, the third solder 133, and the fourth solder 134. The underfill 150 also extends into the cavities 142, 144, 146. The underfill 150 fills between the second module 220 and the substrate 110, between the third module 230 and the substrate 110, and between the fourth module 240 and the substrate 110.

In some embodiments, any of the first electronic element 212, the second electronic element 222, the third electronic element 232 may be a chip, for example, an ASIC (Application Specific Integrated Circuit, application specific integrated circuit chip) or HBM (High Bandwidth Memory ) chip. In one embodiment, the first electronic component 212 is an HBM chip and the second electronic component 222 is an ASIC chip.

The width of any one of the first electronic component 212, the second electronic component 222, and the third electronic component 232 in the direction X may be in the range of 10 μm to 1000 μm, and the thickness in the direction Z may be in the range of 20 μm to 200 μm. The widths of the second, third and fourth modules 220, 230 and 240 (equal to the widths of the second, third and fourth encapsulation layers 224, 234 and 244, respectively) in the direction X may be in the range of 10 to 1000 μm, and the thickness in the direction Z may be in the range of 20 to 200 μm. The thickness of the first encapsulation layer 214 in the direction Z may be in the range of several hundred micrometers to several millimeters, for example, may be in the range of 100 μm to 9 mm.

The distance D1 between the lower surface of the second module 220 located within the cavity 142 and the substrate 110 may be in the range of 5 μm to 50 μm, and the distance D2 between the side of the second module 220 and the substrate 110 may be in the range of 5 μm to 50 μm. Similarly, the distance between the lower surface of the third module 230 and the substrate 110, the distance between the lower surface of the fourth module 240 and the substrate 110 may be in the range of 5 μm to 50 μm, the distance between the side of the third module 230 and the substrate 110, and the distance between the side of the fourth module 240 and the substrate 110 may be in the range of 5 μm to 50 μm.

The width (i.e., diameter) of each of the first to fourth solders 131 to 134 may be in the range of 5 μm to 100 μm, and the Pitch (Pitch) between each adjacent two of the first to fourth solders 131 to 134 may be in the range of 10 μm to 200 μm. In some embodiments, each of the first through fourth solders 131 through 134 may be a C4 bump, and the width (i.e., diameter) of each of the first through fourth solders 131 through 134 may be greater than 20 μm.

The surface of the substrate 110 remote from the first module 210 is provided with solder balls 111. The diameter of the solder balls 111 may be in the range of 30 μm to 200 μm, and the pitch between adjacent two solder balls 111 may be in the range of 50 μm to 400 μm.

The first module 210 is electrically connected with the substrate 110, the second module 220, the third module 230 and the fourth module 240 through the first solder 131, the second solder 132, the third solder 133 and the fourth solder 134 with substantially equal sizes, and the heat degree of the first solder 131, the second solder 132, the third solder 133 and the fourth solder 134 in the reflow process is substantially the same, so that the first solder 131, the second solder 132, the third solder 133 and the fourth solder 134 can form good electrical connection after the reflow process, that is, the problems of cracking, necking or cold joint caused by different heat degrees of the solders with different sizes in the prior art are avoided.

The package structure 100 provided in the present application may have a plurality of redistribution layers (e.g., the first redistribution layer 218 to the fourth redistribution layer 248) and a plurality of modules (e.g., the first module 210 to the fourth module 240)/devices (e.g., the first electronic device 212 to the fifth electronic device 242) disposed in the same package structure 100, which may be used for more functions and may improve the performance of the package structure 100.

For the interconnections within the package structure 100, the second module 220 to the fourth module 240 are connected using the first solder 131 to the fourth solder 134 connected to a single size (e.g., a large size having a width of more than 20 μm) of the first module 210. The larger and single size of the first to fourth solders 131 to 134 is more advantageous for improving reliability. The first redistribution layer 218 in the first module 210 may provide sufficient area for more I/O designs. In some embodiments, the linewidth pitch of the first re-routing layer 218 may be less than 2 μm/2 μm, such that the fine-line first re-routing layer 218 may provide more I/O designs. In addition, the second through fourth redistribution layers 228 through 248 in the second through fourth modules 220 through 240 may provide fine-pitch pads 229, 239, 249 for bridging the second, third, and fifth electronic elements 222, 232, and 242 to provide more I/O.

In addition, the CTE (coefficient of thermal expansion ) of the substrate 110 is relatively large, e.g., the CTE of the substrate 110 is greater than the CTE of the first 214 through fourth 244 package layers, the first 218 through fourth 248 redistribution layers, and the underfill 150. Because of the different CTEs of the different materials, when the different materials together undergo a temperature change in the environment, the respective materials will experience different amounts of expansion (amount of expansion or contraction) due to the CTE difference, and thus will cause stress warpage due to the difference in the amount of expansion when the different materials are bonded together. Thus, if the substrate 110 is bonded together in physical contact with the first 214 through fourth 244 and the first 218 through fourth 248 redistribution layers, the amount of expansion or contraction will be different when the temperature changes, and the stress warpage will be greater. According to the embodiment of the present application, the stress warpage can be advantageously avoided by disposing the underfill 150 in the gap between the substrate 110 and the first module 210 and disposing the underfill 150 in the gaps between the second to fourth modules 220 to 240 and the substrate 110.

Methods of forming the package structure 100 shown in fig. 2 are also provided in accordance with embodiments of the present application. Fig. 3A to 3O are schematic cross-sectional views at a plurality of steps of forming the first module 210 in the package structure 100 shown in fig. 2. Referring to fig. 3A, a first carrier 301 is provided. The first electronic component 212 is placed on the first carrier 301. At this time, the bonding pad 212p of the first electronic component 212 is far away from the first carrier 301. Referring to fig. 3B, a plurality of fourth electronic components 216 are disposed on the first carrier 301.

Referring to fig. 3C, a molding process is performed to form a first encapsulation layer 214 encapsulating the first electronic component 212 and each fourth electronic component 216. The pads 212p of the first electronic component 212 are exposed by the first encapsulation layer 214. Referring to fig. 3D, a dielectric layer 218D is covered on the first encapsulation layer 214.

Referring to fig. 3E, photolithography, development, etching, and the like processes are performed to form a plurality of openings 321 through the dielectric layer 218D and the first encapsulation layer 214, and a plurality of openings 322 through the dielectric layer 218D. The plurality of openings 321 expose the pads 216p of the fourth electronic component 216, respectively. Then, a seed layer 332 is covered over the dielectric layer 218D, the seed layer 332 extending into each of the openings 321, 322 and being electrically connected to the first electronic component 212 and the fourth electronic component 216.

Referring to fig. 3F, a mask layer 342 is covered on the seed layer 332, and the mask layer 342 fills the remaining space of the openings 321, 322 (see fig. 3E). The material of the mask layer 342 may be a photoresist. Referring to fig. 3G, photolithography, development, etching, and the like are performed to form a plurality of openings through the mask layer 342, and the openings are filled with a conductive material 350.

Referring to fig. 3H, the mask layer 342 and the seed layer 332 covered by the mask layer 342 are removed. The conductive material 250 forms patterned conductive lines 218L with the remaining seed layer 332. Moreover, a via 217 is formed through the first encapsulation layer 214 to the fourth electronic component 216.

The steps described in fig. 3D-3H may then be repeated to form a greater number of dielectric layers 218D and conductive traces 218L, as shown in fig. 3I.

Referring then to fig. 3J, a final dielectric layer 218D is further overlaid on the structure shown in fig. 3I. Then, as shown in fig. 3K, photolithography, development, etching, etc. are performed to form an opening 323 through the last dielectric layer 218D, and a seed layer 334 is formed to cover the last dielectric layer 218D and extend into the opening 323, and the seed layer 334 is connected to the underlying conductive line 218L.

Referring to fig. 3L, a mask layer 344 is overlaid on the seed layer 334. Then, photolithography, development, and etching processes may be performed to form a plurality of openings 324 through the mask layer 344, as shown in fig. 3M. Next, the opening 324 is filled with the conductive material 350, and the solder 130 is further filled on the conductive material 350.

Mask layer 344 and seed layer 334 covered by mask layer 344 are then removed, as shown in fig. 3N. The seed layer 334 and conductive material 350 remaining over the last dielectric layer 218D form the pad 219. Thus, a first redistribution layer 218 is formed on the first encapsulation layer 214, the first redistribution layer 218 including a plurality of dielectric layers 218D, conductive traces 218L disposed in the plurality of dielectric layers 218D, and pads 219 located on the dielectric layers 218D. In some embodiments, the material of conductive line 218L and pad 219 may include any one of Cu, au, ag, al, pd, pt and Ni, or an alloy of any number of.

In some embodiments, the thickness of each dielectric layer 218D of the first redistribution layer 218 may be in the range of 5 μm to 20 μm. The thickness of the conductive lines 218L of the first re-routing layer 218 may be in the range of 1 μm to 10 μm, wherein the thickness of the seed layers 332, 334 of the conductive lines 218L may be in the range of 0.1 μm to 1 μm. The line width and pitch of the conductive lines 218L of the first re-wiring layer 218 may be in the range of 2 μm/2 μm to 20 μm/20 μm. In some embodiments, the linewidth of the conductive lines 218L of the first redistribution layer 218 may be less than 2 μm/2 μm.

Referring to fig. 3O, a dicing process is performed on the resulting structure along the line L1, and the first electronic component 212 and the fourth electronic component 216 encapsulated by the first encapsulation layer 214, the first re-wiring layer 218 electrically connected to the first electronic component 212 and the fourth electronic component 216, and the plurality of solders 130 connected to the first re-wiring layer 218 are formed on the first carrier 301. The solder amounts of the plurality of solders 130 are the same. The plurality of solders 130 includes the first solder 131 to the fourth solder 134 described above with reference to fig. 2.

Fig. 4A to 4L are schematic cross-sectional views at a plurality of steps of forming a second module 220 embedded in a cavity 142 of a substrate 110 in the package structure 100 shown in fig. 2.

Referring to fig. 4A, a second carrier 401 is provided, and a release layer 402 is covered on the second carrier 401. Referring to fig. 4B, the second electronic component 222 is placed on the second carrier 401, and at this time, the bonding pad 222p of the second electronic component 222 is far away from the second carrier 401.

Referring to fig. 4C, a molding process is performed to form a second package layer 224 for packaging a plurality of second electronic devices 222. The second encapsulation layer 224 exposes the pads 222p of the plurality of second electronic components 222.

Referring to fig. 4D, a dielectric layer 228D is covered on the second encapsulation layer 224. Then, photolithography, development, etching, and the like are performed, and as shown in fig. 4E, a plurality of openings 421 exposing the pads 222p are formed in the dielectric layer 228D. Then, a seed layer 432 is covered over the dielectric layer 228D, the seed layer 432 extending into each opening 421 to connect the plurality of pads 222p.

Referring to fig. 4F, a mask layer 442 is covered on the seed layer 432. Then, photolithography, development, etching, etc. processes may be performed to form a plurality of openings 422 through the mask layer 442, as shown in fig. 4G. Next, the opening 422 is filled with a conductive material 450. Then, the mask layer 442 and the seed layer 432 covered by the mask layer 442 are removed, as shown in fig. 4H. The remaining seed layer 432 and conductive material 450 form conductive lines 228L connected to pads 222p of the first electronic component 222.

Referring to fig. 4I, the structure shown in fig. 4H is continued to be covered with a further dielectric layer 228D. Also, the steps described in fig. 4D-4H may be repeated to form a greater number of dielectric layers 228D and conductive lines 228L. As shown in fig. 4J, a second re-wiring layer 228 is formed, the second re-wiring layer 228 including a multi-layered dielectric layer 228D, and a multi-layered conductive line 228L provided in the multi-layered dielectric layer 228D to a pad 229 provided over the dielectric layer 228D. In some embodiments, the material of the dielectric layer 228D of the first redistribution layer 228 may be any one of polyimide, epoxy, ABF, polypropylene, and acryl, and may also be any one of an organic photosensitive liquid, an organic non-photosensitive liquid, and a dry film material.

Referring to fig. 4K, the release layer 402 and the second carrier 401 are removed. Referring to fig. 4L, a dicing process 440 is performed at a position between adjacent second electronic components 222, and the dicing process 440 cuts the second redistribution layer 228 and the second packaging layer 224 to obtain individual second modules 220.

The third and fourth die sets 230 and 240 in fig. 2 are formed in a manner similar to the steps described above with reference to fig. 4A-4L and may have similar material compositions, which are not repeated here.

Fig. 5A-5G are schematic cross-sectional views at various steps of forming the substrate 110 with cavities 142, 144, 146 in the package structure 100 shown in fig. 2.

Referring to fig. 5A, an initial substrate 110' is provided. The initial substrate 110' includes a plurality of dielectric layers 110D, and conductive traces 110L disposed in the plurality of dielectric layers 110D. The pads 119 of the initial substrate 110' for bonding with the first die set 210 face upward. The pad 119 may connect the conductive trace 110L within the initial substrate 110'.

Referring to fig. 5B, a drilling process 510 is performed, for example, to form the cavity 144 through the initial substrate 110'.

Referring to fig. 5C, after three cavities 142, 144, 146 are formed in the initial substrate 110', the initial substrate 110' is inverted such that the pads 119 face downward. Then, a dielectric layer 110D is further covered on the side of the initial substrate 110' facing away from the pad 119. Then, photolithography, development, etching, etc. are performed, and as shown in fig. 5D, a plurality of openings 521 are formed through the dielectric layer 110D. Then, a seed layer 532 is covered over the dielectric layer 110D, the seed layer 532 extending into each opening 521.

Referring to fig. 5E, a mask layer 542 is overlaid on the seed layer 532. Then, photolithography, development, etching, etc. processes may be performed, as shown in fig. 5F, to form a plurality of openings 522 through the mask layer 542. Next, the opening 522 is filled with a conductive material 550. Then, the mask layer 542 and the seed layer 532 covered by the mask layer 542 are removed, and as shown in fig. 5G, the seed layer 532 and the conductive material 550 remaining on the dielectric layer 110D form a pad 110p for connecting solder balls later. This forms the substrate 110 with the cavities 142, 144, 146.

In some embodiments, the material of the dielectric layer 110D may be any one of polyimide, epoxy, ABF, polypropylene, and acryl, and may also be any one of an organic photosensitive liquid, an organic non-photosensitive liquid, and a dry film material. In some embodiments, the material of the conductive line 110L may include any one of Cu, au, ag, al, pd, pt and Ni, or an alloy of any number of. The thickness of each dielectric layer 110D of the substrate 110 may be in the range of several micrometers to several tens of micrometers, for example, in the range of 5 μm to 90 μm.

Fig. 6A to 6G are schematic views at various steps of forming the package structure 100 using the first module 210, the second module 220, the third module 230, the fourth module 240, and the substrate 110 formed above.

Referring to fig. 6A, pads 239 of third module 230 are bonded with corresponding solder 130. Referring to fig. 6B, the pads 229 of the second module 220 are bonded with the corresponding solders 130. Referring to fig. 6C, the pads 249 of the fourth die set 240 are bonded with the corresponding solders 130.

Referring to fig. 6D, the solder 130 bonded to the second die set 220 is the second solder 132, the solder 130 bonded to the third die set 230 is the third solder 133, and the solder 130 bonded to the fourth die set 240 is the fourth solder 134. At this time, the non-bonded solder 130 is the first solder 131 to be subsequently bonded to the substrate 110. The underfill 150 is poured over the first module 210. The underfill 150 covers the second, third and fourth modules 220, 230 and 240. In some embodiments, the material of the underfill 150 may be any one of Polyimide (PI), epoxy, ABF, polypropylene (PP), and acryl (acrylic), and may also be any one of an organic photosensitive liquid, an organic non-photosensitive liquid, and a dry film material.

Referring to fig. 6E, the substrate 110 is assembled with the structure shown in fig. 6D. Each of the cavities 142, 144, 146 of the substrate 110 is vertically aligned with a corresponding second, third, and fourth module 220, 230, 240, respectively, and the substrate 110 is moved downward. The portion of the substrate 110 where the cavity is not formed may displace the underfill 150 such that the pad 119 of the substrate 110 is bonded with the first solder 131. The underfill 150 extends into each of the cavities 142, 144, 146 and fills between the second module 220, the third module 230, the fourth module 240, and the substrate 110.

Referring to fig. 6F, solder balls 111 are bonded on the pads 110p of the substrate 110. The material of the solder balls 111 may be any one of solder, ACP (Anisotropic Conductive Paste, paste-like anisotropic conductive paste), ACF (Anisotropic Conductive Film, film-like anisotropic conductive paste). Referring to fig. 6G, the structure of fig. 6F is inverted and then the resulting structure of fig. 6F is cut along line L2 to yield package structure 100.

In some embodiments, the solder 130, the via 217, the pad 219 of the first redistribution layer 218, the conductive trace 218L, the conductive trace 110L in the substrate 110, and the solder ball 111 may be formed by a variety of suitable processes, such as using PVD (Physical Vapor Deposition ), electroplating, electroless plating, metal printing, metal pouring, and the like.

In the above-mentioned process of forming the package structure 100, when forming the substrate 110, the cavities 142, 144, 146 are first formed in the initial substrate 110 'by the panel-level (or wafer-level) process through the drilling process 510, and then the conductive traces 110L and the dielectric layer 110D are continuously fabricated on the initial substrate 110' to form the substrate 110 and the pads 110p for connecting the pads 111. In addition, the first package layer 214 and some embedded components (e.g., the first electronic component 212 and/or the fourth electronic component 215) may be fabricated on the first carrier 301 by a panel-level (or wafer-level) process, and the first redistribution layer 218 having a fine pitch may be further fabricated on the first package layer 214 to form the first module 210. Then, the second to fourth modules 220 to 240 are bonded to the first module 210, and the underfill 150 is potted on the first module 210, and the underfill 150 covers the second to fourth modules 220 to 240. Subsequently, the first module 210 is bonded to the substrate 110, and the underfill 150 fills all gaps, including the gaps between the second module 220 to the fourth module 240 and the substrate, and the gaps between the first module 210 and the substrate 110. Finally, after the structures are assembled together, solder ball 111 placement and package singulation at the panel level (or wafer level) is performed.

In the process of forming the package structure 100, since the second module 220 to the fourth module 240 are individually fabricated and then bonded to the first module 210, and then the first module 210 and the substrate 110 are bonded together, each module can be tested before bonding, so that the component and module loss problem can be avoided. The first module 210 may be manufactured at a wafer (or panel) level, and the first module 210 may be combined with the substrate 110 at the wafer (or panel) level, which is advantageous for reducing costs.

Fig. 7 is a schematic cross-sectional view of a package structure 200 according to another embodiment of the present application. Aspects of the package structure 200 shown in fig. 7 may be similar to the package structure 100 shown in fig. 2, and only the differences of the package structure 200 in fig. 7 are described below. Referring to fig. 7, the first module 210 may not include the first encapsulation layer 214. The first electronic component 212 and the fourth electronic component 216 may be exposed on the first rewiring layer 218. In this embodiment, the first electronic component 212 and the fourth electronic component 216 may be bonded on the first redistribution layer 218 by using the solder 740 through an SMT process. The space between the first electronic component 212 and the first redistribution layer 218 may be filled with an underfill 750.

Fig. 8 is a schematic cross-sectional view of a package structure 300 according to another embodiment of the present application. Aspects of the package structure 300 shown in fig. 8 may be similar to the package structure 100 shown in fig. 2, and only the differences of the package structure 300 in fig. 8 are described below. Referring to fig. 8, the substrate 110 may have a cavity 142, and the second module 220 is located in the cavity 142. In other embodiments, the substrate 110 may be provided with any number of cavities, and corresponding modules disposed in the cavities, as desired.

Fig. 9 is a schematic cross-sectional view of a package structure 400 according to another embodiment of the present application. Aspects of the package structure 400 shown in fig. 9 may be similar to the package structure 100 shown in fig. 2, and only the differences of the package structure 400 in fig. 9 are described below. Referring to fig. 9, the substrate 110 has a cavity 942, and the second module 220, the third module 230 and the fourth module 240 are all located in the same cavity 942. In other embodiments, the substrate 110 may be provided with any number of cavities as desired, and any number of modules may be provided in each cavity.

Fig. 10 is a schematic cross-sectional view of a package structure 500 according to another embodiment of the present application. Aspects of the package structure 500 shown in fig. 10 may be similar to the package structure 100 shown in fig. 2, and only the differences of the package structure 500 in fig. 10 are described below. Referring to fig. 10, surfaces of the second and third modules 220 and 230 facing away from the first module 210 may be in contact with the substrate 110. Similarly, a surface of the third module 230 facing away from the first module 210 may be in contact with the substrate 110.

As used herein, the terms "substantial", "about" are used to indicate and explain minor variations. For example, when used in conjunction with a numerical value, the terms "substantially" and "about" may refer to a range of variation of less than or equal to + -10% of the corresponding numerical value. The terms "substantially coplanar", "substantially flush" may refer to two surfaces lying within ±50 μm along the same plane (such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm along the same plane).

The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but rather is intended to cover any and all modifications, equivalents, alternatives, and improvements within the spirit and principles of the present application.

Claims (10)

1. A package structure, comprising:

the first module at least comprises a first electronic element and a first packaging layer for packaging the first electronic element;

a substrate including at least one cavity and electrically connected to the first module through a first solder;

the second module comprises a second electronic element and is positioned in one cavity, and the second electronic element is electrically connected with the first module through a second solder;

wherein the second solder has a size substantially equal to the size of the first solder.

2. The package structure of claim 1, wherein,

the size of the bonding pads of the first electronic component is different from the size of the bonding pads of the second electronic component.

3. The package structure of claim 1, wherein a size of the pads of the first electronic component is different from a size of the pads at a surface of the substrate facing the first module.

4. The package structure of claim 1, further comprising:

and a third module including a third electronic component and the other of the cavities, and electrically connected to the first module via a third solder, the third solder having a size substantially equal to the size of the first solder.

5. The package structure of claim 1, further comprising:

an underfill encapsulating the first and second solders, the underfill extending into the cavity.

6. The package structure of claim 1, wherein the first solder is connected to pads of substantially the same size at a surface of the substrate facing the first module.

7. The package structure of claim 1, wherein the first module further comprises a first rewiring layer between the first electronic component and the first solder.

8. The package structure of claim 7, wherein the first redistribution layer has a plurality of pads of substantially the same size at a surface facing the substrate, wherein the first solder and the second solder are physically connected to the corresponding pads.

9. The package structure of claim 8, wherein the second module further comprises a second redistribution layer having a plurality of pads of substantially the same size at a surface facing the first module, wherein a size of the pads of the second redistribution layer is substantially equal to a size of the pads of the first redistribution layer.

10. The package structure of claim 9, wherein the size of the pads of the second redistribution layer is substantially equal to the size of pads at a surface of the substrate facing the first module.