KR102331050B1 - Semiconductor packages and method of forming same - Google Patents

Abstract

In one embodiment, a package comprises a first integrated circuit die having an active side including a die connector, and a back surface, a second integrated circuit die adjacent the first integrated circuit die, an active side including a die connector, and a back surface a second integrated circuit die, a routing die bonded to active surfaces of the first integrated circuit die and the second integrated circuit die, the routing die electrically coupling the first integrated circuit die to the second integrated circuit die; a first package structure comprising an integrated circuit die and an encapsulant sealing the routing die, and a first redistribution structure on and electrically connected to the die connector of the first integrated circuit die and the second integrated circuit die; do.

Description

Semiconductor package and method of forming the same

<Cross Reference>

This application claims priority to U.S. Provisional Application No. 62/586,509, entitled "Semiconductor Packages and Methods of Forming Same," filed on November 15, 2017, which priority application is incorporated herein by reference. Included.

<background>

The semiconductor industry continues to grow rapidly due to continuous improvement in the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density results from repeated reductions in the minimum feature size, so that more components can be integrated within a given area. As the desire to shrink electronic devices increases, there is a need for smaller and more ingenious packaging techniques for semiconductor dies. An example of such a packaging system is a Package-on-Package (PoP) technology. For PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables the production of semiconductor devices with improved functionality and small footprints on printed circuit boards (PCBs).

Aspects of the present disclosure are best understood from the following detailed description with reference to the accompanying drawings. In accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for convenience of description.
1-15 are cross-sectional and plan views of intermediate steps in the process of forming a package structure in accordance with some embodiments.
16-19 are cross-sectional views of intermediate steps in the process of forming a package structure in accordance with some embodiments.

The following disclosure provides a number of different embodiments or embodiments for implementing different features of the invention. To simplify the present disclosure, specific embodiments of components and configurations are described below. Of course, these are merely examples, and are not intended to be limiting. For example, in the description that follows, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and the first and second features Embodiments may also be included in which additional features may be formed between the first and second features such that the second features do not directly contact. Also, the present disclosure may repeat reference numerals and/or letters in the various embodiments. This repetition is for the purpose of simplification and clarification, and does not in itself indicate a relationship between the various embodiments and/or configurations described.

In addition, space-related terms such as "beneath", "below", "lower", "above", "upper", etc. It may be used herein for ease of description in describing the relationship of a feature to another element(s) or feature(s). Spatial terminology is intended to include different orientations of the device in use or operation, in addition to the orientation shown in the drawings. The apparatus may be otherwise oriented (rotated 90 degrees or in other orientations) and spatially related descriptors used herein may likewise be interpreted accordingly.

Embodiments described herein may be discussed in specific contexts, namely, a package structure (eg, package on package (PoP)), which includes routing dies that connect one or more dies within the package structure. In some embodiments, the routing die is a fine pitch routing die in which the pitch of the routing (eg, line width and spacing) is less than that of a conventional redistribution structure. The routing die may be an integrated passive device (IPD), a surface mount device (SMD), a routing die without active and passive devices, an integrated circuit die, and the like. The routing die may be bonded face-to-face with one or more dies. Additionally, the routing die may be sealed with the same encapsulant as the one or more die. In some embodiments, a front-side redistribution structure of a package including one or more dies and a routing die may overlie the routing die pins such that the routing die is between the one or more dies and the front redistribution structure. Embodiments of the present disclosure may include routing dies having routing densities that are five times greater than the routing densities of conventional redistribution structures.

Further, the teachings of this disclosure are applicable to any package structure that includes one or more semiconductor dies. Other embodiments contemplate other applications, such as other package types or other configurations, that are readily understood by those skilled in the art upon reading this disclosure. It should be noted that the embodiments disclosed herein do not represent every component or feature that may be present in a structure. For example, multiples of one component may be omitted from the drawings, because a description of one component is sufficient to convey the characteristics of the embodiment. Moreover, while method embodiments disclosed herein are described as being performed in a particular order, other method embodiments may be performed in any logical order.

1-15 illustrate cross-sectional and top views of intermediate steps in the process of forming a first package structure in accordance with some embodiments. 1 shows a carrier substrate 100 and a release layer 102 formed thereon. A first package area 600 and a second package area 602 for forming the first package and the second package are shown.

The carrier substrate 100 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 100 may be a wafer, so that multiple packages may be simultaneously formed on the carrier substrate 100 . The release layer 102 may be formed of a polymer-based material, and may be removed together with the carrier substrate 100 from an upper substrate formed in a subsequent step. In some embodiments, release layer 102 is an epoxy-based thermal-release material, such that its adhesion properties, such as a Light-to-Heat-Conversion (LTHC) release coating, are improved upon heating. disappear In another embodiment, release layer 102 is an ultra-violet (UV) glue, which loses its adhesion when exposed to UV light. The release layer 102 may be dispensed like a liquid and cured, may be laminated as a laminate film on the carrier substrate 100 , or a similar method may be used. The top surface of the release layer 102 may be flat and may have a high degree of coplanarity.

In Fig. 2, a dielectric layer 104 and a metallization pattern 106 (sometimes referred to as a redistribution layer or redistribution line) are formed. A dielectric layer 104 is formed on the exfoliation layer 102 . A bottom surface of the dielectric layer 104 may contact a top surface of the exfoliation layer 102 . In some embodiments, dielectric layer 104 is formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In another embodiment, the dielectric layer 104 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PhosphoSilicate Glass (PSG), BoroSilicate Glass (BSG), Boron-doped PhosphoSilicate Glass (BPSG), or the like. The dielectric layer 104 may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, or the like, or a combination thereof.

A metallization pattern 106 is formed on the dielectric layer 104 . As an example for forming the metallization pattern 106 , a seed layer (not shown) is formed over the dielectric layer 104 . In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer may include a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD. Then, a photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and exposed for patterning. The pattern of photoresist corresponds to the metallization pattern 106 . The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed within the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include metal, copper copper, titanium, tungsten, aluminum, and the like. Then, the portion of the seed layer on which the conductive material is not formed and the photoresist are removed. The photoresist is removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed by an acceptable etching process such as wet or dry etching. The remainder of the seed layer and the conductive material form a metallization pattern 106 .

In FIG. 3 , a dielectric layer 108 is formed over the metallization pattern 106 and the dielectric layer 104 . In some embodiments, dielectric layer 108 is formed of a polymer, which may be a photosensitive material, such as PBO, polyimide, BCB, or the like, that can be patterned using a lithographic mask. In another embodiment, the dielectric layer 108 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 108 may be formed by spin coating, laminating, CVD, or the like, or a combination thereof. The dielectric layer 108 is then patterned to form openings 46 that expose portions of the metallization pattern 106 . The patterning may be accomplished by a process of exposing the dielectric layer 108 to light when the dielectric layer is a photosensitive material, or by an acceptable process such as etching using, for example, anisotropic etching.

The dielectric layers 104 and 108 and the metallization pattern 106 may be referred to as a back-side redistribution structure 110 . In the illustrated embodiment, the backside redistribution structure 110 includes two dielectric layers 104 and 108 and one metallization pattern 106 . In other embodiments, the backside redistribution structure 110 may include any number of dielectric layers, metallization patterns, and conductive vias. One or more additional metallization patterns and dielectric layers may be formed in the rear redistribution structure 110 by repeating the process of forming the metallization pattern 106 and the dielectric layer 108 . Conductive vias (not shown) may be formed during formation of the metallization pattern by forming a seed layer and conductive material of the metallization pattern in the opening of the lower dielectric layer. Conductive vias can thereby interconnect and electrically couple the various metallization patterns.

4 , an electrical connector 112 is formed. Since the electrical connector 112 will extend through the subsequently formed sealant 130 (see FIG. 9 ), it may hereinafter be referred to as a through via 112 . As an example for forming the through via 112 , a seed layer is formed over the exposed portions of the back surface redistribution structure 110 , such as the dielectric layer 108 and the metallization pattern 106 , as shown. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer may include a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD. A photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and exposed for patterning. The pattern in the photoresist corresponds to the through via. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed within the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include metal, copper copper, titanium, tungsten, aluminum, and the like. The portion of the seed layer where no conductive material is formed and the photoresist are removed. The photoresist is removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed by an acceptable etching process such as wet or dry etching. The remaining portion of the seed layer and the conductive material form a through via 112 .

5 , the integrated circuit die 114 is adhesively adhered to the release layer 102 . Although two integrated circuit dies 114 are shown as adhered to each of the second package region 600 and the second package region 602, more or fewer integrated circuit dies 114 are attached to each package region. It should be noted that it may be sticky. For example, only one integrated circuit die 114 may be adhered to each region. The integrated circuit die 114 includes a logic die (e.g., central processing unit, microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die ( e.g. power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g. digital signal processing (DSP) dies), front-end dies ( eg, analog front end (AFE) die), etc., or a combination thereof. Further, in some embodiments, the integrated circuit dies 114 may be of different sizes (eg, different heights and/or surface areas), and in other embodiments, the integrated circuit dies 114 may be the same size (eg, the same height). and/or surface area).

Prior to adhering to the release layer 102 , the integrated circuit die 114 may be processed according to an applicable manufacturing process to form an integrated circuit within the integrated circuit die 114 . For example, each integrated circuit die 114 includes an active layer of a semiconductor substrate 118 or a semiconductor-on-insulator (SOI) substrate, such as doped or undoped silicon. The semiconductor substrate comprises a compound semiconductor comprising another semiconductor material such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antitide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or an alloy semiconductor comprising GaInAsP, or a combination thereof. Other substrates may also be used, such as multi-layered or inclined substrates. Devices such as transistors, diodes, capacitors, resistors, etc. may be formed in and/or on the semiconductor substrate 118 , such as metallization in one or more dielectric layers on the semiconductor substrate 118 , to form an integrated material. may be interconnected by an interconnect structure 120 formed by a pattern. Interconnect structure 120 is formed using damascene and/or dual damascene processes in some embodiments.

The integrated circuit die 114 further includes pads 122, such as copper pads or aluminum pads, to which external connections are made. Pads 122 are on what may be referred to as the respective active side of integrated circuit die 114 . A passivation film 124 is on the integrated circuit die 114 and may be on a portion of the pad 122 . The opening passes through the passivation layer 124 to reach the pad 122 . A die connector 126 , such as a conductive pillar (eg, including a metal such as copper), is in the opening passing through the passivation film 124 and is mechanically and electrically coupled to each pad 122 . The die connector 126 may be formed, for example, by plating or the like. Die connector 126 electrically couples each integrated circuit of integrated circuit die 114 .

5 , integrated circuit die 114 may have die connectors 126 (eg, die connectors 126A and 126B) of different configurations. In some embodiments, the integrated circuit die 114 includes a short die connector 126B and a tall die connector 126A. The short die connector 126B allows space for a subsequently attached routing die (eg, see FIG. 7A ) while keeping the thickness of the package structure to a minimum. The tall die connector 126A electrically couples the integrated circuit die 114 to the subsequently formed front redistribution structure 131 (see, eg, FIG. 10 ), which includes the integrated circuit die 114 and the front redistribution structure ( 131), there is a routing die. In some embodiments, these short and tall die connectors may be formed by similar processing, in which case an additional process (eg, an etching process) is performed on the short die connector 126B to make them shorter. In some embodiments, the tall die connector 126A is formed in a separate forming process from the short die connector 126B. For example, the tall die connector 126A may be formed using a first forming process (eg, a first plating process), and then a mask may be covered, and the short die connector 126B may be formed in a second forming process. It is formed using a process (eg, a second plating process).

An adhesive 116 on the backside of the integrated circuit die 114 adheres the integrated circuit die 114 to the release layer 102 . Adhesive 116 may be any suitable adhesive, epoxy, die attach film (DAF), or the like. In some embodiments, the adhesive has a thickness in the range of about 5 μm to about 30 μm, measured in a direction perpendicular to the back surface of each integrated circuit die 114 . The adhesive 16 may be applied to the backside of the integrated circuit die 114 , such as the backside of each semiconductor wafer, or it may be applied over the surface of the carrier substrate 100 . The integrated circuit die 114 may be singulated, such as by sawing or dicing, and adhered to the release layer 102 with an adhesive 116 using, for example, a pick-and-place tool.

In Fig. 6, a routing circuit 160 is shown. Routing die 160 may be an integrated passive device (IPD), a surface mount device (SMD), a routing die without active and passive devices, an integrated circuit die, or the like. Routing die 160 may be processed through a process similar to that described above with respect to integrated circuit die 114 . For example, each routing die 160 includes a substrate 162 , an interconnect structure 163 , and a routing pad 164 . Substrate 162 may be formed of a semiconductor material, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate comprises: a semiconductor material such as germanium; and/or an alloy semiconductor including GaInAsP, or a combination thereof. Other substrates may also be used, such as multi-layered or inclined substrates.

The interconnect structure 163 is formed by, for example, a metallization pattern 161 in one or more dielectric layers on the substrate 162 . Interconnect structure 163 may be formed using damascene and/or dual damascene processes in some embodiments. In some embodiments, the metallization pattern 161 of the interconnect structure 163 is a fine pitch metallization pattern in which the pitch (eg, line width and spacing) of the metallization pattern is smaller than the pitch of a conventional redistribution structure. In some embodiments, the line width of the fine pitch metallization pattern is in the range of about 0.03 μm to about 12 μm, such as about 0.4 μm, and the spacing between the lines of the fine pitch metallization pattern is in the range of about 0.03 μm to about 12 μm. within the range, such as about 0.4 μm.

In some embodiments, routing die 160 is free of active and passive devices and is used to route signals between integrated circuit die 14 . In some embodiments, devices such as transistors, diodes, capacitors, resistors, etc. may be formed in and/or on substrate 162 and may be interconnected by interconnect structure 163 to form an integrated circuit.

Routing die 160 further includes pads 164, such as copper pads or aluminum pads, to which external connections are made. A passivation film 166 is on the routing die 160 and may be on a portion of the pad 164 . The opening passes through the passivation film 166 to reach the pad 164 . Die connectors 168 , such as conductive posts (eg, comprising metal such as copper, with or without a solder cap layer), are in openings through passivation film 166 to mechanically and electrically couple to respective pads 164 . do. The die connector 168 may be formed, for example, by plating or the like. Die connectors 168 are electrically coupled to respective metallization patterns 161 of routing die 160 .

7A and 7B , routing die 160 is bonded to integrated circuit die 114 . In some embodiments, the die connector of the routing die 160 is bonded to the short die connector 126B of the integrated circuit die 114 . In some other embodiments, the die connector 168 is bonded to the metal pad 122 when the short die connector 126B is not over the metal pad 122 . In some embodiments, routing die 160 electrically couples adjacent integrated circuit dies 114 to each other in a structure including only a front redistribution structure (eg, front redistribution structure 131 in FIG. 10 ). It increases routing density compared to

The bonding between the routing die 160 and the integrated circuit die 114 may be solder bonding or direct metal-to-metal (such as copper-to-copper or tin-to-tin) bonding. In one embodiment, the routing die 160 is bonded to the integrated circuit die 114 by a reflow process. During this reflow process, die connector 168 contacts die connector 126B to physically and electrically connect routing die 160 to integrated circuit die 114 . After the bonding process, an intermetallic compound (IMC) (not shown) may be formed at the interface between the die connector 126 and the die connector 168 .

After the routing die 160 is bonded to the integrated circuit die 114 , the routing die 160 is separated from the nearest tall die connector 126A by a distance D1 . In some embodiments, this distance D1 is at least about 2 μm, such as 3 μm. Further, the bonded routing die has a height H2 measured from the metal pad 122 to the backside of the routing die 160 . This height H2 is smaller than the height H1 of the tall die connector 126A. The height H1 of the tall die connector 126A is measured from the metal pad 122 to the top surface of the die connector 126A. In some embodiments, height H1 is at least about 3 μm greater than height H2, such as height H1 is 4 μm greater than height H2.

Fig. 7b shows a top view of the structure of Fig. 7a; As shown in FIG. 7B , there may be multiple routing dies 160 coupled to and between a pair of integrated circuit dies 114 . The cross-sectional view of FIG. 7A is taken along line A-A or line B-B of FIG. 7B . 7B also shows that each routing die 160 may have a different number and configuration of die connectors 168 , such as 2, 4, 6, 10, 20 or hundreds of die connectors 168 .

In Figure 8, sealant 130 is formed on the various components. The sealing material 130 may be a molding compound, epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. The sealing material 130 may be formed on the carrier substrate 100 such that the electrical connector 112 , the tall die connector 126A, and the routing die 160 are buried or covered. A sealant 130 extends between the routing die 160 and the integrated circuit die 114 to which the routing die is bonded. In some embodiments, the encapsulant surrounds the die connector 168 of the routing die 160 and the tall and short die connectors 126A/126B of the integrated circuit die 114 . Then, the sealing material 130 may be cured.

In FIG. 9 , the sealant 130 may be subjected to a grinding process to expose the electrical connector 112 and the tall die connector 126A. After the grinding process, the top surfaces of the electrical connector 112, the tall die connector 126A, and the sealing material 130 are at the same height. In some embodiments, grinding may be omitted, for example if electrical connector 112 and tall die connector 126A are already exposed. The electrical connector 112 may also be referred to as a through via 112 hereinafter. In some embodiments, the backside of routing die 160 is covered after the grinding process. In some embodiments, at least a portion of the back surface of the routing die 160 is exposed after the grinding process.

In FIG. 10 , a front redistribution structure 131 is formed. The front redistribution structure 131 includes dielectric layers 132 , 136 , 140 , and 144 and metallization patterns 134 , 138 , and 142 .

Formation of the front redistribution structure 131 may begin by depositing a dielectric layer 132 on the sealant 130 , the through via 112 , and the die connector 126A. In some embodiments, dielectric layer 132 is formed of a polymer, which may be a photosensitive material, such as PBO, polyimide, BCB, or the like, that can be patterned using a lithographic mask. In another embodiment, dielectric layer 132 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 132 may be formed by spin coating, laminating, CVD, or the like, or a combination thereof.

Next, the dielectric layer 132 is patterned. The patterning forms an opening to expose a portion of the toll die connector 126A and the through via 112 . The patterning may be performed by a process of exposing the dielectric layer 132 to light when the dielectric layer 132 is a photosensitive material, or an acceptable process such as etching using, for example, anisotropic etching. If dielectric layer 132 is a photosensitive material, dielectric layer 132 may be developed after exposure.

Next, a metallization pattern 134 having vias is formed on the dielectric layer 132 . As an example for forming the metallization pattern 134 , a seed layer (not shown) is formed over the dielectric layer 132 and in the openings through the dielectric layer 132 . In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer may include a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD. Then, a photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and exposed for patterning. The pattern of photoresist corresponds to the metallization pattern 134 . The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed within the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include metal, copper copper, titanium, tungsten, aluminum, and the like. Then, the portion of the seed layer on which the conductive material is not formed and the photoresist are removed. The photoresist is removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed by an acceptable etching process such as wet or dry etching. The remainder of the seed layer and the conductive material form metallization patterns 138 and vias. Vias are formed in openings through dielectric layer 132 , such as through vias 112 and/or toll die connectors 126A.

This process may be repeated for the dielectric layers 136 and 140 and the metallization patterns and vias 138 and 142 to continue the formation of the redistribution structure 131 . Materials and processes used to form these layers of the redistribution structure 131 may be similar to the dielectric layer 132 and the metallization patterns and vias 134 , and descriptions thereof are not repeated herein.

After formation of the metallization pattern and vias 142 , a dielectric layer 144 is deposited over the metallization pattern 142 and the dielectric layer 140 . In some embodiments, dielectric layer 144 is formed of a polymer, which may be a photosensitive material, such as PBO, polyimide, BCB, or the like, that can be patterned using a lithographic mask. In another embodiment, dielectric layer 144 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 144 may be formed by spin coating, laminating, CVD, or the like, or a combination thereof.

11 , dielectric layer 144 is then patterned. The patterning forms an opening to expose a portion of the metallization pattern 142 . The patterning may be accomplished by a process of exposing the dielectric layer 144 to light when the dielectric layer is a photosensitive material, or by an acceptable process such as etching using, for example, anisotropic etching. If dielectric layer 144 is a photosensitive material, dielectric layer 144 may be developed after exposure.

The front redistribution structure 131 is shown as an example. More or fewer dielectric layers and metallization patterns may be formed in the front redistribution structure 131 . If fewer dielectric layers and metallization patterns are formed, the steps and processes described above may be omitted. If more dielectric layers and metallization patterns are formed, the steps and processes described above may be repeated. Those skilled in the art will readily understand which steps and processes are omitted or repeated.

In some embodiments, the routing die 160 may have a routing density that is about 5 times higher than the routing density possible for the front redistribution structure 131 . For example, the metallization pattern of the front redistribution structure 131 may have a line width within a range of about 2 μm to about 15 μm, and the interval between lines of the metallization pattern of the front redistribution structure 131 is about 2 It can be in the range of from about 15 μm to about 15 μm. As noted above, routing die 160 may have a line width/spacing within a range of about 0.03 μm/0.03 μm to about 12 μm/12 μm, such as about 0.4 μm/0.4 μm.

Thus, in an embodiment where the width and spacing of the routing die is about 0.03 μm/0.03 μm, the routing density of the routing die is about 66 times higher than the minimum routing density of the front redistribution structure 131 and/or the front redistribution structure ( 131) can be about 500 times higher than the maximum routing density of In embodiments where the routing die width and spacing are about 0.4 μm/0.4 μm, the routing density of the routing die is about 5 times greater than the minimum routing density of the front redistribution structure 131 and/or the front redistribution structure 131 . can be about 375 times higher than the maximum routing density of In embodiments where the width and spacing of the routing die is about 12 μm/12 μm, the routing density of the routing die is about 6 times lower than the minimum routing density of the front redistribution structure 131 and/or the front redistribution structure 131 . can be about 1.25 times higher than the maximum routing density of

Also, in FIG. 11 , the pad 150 is formed on the outside of the front redistribution structure 131 . Pad 150 is used to couple to conductive connector 152 (see FIG. 12 ) and may also be referred to as under bump metallurgy (UBM) 150 . In the illustrated embodiment, pads 150 are formed through openings through dielectric layer 144 to metallization pattern 142 . As an example for forming the pad 150 , a seed layer (not shown) is formed over the dielectric layer 144 . In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer may include a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD. Then, a photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and exposed for patterning. The pattern of photoresist corresponds to the pad 150 . The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed within the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include metal, copper copper, titanium, tungsten, aluminum, and the like. Then, the portion of the seed layer on which the conductive material is not formed and the photoresist are removed. The photoresist is removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed by an acceptable etching process such as wet or dry etching. The remainder of the seed layer and the conductive material form the pad 150 . In this embodiment, if the pads 150 are formed differently, more photoresist and patterning steps may be used.

12 , a conductive connector 152 is formed on the UBM. The conductive connector 152 is formed with a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, and an electroless nickel electroless palladium immersion gold (ENEPIG) technology. It may be a bump or the like. The conductive connector 152 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connector 152 is formed by initially forming a solder layer through commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, and the like. Once the solder layer has been formed on the structure, a reflow may be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 152 is a metal pillar (eg, a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal posts may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on top of the metal post connector 152 . The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or a combination thereof, and may be formed by a plating process.

In FIG. 13 , carrier substrate de-bonding is performed to separate (debond) the carrier substrate 100 from the backside redistribution structure 110 , eg, the dielectric layer 104 . Accordingly, a first package 200 is formed in each of the first package region 600 and the second package region 602 . According to some embodiments, debonding includes projecting light, such as laser light or UV light, onto the release layer 102 so that the release layer 102 is decomposed by light heat so that the carrier substrate 100 can be peeled off. do. The structure is then turned over and placed on tape 176 . Also, an opening 178 is formed through the dielectric layer 104 to expose a portion of the metallization pattern 106 . Openings 178 may be formed using, for example, laser drilling, etching, or the like.

14 and 15 illustrate cross-sectional views of intermediate steps in the process of forming a package structure 500 in accordance with some embodiments. The package structure 500 may be referred to as a package-on-package (PoP) structure.

In FIG. 14 , the second package 300 is attached to the first package 200 . The second package 300 includes a substrate 302 and one or more stacked dies 308 , 308A and 308B coupled to the substrate 302 . Although a single stack of dies 308 , 308A and 308B is shown, in other embodiments a plurality of stacked dies 308 (each having one or more stacked dies) are coupled to the same surface of the substrate 302 and placed side by side. it might be The substrate 302 may be made of a semiconductor material such as silicon, germanium, or diamond. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, etc. may also be used. Additionally, the substrate 302 may be a semiconductor-on-insulator (SOI) substrate. In general, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. In one alternative embodiment, the substrate 302 is based on an insulating core, such as a glass fiber reinforced resin core. An example of a core material is glass fiber resin, such as FR4. Alternatives to core materials include bismaleimide-triazine (BT) resins or alternatively other printed circuit board (PCB) materials or films. A buildup film, such as Ajinomoto build-up film (ABF) or another laminate, may be used for the substrate 302 .

Substrate 302 may include active and passive devices (not shown). Those skilled in the art will appreciate that a variety of devices, such as transistors, capacitors, resistors, combinations thereof, etc., may be used to create the structural and functional requirements of the design for the second package 300 . The device may be formed using any suitable method.

The substrate 302 may also include a metallization layer (not shown) and a through via 306 . Metallization layers can be formed over active and passive devices and are designed to connect various devices to form functional circuitry. The metallization layer may be formed from alternating layers of dielectric (eg, low-k dielectric material) and conductive material (eg, copper), with vias interconnecting layers of conductive material, and may be formed by any suitable process (deposition, damascene, double damisin, etc.). In some embodiments, the substrate 302 is substantially free of active and passive devices.

The substrate 302 may have bond pads 303 on a first side of the substrate 302 for bonding to a stack die 308 , and bonds on the substrate 302 for bonding to a conductive connector 314 . It may have a pad 304 , a second side opposite the first side of the substrate 302 . In some embodiments, the bond pads 303 and 304 are formed by forming recesses (not shown) in a dielectric layer (not shown) on the first and second sides of the substrate 302 . The recesses may be formed to allow the bond pads 303 and 304 to be buried in the dielectric layer. In another embodiment, the recesses are omitted because the bond pads 303 and 304 may be formed on the dielectric layer. In some embodiments, bond pads 303 and 304 include thin seed layers (not shown) made of copper, titanium, nickel, gold, palladium, etc., or combinations thereof. A conductive material of bond pads 303 and 304 may be deposited over the thin seed layer. The conductive material may be formed by an electrochemical plating process, an electroless plating process, CVD, ALD, PVD, or the like, or a combination thereof. In one embodiment, the conductive material of the bond pads 303 , 304 is copper, tungsten, aluminum, silver, gold, etc., or a combination thereof.

In one embodiment, bond pads 303 and 304 are UBMs comprising three layers of a conductive material, such as a titanium layer, a copper layer, and a nickel layer. However, those skilled in the art will recognize that there are many suitable arrangements for the formation of bond pads 303 and 304, such as a chromium/chromium-copper alloy/copper/gold arrangement, a titanium/titanium tungsten/copper arrangement, or a copper/nickel/gold arrangement. It will be appreciated that there is an arrangement of suitable materials and layers. Any suitable material or material layer that may be used for bond pads 303 and 304 is fully intended to be included within the scope of this disclosure. In some embodiments, a through via 306 extends through the substrate 302 and couples the at least one bond pad 303 to the at least one bond pad 304 .

In the illustrated embodiment, the stack die 308 is coupled to the substrate 302 by wire bonds 310 , although other connections such as conductive bumps may be used. In one embodiment, the stack die 308 is a stack memory die. For example, stack die 308 may be a memory die, such as a low power (LP) double data rate (DDR) memory module, such as an LPDDR1, LPDDR2, LPDDR3, LPDDR4, or similar memory module.

The stack die 308 and wire bonds 310 may be sealed with a molding material 312 . Molding material 312 may be molded onto stack die 308 and wire bonds 310 using, for example, compression molding. In some embodiments, the molding material 312 is a molding compound, a polymer, an epoxy, a silicon oxide filling material, or the like, or a combination thereof. A curing step may be performed to cure the molding material 312 , and the curing step may be thermal curing, UV curing, or the like, or a combination thereof.

In some embodiments, stack die 308 and wire bonds 210 are embedded in molding material 312 , and after curing of molding material 312 , a planarization step such as grinding is performed to reduce molding material 312 . The excess portion is removed and provides a substantially planar surface for the second package 300 .

After the second package 300 is formed, the second package 300 is mechanically and electrically connected to the first package 200 by means of a conductive connector 314 , a bond pad 304 , and a metallization pattern 106 . are bonded In some embodiments, the stack die 308 is coupled to the integrated circuit die via wire bonds 310 , bond pads 303 and 304 , through vias 306 , conductive connectors 314 , and through vias 112 . 114) can be combined.

Although the conductive connector 314 is similar to the conductive connector 152 described above and description is not repeated herein, the conductive connector 314 and the conductive connector 152 need not be the same. A conductive connector 314 may be disposed on the side of the substrate 302 opposite the stack die 308 at the opening 178 . In some embodiments, a solder resist (not separately labeled) may also be formed on the side of the substrate opposite the stack die 308 . A conductive connector 314 may be disposed in an opening in the solder resist to electrically and mechanically couple to conductive features (eg, bond pads 304 ) in the substrate 302 . Solder resist may be used to protect areas of the substrate 302 from external damage.

In some embodiments, prior to bonding the conductive connector 314 , the conductive connector 314 is coated with a flux (not shown), such as a no-clean flux. The conductive connector 314 may be immersed in the flux or the flux may be sprayed onto the electrical connector 314 . In other embodiments, a flux may be applied to the surface of the metallization pattern 106 .

In some embodiments, the conductive connector 314 may have an optional epoxy flux (not shown) formed before reflow, and the electrical connector after the second package 300 is attached to the first package 200 . At least a portion of the epoxy portion of the remaining epoxy flux is reflowed.

An underfill material (not shown) may be formed between the first package 200 and the second package 300 to surround the conductive connector 314 . The underfill can reduce stress and protect the junction formed by reflowing of the conductive connector 314 . The underfill may be formed by a capillary flow process after the first package 200 is attached, or may be formed by a suitable deposition method before the first package 200 is attached. In embodiments where an epoxy flux is formed, the epoxy flux may act as an underfill.

The bonding between the second package 300 and the first package 200 may be solder bonding. In one embodiment, the second package 300 is bonded to the first package 200 by a reflow process. During this reflow process, conductive connector 314 contacts bond pad 304 and metallization pattern 106 to physically and electrically couple second package 300 to first package 200 . After the bonding process, an intermetallic compound (IMC, not shown) may be formed at the interface between the metallization pattern 106 and the conductive connector 114 and at the interface between the conductive connector 314 and the bond pad 304 .

The singulation process is performed, for example, by sawing along a scribe line area between the first package area 600 and the second package area 602 . Sawing separates the first package area 600 from the second package area 602 . The individualized first and second packages 200 and 300 are thereby derived from either the first package area 600 or the second package area 602 . In some embodiments, the singulation process is performed after the second package 300 is attached to the first package 200 . In another embodiment (not shown), the singulation process is performed before the second package 300 is attached to the first package 200 , such as after the carrier substrate 100 is debonded and the openings 178 are formed. do.

In FIG. 15 , a first package 200 is mounted on a package substrate 400 using a conductive connector 152 . The package substrate 400 may be made of a semiconductor material such as silicon, germanium, or diamond. Meanwhile, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, and combinations thereof may also be used. Additionally, the package substrate 400 may be an SOI substrate. In general, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In one alternative embodiment, the package substrate 400 is based on an insulating core, such as a glass fiber reinforced resin core. An example of a core material is glass fiber resin, such as FR4. Alternatives to core materials include bismaleimide-triazine (BT) resins or alternatively other PCB materials or films. A buildup film, such as ABF or other laminate, may be used for the package substrate 400 .

The package substrate 400 may include active and passive devices (not shown). Those of ordinary skill in the art will appreciate that a variety of devices, such as transistors, capacitors, resistors, combinations thereof, etc., may be used to create the structural and functional requirements of the design for package structure 500 . The device may be formed using any suitable method.

The package substrate 400 may include metallization layers and vias (not shown), and bond pads 402 over the metallization layers and vias. Metallization layers can be formed over active and passive devices and are designed to connect various devices to form functional circuitry. The metallization layer may be formed from alternating layers of dielectric (eg, low-k dielectric material) and conductive material (eg, copper), with vias interconnecting layers of conductive material, and may be formed by any suitable process (deposition, damascene, double damisin, etc.). In some embodiments, the package substrate 400 is substantially free of active and passive devices.

In some embodiments, the conductive connector 152 is reflowed to attach the first package 200 to the bond pad 402 . The conductive connector 152 includes a metallization layer in the package substrate 400 to electrically and/or physically couple the package substrate 400 to the first package 200 . In some embodiments, a passive device (eg, a surface mount device (SMD), not shown) may be attached to the first package 200 (eg, a bond pad (eg, a bond pad) 402)). In this embodiment, a passive device may be bonded to the same surface of the first package 200 as the conductive connector 152 .

The conductive connector 152 may have an epoxy flux (not shown) formed prior to reflow, wherein the conductive connector comprises at least the epoxy portion of the epoxy flux remaining after the first package 200 is attached to the package substrate 400 . partly reflowed. This residual epoxy portion may act as an underfill to reduce stress and protect the junction formed by reflowing of the conductive connector 152 . In some embodiments, an underfill (not shown) may be formed between the first package 200 and the second package 400 to surround the conductive connector 152 . The underfill may be formed by a capillary flow process after the first package 200 is attached, or may be formed by a suitable deposition method before the first package 200 is attached.

16-19 are cross-sectional views of other package structures in accordance with some embodiments. 16-19 embodiment includes a routing die 160 with a through via 170 extending through a substrate 162 of the routing die 160 , except that the embodiment of FIGS. It is similar to the embodiment shown in 15. Details regarding this embodiment similar to the previously described embodiment will not be repeated here.

In FIG. 16 , a routing die 160 including through vias 170 is shown. Details regarding this embodiment of routing die 160 similar to the previously described embodiment of routing die 160 will not be repeated herein.

In this embodiment, a through via 170 extends through the substrate 162 from the metallization pattern 161 of the interconnect structure 163 to the backside of the substrate 162 . The through via 170 may be exposed from the backside of the substrate, and the exposed portion may be electrically coupled to an upper conductive feature (eg, a metallization pattern in the lower redistribution structure).

Although two through vias 170 are shown in routing die 160 , it should be understood that there may be more or fewer through vias 170 in each routing die 160 .

Fig. 17 shows processing of an intermediate stage equivalent to that of Figs. 7A and 7B described above, and the description thereof is not repeated here. In FIG. 17 , routing die 160 is bonded to integrated circuit die 114 . In some embodiments, the die connector of the routing die 160 is bonded to the short die connector 126B of the integrated circuit die 114 . In some other embodiments, the die connector 168 is bonded to the metal pad 122 when the short die connector 126B is not over the metal pad 122 . In some embodiments, routing die 160 electrically couples adjacent integrated circuit dies 114 to each other and to an upper conductive feature, such that a front redistribution structure (eg, front redistribution structure 131 in FIG. 10 ) is used in some embodiments. Increases routing density compared to only containing structures.

As with the previous embodiment, the height H2 of the routing die 160 may initially be lower than the height H1 of the tall die connector 126A. In this embodiment, the height difference between H1 and H2 is such that the through via 170 of the routing die 160 has a top surface flush with the top surface of the tall die connector 126A and the through via 112 (eg, in FIG. 18), and will be removed in a subsequent planarization process (eg, grinding the sealant 130). In some embodiments, the height H2 of the routing die 160 may initially be approximately equal to the height H1 of the tall die connector 126A, leveling to equalize these heights is necessary don't

Fig. 18 shows further processing for the structure of Fig. 17; The processing between these two drawings is similar to the processing exemplified and described with reference to FIGS. 8 to 12 , and FIG. 12 is an intermediate step equivalent to that of FIG. 18 , so the description thereof will not be repeated here.

In FIG. 18 , the through via 170 of the routing die 160 is physically and electrically connected to the metallization pattern and the via 132 of the front redistribution structure 131 . The through via 170 may simplify routing of lines and signals in the front redistribution structure 131 .

Fig. 19 shows further processing for the structure of Fig. 18; The processing between these two drawings is similar to the processing exemplified and described with reference to FIGS. 13 to 15 , and FIG. 14 is a manufacturing step equivalent to that of FIG. 19 , so the description thereof will not be repeated here.

In FIG. 19 , a package structure 200 including a routing die 160 having a through via 170 is included in the package structure 500 . Details regarding this embodiment similar to the previously described embodiment will not be repeated here.

By including routing dies that connect one or more dies to the package structure, the routing density of the package structure may be increased. In some embodiments, the routing die is a fine pitch routing die in which the pitch of the routing (eg, line width and spacing) is less than that of a conventional redistribution structure. The routing die may be an integrated passive device (IPD), a surface mount device (SMD), a routing die without active and passive devices, an integrated circuit die, and the like. The routing die may be bonded face to face with one or more dies. Also, the routing die may be sealed with the same sealant as the one or more die. In some embodiments, a front redistribution structure of a package including one or more dies and a routing die may overlie the routing die pins such that the routing die is between the one or more dies and the front redistribution structure. Embodiments of the present disclosure may include routing dies having routing densities that may be 66 times greater than the routing densities of conventional redistribution structures. In addition, the package including the routing die can be manufactured in a time-saving manner with less warpage as compared to other package structures that attempt to achieve similar routing densities in the redistribution structure.

In one embodiment, a package comprises a first integrated circuit die having an active side including a die connector, and a back surface, a second integrated circuit die adjacent the first integrated circuit die, an active side including a die connector, and a back surface a routing die bonded to two integrated circuit dies, the first integrated circuit die and the second integrated circuit die, the routing die having a front side and a back side, the front side of the routing die comprising a die connector, the die connector of the routing die comprising the first integrated circuit die the routing die and the first integrated circuit die, a second integrated circuit being bonded to active surfaces of a circuit die and a second integrated circuit die, the routing die electrically coupling the first integrated circuit die to a second integrated circuit die A first package structure comprising a circuit die and an encapsulant sealing the routing die, and a first redistribution structure on and electrically connected to the die connectors on the first integrated circuit die and the second integrated circuit die. wherein the routing die is between the first redistribution structure and the first integrated circuit die and the second integrated circuit die.

Embodiments may include one or more of the following features. The package, wherein the first package structural structure further comprises a first through via adjacent to the first integrated circuit die, the first through via extending through the encapsulant. The package further comprising a second package structure bonded to the first through via via the first set of conductive connectors. In the package, wherein the first package structure further includes a second redistribution structure electrically connected to the first through via, the second redistribution structure is disposed between the first integrated circuit die and the second integrated circuit die. have. The package further includes a package structure bonded to a first redistribution structure of the first package structure by a second set of conductive connectors. In the package, an encapsulant extends between the routing die and the first integrated circuit die and the second integrated circuit die, and the encapsulant surrounds a die connector of the routing die. In the package, the sealant extends between the routing die and the first redistribution structure. In the package, the routing die includes a substrate, an interconnect structure on the substrate comprising a metallization pattern in one or more dielectric layers, and a die connector electrically coupled to the metallization pattern of the interconnect structure. In the package, the routing die further includes a through via extending through the substrate, the through via being physically and electrically connected to the first redistribution structure. In the package, the routing die includes an active or passive device. In the package, the routing die is substantially free of active and passive devices.

In one embodiment, a method comprises forming a first package, forming an electrical connector on a carrier substrate, and attaching a backside of a first die to the carrier substrate using an adhesive layer, the attaching the backside of the first die, the first die adjacent the electrical connector, and attaching the backside of the second die to the carrier substrate using an adhesive layer, wherein the second die is adjacent to the second die. attaching the back side of the second die adjacent the first die; bonding the routing die to the active side of the first and second die using a die connector on the routing die; the bonding step electrically coupling the first and second dies; sealing the first die, the second die, the routing die, and the electrical connector with a molding compound; forming a first redistribution structure over two dies, a routing die, a molding compound, and an electrical connector; and removing the carrier substrate; bonding a second package to the first package using a set, wherein the second package is proximate to the first die and a back surface of the second die.

Embodiments may include one or more of the following features. The method further comprises forming a second redistribution structure over back surfaces of the first and second dies and over a first end of the first electrical connector, wherein the second redistribution structure comprises the electrical It is electrically connected to the connector, and the second package is bonded to the second redistribution structure. The method, wherein the molding compound extends between the routing die and the first integrated circuit die and the second integrated circuit die, and the molding compound surrounds a die connector of the routing die. In the method, the molding compound extends between the routing die and the first redistribution structure. The method further comprises the step of planarizing the molding compound, the die connectors on the active surfaces of the first and second dies, and the electrical connector to have flush surfaces. The method, wherein the routing die includes a substrate, an interconnect structure on the substrate comprising a metallization pattern in one or more dielectric layers, and extending through the substrate, physically and electrically connected to the first redistribution structure. and a through via connected to the , and a die connector electrically coupled to the metallization pattern of the interconnect structure. The method wherein the second and fourth sets of die connectors of the first and second dies are adjacent the routing die and extend from a front surface of the routing die to a rear surface of the routing die. The method, wherein the second and fourth sets of die connectors have a first height, the routing die has a second height, and the first height is greater than the second height.

In one embodiment, a method comprises forming a first package, forming an electrical connector over a carrier substrate, and adhering a first die to the carrier substrate, wherein the active side of the first die is attaching the first die to the carrier substrate, the step of attaching the first die comprising a first set and a second set of die connectors, the active side facing the back side, and the first die being adjacent the electrical connector; wherein the active side of the second die comprises a third and a fourth set of die connectors, the active side faces the back side, the second die adjacent the first die bonding a second die; bonding a routing die to the first and second dies using the first and third sets of die connectors; the first die, a second die, a routing die, and sealing the electrical connector with a molding compound, and forming a redistribution structure over the active surface of the first die, the molding compound, and the electrical connector, wherein the redistribution structure comprises second and second portions of the die connector. and forming the first package comprising the steps of: forming the redistribution structure electrically coupled to the set of four and the electrical connector; and removing the carrier substrate; bonding two packages to the first package, wherein the second package is proximate to the backside of the routing die.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. It will be appreciated by those skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for accomplishing the same purpose and/or achieving the same effects of the embodiments introduced herein. Furthermore, those skilled in the art will recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.

<bookkeeping>

1. In the package,

A first package structure, wherein the first package structure comprises:

a first integrated circuit die having an active side including a die connector, and a back-side;

a second integrated circuit die adjacent the first integrated circuit die, the second integrated circuit die having an active side including a die connector, and a back side;

a routing die bonded to the first integrated circuit die and the second integrated circuit die, the routing die having a front-side and a back side, the front side of the routing die including a die connector, the die connector of the routing die comprising the a routing die bonded to active surfaces of a first integrated circuit die and a second integrated circuit die, the routing die electrically coupling the first integrated circuit die to the second integrated circuit die;

an encapsulant sealing the first integrated circuit die, the second integrated circuit die, and the routing die;

a first redistribution structure electrically connected to the die connector on the die connectors of the first integrated circuit die and the second integrated circuit die

including,

and the routing die is between the first redistribution structure and the first integrated circuit die and the second integrated circuit die.

2. The method of claim 1, wherein the first package structure comprises:

and a first through via adjacent the first integrated circuit die, the first through via extending through the encapsulant.

3. Item 2,

and a second package structure bonded to the first through via via the first set of conductive connectors.

4. The method of claim 3, wherein the first package structure comprises:

Further comprising a second redistribution structure electrically connected to the first through via;

and the second redistribution structure is between the first integrated circuit die and the second integrated circuit die.

5. The package of clause 3, further comprising a package structure bonded to a first redistribution structure of the first package structure by the second set of conductive connectors.

6. The package of claim 1, wherein the sealant extends between the routing die and the first integrated circuit die and the second integrated circuit die, the sealant surrounds a die connector of the routing die.

7. The package of claim 1, wherein the sealant extends between the routing die and the first redistribution structure.

8. The method of 1, wherein the routing die comprises:

board and

an interconnect structure on the substrate comprising a metallization pattern in one or more dielectric layers;

a die connector electrically coupled to the metallization pattern of the interconnect structure

A package that contains

9. The package of clause 8, wherein the routing die further comprises a through via extending through the substrate, the through via being physically and electrically coupled to the first redistribution structure.

10. The package of clause 1, wherein the routing die comprises an active or passive device.

11. The package of clause 1, wherein the routing die is substantially free of active and passive devices.

12. A method comprising:

forming a first package, comprising:

forming an electrical connector on a carrier substrate;

attaching the backside of the first die to the carrier substrate using an adhesive layer, the first die adjacent the electrical connector;

attaching the backside of the second die to the carrier substrate using an adhesive layer, the second die adjacent the first die;

bonding a routing die to the active side of the first and second dies using a die connector on the routing die, the routing die electrically coupling the first and second dies Wow,

sealing the first die, the second die, the routing die, and the electrical connector with a molding compound;

forming a first redistribution structure over the first die, the second die, the routing die, the molding compound, and the electrical connector;

removing the carrier substrate

Including, the first package forming step;

bonding a second package to the first package using a first set of conductive connectors;

including,

and the second package is proximate to a back surface of the first die and the second die.

13. Clause 12,

forming a second redistribution structure over the back surfaces of the first die and the second die and over the first end of the first electrical connector;

The second redistribution structure is electrically connected to the electrical connector, and the second package is bonded to the second redistribution structure.

14. The method of clause 12, wherein the molding compound extends between the routing die and the first integrated circuit die and the second integrated circuit die, and the molding compound surrounds a die connector of the routing die.

15. The method of clause 12, wherein the molding compound extends between the routing die and the first redistribution structure.

16. Clause 12,

and planarizing the molding compound, die connectors on the active surfaces of the first and second dies, and the electrical connector to have flush surfaces.

*17. 13. The method of claim 12, wherein the routing die,

board and

an interconnect structure on the substrate comprising a metallization pattern in one or more dielectric layers;

a through via extending through the substrate and physically and electrically connected to the first redistribution structure;

a die connector electrically coupled to the metallization pattern of the interconnect structure

A method comprising

18. A method comprising:

forming a first package, comprising:

* forming an electrical connector on a carrier substrate;

adhering a first die to the carrier substrate, the active side of the first die comprising a first set and a second set of die connectors, the active side facing the back side, the first die comprising the said first die attaching adjacent to an electrical connector;

adhering a second die to the carrier substrate, the active side of the second die comprising a third and fourth set of die connectors, the active side facing the back side, the second die including the second die the second die sticking step adjacent to the first die;

bonding a routing die to the first and second dies using the first and third sets of die connectors;

sealing the first die, the second die, the routing die, and the electrical connector with a molding compound;

forming a redistribution structure over the active side of the first die, the molding compound, and the electrical connector, the redistribution structure electrically coupled to the electrical connector and the second and fourth sets of die connectors; and forming the redistribution structure;

removing the carrier substrate

Including, the first package forming step;

bonding a second package to the first package using a first set of conductive connectors, the second package proximate to a back surface of the routing die.

19. The method of clause 18, wherein the second and fourth sets of die connectors of the first and second die are adjacent the routing die and extend from a front side of the routing die to a back side of the routing die. .

20. The method of clause 18, wherein the second and fourth sets of die connectors have a first height, the routing die has a second height, and wherein the first height is greater than the second height.

Claims (8)

in the package,
A first package structure comprising:
a first integrated circuit die having an active side including a die connector, and a back-side;
a second integrated circuit die adjacent the first integrated circuit die, the second integrated circuit die having an active side including a die connector, and a back side;
a first routing die bonded to the first integrated circuit die and the second integrated circuit die, the first routing die having a front-side and a back surface, the front side of the first routing die including a die connector, the first routing die a die connector of the die is bonded to active surfaces of the first integrated circuit die and the second integrated circuit die, the first routing die electrically coupling the first integrated circuit die to the second integrated circuit die; and a passive device, wherein the first routing die comprises a first metallization pattern in one or more dielectric layers, the first metallization pattern having a line width in the range of 0.03 μm to 12 μm and a line width in the range of 0.03 μm to 12 μm. the first routing die having a spacing within a range;
a second routing die bonded to the first integrated circuit die and the second integrated circuit die, the second routing die having a front-side and a rear surface, the front side of the second routing die including a die connector, the second routing die a die connector of a die is bonded to active surfaces of the first integrated circuit die and the second integrated circuit die, the second routing die electrically coupling the first integrated circuit die to the second integrated circuit die; adjacent to the first routing die and free of active and passive devices, the second routing die having a different number of die connectors than the first routing die, the die connectors on the second routing die being in a plan view of the first routing die the second routing die being a different size than die connectors on the die;
the first package structure comprising an encapsulant sealing the first integrated circuit die, the second integrated circuit die, and the first and second routing dies; and
a first redistribution structure on die connectors of the first integrated circuit die and the second integrated circuit die and electrically connected to the die connectors, the first and second routing dies comprising the first between the redistribution structure and the first integrated circuit die and the second integrated circuit die, the first redistribution structure comprising a second metallization pattern in one or more dielectric layers, the second metallization pattern comprising: A package comprising the first redistribution structure, wherein the first redistribution structure has a line width within a range of μm to 15 μm and a spacing within a range of 2 μm to 15 μm. The method of claim 1,
The first package structure,
and a first through via adjacent the first integrated circuit die, the first through via extending through the encapsulant. The method of claim 1,
wherein the sealant extends between the first routing die and the first integrated circuit die and the second integrated circuit die, the sealant surrounds the die connectors of the first routing die. The method of claim 1,
and the sealant extends between the first routing die and the first redistribution structure. The method of claim 1,
The first routing die includes:
Board;
an interconnect structure on the substrate comprising the first metallization pattern in one or more dielectric layers; and
and the die connectors of the first routing die electrically coupled to the first metallization pattern of the interconnect structure. 6. The method of claim 5,
The first routing die further includes a through via extending through the substrate, the through via being physically and electrically connected to the first redistribution structure, the first surface of the sealant including the first cultivation physically contacting the one or more dielectric layers of a wire structure, the first surface of the sealant being coplanar with a second surface of the substrate of the first routing die, and the second surface of the substrate of the first routing die being coplanar with the second surface of the substrate of the first routing die. and a surface physically contacts the one or more dielectric layers of the first redistribution structure. In the method,
Forming a first package comprising:
forming an electrical connector over the carrier substrate;
attaching the backside of the first die to the carrier substrate using an adhesive layer, the first die adjacent the electrical connector;
attaching the backside of the second die to the carrier substrate using an adhesive layer, the second die adjacent the first die;
bonding a first routing die to active surfaces of the first and second dies using a die connector on the first routing die, the first routing die electrically coupling the first and second dies and free of active and passive devices, wherein the electrical connector has a surface further away from the top surface of the carrier substrate than any surface of the first routing die is further away from the top surface of the carrier substrate; , bonding the first routing die;
bonding a second routing die to the active surfaces of the first and second dies using a die connector on the second routing die, the second routing die electrically coupling the first and second dies wherein the second routing die is adjacent the first routing die and is free of active and passive devices, the second routing die has a different number of die connectors than the first routing die, wherein the die connectors on the second routing die are bonding the second routing die, the second routing die being a different size than die connectors on the first routing die in a plan view;
sealing the first die, the second die, the first routing die, the second routing die and the electrical connector with a molding compound;
forming a first redistribution structure over the first die, the second die, the first routing die, the second routing die, the molding compound, and the electrical connector; and
forming the first package comprising removing the carrier substrate; and
bonding a second package to the first package using a first set of conductive connectors, the second package proximate the first die and a back surface of the second die; A method comprising In the method,
forming a first die comprising an active side and a back side, wherein forming the first die comprises:
forming a first set and a second set of die connectors on the active side of the first die, the first set of die connectors being shorter than the second set of die connectors; forming said first die comprising forming two sets;
Forming a first package comprising:
forming an electrical connector over the carrier substrate;
adhering the first die to the carrier substrate, the active side facing the back side, the first die adjoining the electrical connector;
adhering a second die to the carrier substrate, the active surface of the second die comprising third and fourth sets of die connectors, the third set of die connectors being greater than the fourth set of die connectors; adhering the second die, the second die being short, the active side facing the back side, and the second die being adjacent the first die;
bonding a routing die to the first and second dies using the first and third sets of die connectors, the routing die comprising a substrate, a through via extending through the substrate, and the substrate and the an interconnect structure on a through via, the interconnect structure comprising a first metallization pattern in one or more dielectric layers, the first metallization pattern electrically coupled to the through via, the die connector of the routing die are electrically connected to the first metallization pattern of the interconnect structure, the routing die is free of active and passive devices, and after bonding the routing die, the electrical connector is connected to any surface of the routing die. bonding the routing die, the routing die having a surface that is further away from the top surface of the carrier substrate than it is remote from the top surface of the carrier substrate;
sealing the first die, the second die, the routing die, and the electrical connector with a molding compound;
forming a redistribution structure over the active side of the first die, the molding compound, and the electrical connector, the redistribution structure comprising a second metallization pattern in one or more dielectric layers, the redistribution structure comprising: a second metallization pattern electrically coupled to the electrical connector and the second and fourth sets of die connectors, the through via of the routing die physically and electrically coupled to the redistribution structure, and the molding compound a first surface of physically contacting the one or more dielectric layers of the redistribution structure, the first surface being coplanar with a second surface of the substrate of the routing die, the second surface of the substrate of the routing die being coplanar with a second surface of the substrate of the routing die forming the redistribution structure, the surface physically contacting the one or more dielectric layers of the redistribution structure; and
forming the first package, including removing the carrier substrate; and
bonding a second package to the first package using a first set of conductive connectors, the second package proximate the back surface of the first and second dies; Including method.

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