CN112038305A - Multi-chip ultrathin fan-out packaging structure and packaging method thereof - Google Patents
Multi-chip ultrathin fan-out packaging structure and packaging method thereof Download PDFInfo
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Abstract
The invention discloses a multi-chip ultrathin fan-out type packaging structure and a packaging method thereof, and belongs to the technical field of semiconductor packaging. An upper metal pad (31) is arranged on the upper surface of a rewiring metal circuit layer (3), a bottom metal pad (33) is arranged on the lower surface of the rewiring metal circuit layer, a chip (8) is fixedly connected with the upper metal pad (31) of the rewiring metal circuit layer (3) through a metal micro-bump (73), underfill (83) fills the bottom of the chip (8) and a chip gap of the same packaging body, and a plastic packaging material (86) is used for plastically packaging the chip (8) above the rewiring metal layer (3) and exposes the back of the chip (8); the reinforced heat dissipation protective layer (63) is arranged on the back surface of the chip (8) through a heat conduction adhesive layer (61). The packaging method realizes the reduction of the thickness of the product, the improvement of the reliability of the product and the realization of a multi-chip packaging structure by wafer-level process forming.
Description
Technical Field
The invention relates to a multi-chip ultrathin fan-out type packaging structure and a packaging method thereof, and belongs to the technical field of semiconductor packaging.
Background
With the development of the electronics industry, high performance chips are increasingly being developed to higher I/O numbers with the background of geometric growth of the number of transistors on a chip due to the reduction of the feature size of the transistors on the chip, and the number of I/O connections is limited by the spreading of I/O connection terminals over the surface area of the chip in conventional flip chip packaging schemes.
The fan-out package is used for guiding I/O from the inside of a chip to the outside of the chip through a rewiring technology, and fanning out high-density I/O into low-density package pins, so that the problem that the packaged chip and a printed circuit board can be interconnected is solved, meanwhile, the package thickness can be greatly reduced, the fan-out package is favorable for being integrated in application scenes such as mobile terminals with increasingly tense space, and is rapidly becoming the choice of ultrathin multi-chip package due to the advantages of high integration degree, good interconnection performance and the like.
Fan-out packages are typically formed by first embedding the back side of a die in epoxy, then forming a dielectric layer and a redistribution layer on the front side of the die and making electrical connections between pads on the front side of the die and the redistribution layer, the redistribution layer rerouting the I/O connections from the die to the peripheral epoxy regions, and then forming solder ball bump structures on the pads of the redistribution layer. The method has certain defects, and the slippage caused by the shrinkage of the injection molding packaging material is difficult to control; the fan-out package adopting the injection molding process is very difficult to control the warpage, and with the reduction of the thickness of the package body, after the package body is connected to the substrate after the warpage is increased, when the heat dissipation module is additionally installed, the line in the area among the multiple chips is deformed, so that the chip interconnection precision is greatly influenced, the reliability of the product package is finally influenced, and the product performance is reduced; increasing package thickness also loses the advantage of thin packages.
Disclosure of Invention
The invention aims to overcome the defect of the strength of the traditional ultrathin fan-out chip packaging structure and provides a multi-chip ultrathin fan-out packaging structure and a packaging method thereof, wherein the multi-chip ultrathin fan-out packaging structure is used for improving the reliability of products and realizing multi-chip packaging and is provided with an integrated heat dissipation structure with a reinforcing structure.
The purpose of the invention is realized as follows:
the invention provides a multi-chip ultrathin fan-out type packaging structure which comprises a plurality of chips, a rewiring metal circuit layer, a reinforced heat dissipation protective layer, underfill and a plastic packaging material, wherein an upper layer metal bonding pad is arranged on the upper surface of the rewiring metal circuit layer, a bottom layer metal bonding pad is arranged on the lower surface of the rewiring metal circuit layer, the chip bonding pad of each chip is provided with a metal micro-bump, each chip is fixedly connected with the upper layer metal bonding pad of the rewiring metal circuit layer through the metal micro-bump and a solder material,
the underfill fills the bottom of the chip and the chip gap, and the plastic package material plastically packages the chip above the rewiring metal layer and exposes the back of the chip;
the reinforced heat dissipation protective layer is arranged on the back surface of the chip through a heat conduction adhesive layer, and is one or a combination of a silicon chip, a glass sheet or a metal sheet;
and a metal connecting piece is arranged on the bottom metal bonding pad of the rewiring metal circuit layer.
Furthermore, the top end of the metal micro-bump also comprises a nickel layer and a gold layer, and the gold layer covers the nickel layer.
Furthermore, the top end of the upper layer metal pad of the rewiring metal circuit layer also comprises a copper layer and a nickel layer, and the nickel layer covers the copper layer.
Furthermore, the metal connecting piece is one or a combination of a plurality of copper columns, metal diffusion layers and solder balls.
Further, the metal sheet is a selenium metal heat sink or a thin copper metal sheet.
The invention also provides a packaging method of the multi-chip ultrathin fan-out type packaging structure, which comprises the following steps:
step one, taking a carrier plate, and coating a composite separation layer on the upper surface of the carrier plate;
forming a rewiring metal circuit layer and a bottom metal pad thereof above the composite separation layer through multiple photoetching, electroplating processes and insulation coating, wherein the rewiring metal circuit layer comprises a plurality of metal layers and an insulation layer with a specified opening position to form an interconnection circuit; then manufacturing an upper metal bonding pad on the upper surface of the rewiring metal circuit layer by a wafer-level metal micro-bump technology;
thirdly, sequentially adopting a flip-chip process and a hot-press welding process, sequentially welding a plurality of chips onto the upper-layer metal bonding pad through a welding tin material, wherein the chip bonding pad of each chip is provided with a metal micro-bump, and one surface of each chip provided with the metal micro-bump is aligned to and welded onto the upper-layer metal bonding pad;
filling the bottom of the chip and the chip gap of the same packaging body with underfill above the rewiring metal circuit layer, and then forming a packaging body, hereinafter referred to as a plastic packaging wafer, by plastic packaging with a plastic packaging material;
step five, integrally thinning the useless plastic package material on the back of the plastic package wafer to a target thickness in a grinding mode, and exposing the silicon surface of the chip;
coating or applying a heat-conducting bonding layer on the whole back surface of the ground plastic package wafer, and covering a preset enhanced heat dissipation protective layer on the whole surface of the heat-conducting bonding layer by adopting a mounting or bonding process;
step seven, thinning the reinforced heat dissipation protective layer through a thinning process;
step eight, separating the composite separation layer and the carrier plate by adopting a laser or mechanical mode, and exposing the rewiring metal circuit layer and the bottom metal bonding pad thereof; arranging a metal connecting piece on the bottom metal pad by a metal micro-bump technology, wherein the metal connecting piece is one or a combination of a copper column, a metal diffusion layer and a tin ball;
and step nine, cutting the plastic package wafer with the reinforcing structure, which is completed through the wafer level process, to form a plurality of independent packaging bodies.
Further, in the first step, the composite separation layer is composed of one or more of a polymer layer, a metal compound layer and a metal thin film layer.
Further, in the second step, the upper metal pad is made of one or more alloys of copper, nickel, tin, gold, tin and silver.
Further, in the sixth step, the heat dissipation enhancing protective layer is one or a combination of a plurality of silicon wafers, glass sheets or metal sheets.
Further, the metal sheet is a selenium metal heat sink or a thin copper metal sheet.
Advantageous effects
1. The invention realizes a single-layer or multi-layer fan-out packaging structure by a wafer-level rewiring metal layer technology and a chip flip technology, so as to ensure that a chip to be packaged, especially a small chip or an ultra-small chip with high pin number and a printed circuit board can realize high-density I/O fan-out into low-density packaging pins, and a substrate, an insert or bottom filling is not needed, so that the whole packaging structure is thinned;
2. the invention adopts the advanced reconstituted wafer packaging technology and the reliable interconnection technology, realizes the multi-chip packaging structure with different functions, and simultaneously avoids the risk of transmission and damage after the thinning of the large-size wafer while thinning the packaging body and additionally installing the back heat dissipation and enhancement structure through the assistance of the carrier plate;
3. the chip to be packaged is embedded in the packaging material by adopting the plastic packaging material, so that the front, the back, the left and the right surfaces and the back of the chip to be packaged are physically and electrically protected, and the reliability of a packaged product is improved;
4. the invention utilizes the back heat radiation structure of the packaging body, and the reinforcing plate serving as the reinforcing structure not only further enhances the strength of the packaging body, reduces the warping degree of the whole packaging structure, but also enhances the heat radiation performance of the chip monomer, and is beneficial to improving the reliability of the packaged product.
5. The invention provides a multi-chip ultrathin fan-out type packaging structure and a packaging method thereof, which improve the reliability of products, realize multi-chip packaging and have an integrated heat dissipation structure with a reinforcing structure.
Drawings
FIG. 1 is a schematic cross-sectional view of an embodiment of a multi-chip ultra-thin fan-out package structure of the present invention;
FIGS. 2A to 2J are schematic views illustrating a manufacturing process of the packaging method of the embodiment of FIG. 1;
description of the main elements
Rewiring metal wiring layer 3
Thermally conductive adhesive layer 61
Enhanced heat dissipation protective layer 63
A metal connector 91.
Detailed Description
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown, so that this disclosure will fully convey the scope of the invention to those skilled in the art. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
Examples
The invention relates to a multi-chip ultrathin fan-out type packaging structure, which is a schematic cross-sectional view of an embodiment of the multi-chip ultrathin fan-out type packaging structure as shown in fig. 1. The invention relates to a multi-chip ultrathin fan-out packaging structure which comprises a plurality of independent chips 8, a rewiring metal circuit layer 3, a reinforced heat dissipation protective layer 63, underfill 83 and a plastic packaging material 86. The rewiring metal circuit layer 3 is a composite layer of three or more metal layers and an insulating layer, the metal layers are made of aluminum Al, copper Cu, nickel Ni, gold Au, a combination thereof or an alloy thereof, and the insulating layer is made of a polymer, including Polybenzoxazole (PBO), Polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like; the line width/line distance is less than 8um/8 um. Preferably, the rewiring metal circuit layer 3 is a high-density rewiring fan-out layer with a line width/line distance as small as 1.5um/1.5 um.
The upper surface of rewiring metal circuit layer 3 sets up upper metal pad 31, the lower surface sets up bottom metal pad 33, the top of rewiring metal circuit layer 3's upper metal pad 31 still includes copper layer and nickel layer, the nickel layer covers on the copper layer. The chip pad 75 of the chip 8 is provided with a metal micro bump 73, and the metal micro bump 73 is usually a micro copper pillar bump. The top of the metal micro-bump 73 further comprises a nickel layer and a gold layer, wherein the gold layer covers the nickel layer to enhance the connection between the chip 8 and the rewiring metal circuit layer 3. The chip 8 is usually a logic chip with different functions using advanced chip processes, such as an application processor, etc., the pitch of the metal micro bumps 73 on the chip 8 is usually 40um to 70um, and the metal micro bumps 73 and the solder 71 are soldered on the upper metal pads 31 of the rewiring metal circuit layer 3 by a flip chip interconnection method. The chip 8 is selectively electrically connected by the rewiring metal wiring layer 3 as an interconnection wiring layer.
The underfill 83 fills the bottom of the chip 8 and the chip gap, and the plastic package material 86 plastically packages the chip 8 above the rewiring metal layer 3 and exposes the back of the chip 8, so that the front, the back, the left and the right of the packaged chip are protected doubly, and the reliability of the packaged product is improved.
The reinforced heat dissipation protective layer 63 is arranged on the back face of the chip 8 through the heat conduction adhesive layer 61, so that the strength of the packaging body is further enhanced, the front face, the back face, the left face, the right face and the back face of the packaged chip are physically and electrically protected, the warping degree of the whole packaging structure is reduced, the heat dissipation performance of the chip 8 is enhanced, and the reliability of a packaged product is improved. The reinforced heat dissipation protective layer 63 is one or a combination of a plurality of silicon wafers, glass sheets or metal sheets; the metal sheet is a metal selenium radiating fin or a metal thin copper sheet.
The bottom metal pad 33 of the rewiring metal wiring layer 3 is provided with a metal connector 91. The metal connecting member 91 is one or a combination of a plurality of copper columns, metal diffusion layers and solder balls, and is used for connecting with a printed circuit board.
The invention relates to a packaging method of a multi-chip ultrathin fan-out packaging structure, which comprises the following steps:
step one, as shown in fig. 2A, a carrier L1 is taken, and a composite separation layer L2 is coated on the upper surface of the carrier L1; the carrier plate L1 can carry a plurality of chips 8 with different functions to be packaged simultaneously, and simultaneously, with the assistance of the carrier plate L1, the transmission damage risk of the thinned large-size wafer is avoided while the packaging body is thinned and the back heat dissipation and enhancement structure is additionally arranged; the composite separation layer L2 is composed of one or more of a polymer layer, a metal compound layer, and a metal thin film layer; carrier plate L1 is generally circular or rectangular with locating reentrants.
Step two, as shown in fig. 2B, a rewiring metal circuit layer 3 and a bottom metal pad 33 thereof are formed above the composite separation layer L2 by multiple photolithography, electroplating processes and insulation coating, the material of the bottom metal pad 33 may be one or several alloys selected from copper, nickel, tin, gold, tin and silver, the rewiring metal circuit layer 3 includes multiple metal layers and an insulation layer with a designated opening position, and an interconnection circuit is formed; then, at a specific position on the surface of the rewiring metal circuit layer 3, an upper metal pad 31 is manufactured by a wafer-level metal micro-bump technology, and the upper metal pad 31 can be made of one or more alloys of copper, nickel, tin, gold and tin-silver; specifically, the top end of the upper metal pad 31 of the rewiring metal wiring layer 3 is sequentially formed with a copper layer and a nickel layer by an electroplating process or a sputtering process, and the nickel layer covers the copper layer.
Step three, as shown in fig. 2C, sequentially soldering a plurality of chips 8 to the upper metal pad 31 through solder 71 by using a flip chip process or a thermocompression bonding method, wherein the chip pad 75 of the chip 8 has a metal micro bump 73, and the surface of the chip 8 having the metal micro bump 73 is aligned and soldered to the upper metal pad 31, and the thickness of the chip 8 is generally 300-700 um at this time; specifically, a nickel layer and a gold layer are sequentially formed on the top of the metal micro-bump 73 by an electroplating process or a sputtering process, and the gold layer covers the nickel layer.
Step four, as shown in fig. 2D and fig. 2E, the underfill 83 is used to fill the bottom of the chip 8 and the chip gap of the same package above the rewiring metal circuit layer 3, and then the package, hereinafter referred to as a plastic package wafer, is formed by plastic package using the plastic package material 86.
And step five, as shown in fig. 2F, the useless plastic package material 86 on the back surface of the plastic package wafer is integrally thinned to a target thickness in a grinding mode, and the silicon surface of the chip 8 is exposed. Usually, after the processing step, the remaining thickness of the chip 8 is 50um to 300 um.
Sixthly, as shown in fig. 2G, coating or applying a heat-conducting bonding layer 61 on the whole back surface of the ground plastic package wafer, wherein the structural thickness of the heat-conducting bonding layer 61 is usually 10-100 um; the whole surface of the heat-conducting adhesive layer 61 is covered with a preset reinforced heat-dissipation protective layer 63 by adopting a mounting or bonding process, the reinforced heat-dissipation protective layer 63 can be one or a combination of a silicon chip, a glass sheet or a metal sheet, and the metal sheet is a metal selenium heat-dissipating sheet or a metal thin copper sheet.
Step seven, as shown in fig. 2H, the enhanced heat dissipation protection layer 63 is thinned by a thinning process, so that the thickness of the whole package is 300-800 um (without the carrier L1), and the size of the package is generally 100 mm or more.
Step eight, as shown in fig. 2I, separating the composite separation layer L2 and the carrier plate L1 by laser or mechanical means, exposing the rewiring metal circuit layer 3 and the bottom metal pad 33 thereof; the metal connecting piece 91 is arranged on the bottom layer metal pad 33 through a metal micro-bump technology, and the metal connecting piece 91 can be one or a combination of a plurality of copper columns, metal diffusion layers and tin balls and can be directly welded on a Printed Circuit Board (PCB).
Step nine, as shown in fig. 2J, the plastic package wafer with the reinforcing structure completed by the wafer level process is cut to form a plurality of independent packages.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A multi-chip ultrathin fan-out type packaging structure is characterized by comprising a plurality of chips (8), a rewiring metal circuit layer (3), a reinforced heat dissipation protective layer (63), bottom filling glue (83) and a plastic packaging material (86), wherein an upper metal pad (31) is arranged on the upper surface of the rewiring metal circuit layer (3), a bottom metal pad (33) is arranged on the lower surface of the rewiring metal circuit layer, a chip pad (75) of each chip (8) is provided with a metal micro-bump (73), each chip (8) is fixedly connected with the upper metal pad (31) of the rewiring metal circuit layer (3) through the metal micro-bump (73) and a soldering tin material (71),
the underfill (83) fills the bottom of the chip (8) and the chip gap, and the plastic package material (86) is used for plastically packaging the chip (8) above the rewiring metal layer (3) and exposing the back surface of the chip (8);
the reinforced heat dissipation protective layer (63) is arranged on the back of the chip (8) through a heat conduction adhesive layer (61), and the reinforced heat dissipation protective layer (63) is one or a combination of a plurality of silicon wafers, glass sheets or metal sheets;
and a metal connecting piece (91) is arranged on the bottom metal pad (33) of the rewiring metal circuit layer (3).
2. The three-dimensional fan-out package structure of claim 1, wherein the top of the metal micro-bumps (73) further comprise a nickel layer and a gold layer, the gold layer overlying the nickel layer.
3. The three-dimensional fan-out package structure according to claim 1, wherein the top of the upper metal pad (31) of the rewiring metal wiring layer 3 further comprises a copper layer and a nickel layer, the nickel layer covering the copper layer.
4. The package structure of claim 1, wherein the metal connecting member (91) is one or a combination of copper pillar, metal diffusion layer and solder ball.
5. The three-dimensional fan-out package structure of claim 1, wherein the metal sheet is a selenium heat sink or a thin copper sheet.
6. A packaging method of a multi-chip ultrathin fan-out packaging structure comprises the following steps:
step one, a piece of carrier plate (L1) is taken, and a composite separation layer (L2) is coated on the upper surface of the carrier plate;
step two, forming a rewiring metal circuit layer (3) and a bottom metal pad (33) thereof above the composite separation layer (L2) through multiple photoetching, electroplating processes and insulation coating, wherein the rewiring metal circuit layer (3) comprises a plurality of metal layers and an insulation layer with a specified opening position to form an interconnection circuit; then an upper metal bonding pad (31) is manufactured on the upper surface of the rewiring metal circuit layer (3) through a wafer-level metal micro-bump technology;
thirdly, sequentially adopting a flip-chip process and a thermal compression bonding process to sequentially bond the plurality of chips (8) to the upper-layer metal bonding pad (31), wherein the chip bonding pad (75) of each chip (8) is provided with a metal micro-bump (73), and one surface of each chip (8) provided with the metal micro-bump (73) is aligned and bonded to the upper-layer metal bonding pad (31);
filling the bottom of a chip (8) and a chip gap of the same packaging body with underfill (83) above the rewiring metal circuit layer (3), and then forming a packaging body, hereinafter referred to as a plastic packaging wafer, by plastic packaging with a plastic packaging material (86);
step five, integrally thinning the useless plastic package material (86) on the back of the plastic package wafer to a target thickness in a grinding mode, and exposing the silicon surface of the chip (8);
coating or applying a heat-conducting bonding layer (61) on the whole back surface of the ground plastic package wafer, and covering a preset reinforced heat dissipation protective layer (63) on the whole surface of the heat-conducting bonding layer (61) by adopting a mounting or bonding process;
step seven, thinning the reinforced heat dissipation protective layer (63) through a thinning process;
eighthly, separating the composite separation layer (L2) and the carrier plate (L1) by adopting a laser or mechanical mode, and exposing the rewiring metal circuit layer (3) and the bottom metal bonding pad (33) thereof; arranging a metal connecting piece (91) on the bottom layer metal pad (33) by a metal micro-bump technology, wherein the metal connecting piece (91) is one or a combination of a copper column, a metal diffusion layer and a tin ball;
and step nine, cutting the plastic package wafer with the reinforcing structure, which is completed through the wafer level process, to form a plurality of independent packaging bodies.
7. The encapsulation method according to claim 6, wherein in the first step, the composite separation layer (L2) is composed of one or more of a polymer layer, a metal compound layer, and a metal thin film layer.
8. The packaging method according to claim 7, wherein in the second step, the material of the upper metal pad (31) is one or more of copper, nickel, tin, gold, tin-silver, and their alloys.
9. The packaging method according to claim 8, wherein in the sixth step, the reinforced heat dissipation protective layer (63) is one or a combination of silicon wafer, glass sheet or metal sheet.
10. The packaging method of claim 9, wherein the metal sheet is a selenium heat sink or a thin copper sheet.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113178394A (en) * | 2021-04-28 | 2021-07-27 | 浙江集迈科微电子有限公司 | Chip mounting process for reducing stress |
| CN113327899A (en) * | 2021-04-22 | 2021-08-31 | 成都芯源系统有限公司 | Flip chip packaging unit and packaging method |
| CN114975405A (en) * | 2022-05-27 | 2022-08-30 | 盛合晶微半导体(江阴)有限公司 | Wafer packaging system and preparation method thereof |
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2020
- 2020-10-12 CN CN202011084019.0A patent/CN112038305A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113327899A (en) * | 2021-04-22 | 2021-08-31 | 成都芯源系统有限公司 | Flip chip packaging unit and packaging method |
| CN113178394A (en) * | 2021-04-28 | 2021-07-27 | 浙江集迈科微电子有限公司 | Chip mounting process for reducing stress |
| CN113178394B (en) * | 2021-04-28 | 2023-06-27 | 浙江集迈科微电子有限公司 | Chip mounting technology for reducing stress |
| CN114975405A (en) * | 2022-05-27 | 2022-08-30 | 盛合晶微半导体(江阴)有限公司 | Wafer packaging system and preparation method thereof |
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