CN105655320B - Low-cost chip back silicon through hole interconnection structure and preparation method thereof - Google Patents
Low-cost chip back silicon through hole interconnection structure and preparation method thereof Download PDFInfo
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- CN105655320B CN105655320B CN201610015756.2A CN201610015756A CN105655320B CN 105655320 B CN105655320 B CN 105655320B CN 201610015756 A CN201610015756 A CN 201610015756A CN 105655320 B CN105655320 B CN 105655320B
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Abstract
The invention discloses a kind of low-cost chip back silicon through hole interconnection structure and preparation method thereof；The interconnection structure includes the chip that at least one front has weld pad, and chip back is formed with the through-hole of corresponding weld pad, and the bottom opening exposure weld pad and size of through-hole are less than the size of weld pad；Insulating layer is covered on the side wall of chip back and through-hole；Certain thickness metal layer is formed with using the method for changing plating on the weld pad surface of the bottom opening exposure of through-hole；Method in through-hole using electroless coating, which is filled out, is filled with conductive material.The present invention can avoid using deep hole physical vapour deposition (PVD) and Deep hole electroplating woth no need to change plating through-silicon via sidewall, have at low cost, simple process and high reliability.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, are specifically related to a kind of low-cost chip back interconnecting silicon through holes knot
Structure and preparation method thereof.
Background technique
With Internet of Things, intelligent mobile terminal miniaturization, multifunction demand, it is three-dimensionally integrated, it is logical to be based particularly on silicon
The Wafer level packaging in hole (TSV) plays the part of more and more important role.
Chinese patent 201520550505.5 proposes that a kind of silicon through hole interconnection structure, including silicon substrate and several silicon lead to
Semiconductor technology layer is arranged in hole, the upper surface of described silicon substrate, and the through silicon via runs through silicon substrate up and down, and fills metal and form gold
Belong to column, the metal column and semiconductor technology layer form electrical communication, be arranged between the metal column and the inner wall of through silicon via blunt
Change layer I, metal block is set in the lower surface of metal column and passivation layer, through silicon via is completely covered metal block, in metal block week
It encloses and covers passivation layer II with the lower surface of silicon substrate, and the lower surface that metal block opening exposes metal block is set, in passivation layer II
Upper selective rewiring metal layer, and in the surface protective mulch of interconnection metal layer again, open up protective layer opening, the program
It can be good at exposing metal column using electrical leakage problems caused by chemical-mechanical polishing before solving, while improving encapsulation
Reliability.But the complex process, at high cost, the structure for not being metal column is no longer applicable in.
Chinese patent 201210570600.2 discloses a kind of method for filling through hole based on electroless nickel alloy and its answers
With through-hole being prepared on matrix first, then directly or indirectly through the method system of chemical plating in the sidewall surfaces of through-hole
Standby electroless nickel alloy coatings, then plating filling is carried out using electroless nickel alloy coatings as seed layer.The present invention proposes that one kind passes through
Barrier layer and seed layer may be implemented in technology of the electroless nickel alloy as the barrier layer of through-hole and the seed layer of plating, this technology
Integration, can simplify traditional process flow, greatly save cost；By the method for chemical plating, in the logical of high aspect ratio
Plated film distribution can be made more uniform in hole, " blind area " for effectively avoiding ion sputtering method from generating, this help to obtain completely
Plating filling effect.This method is used for the interconnecting silicon through holes technology of microelectronics three-dimension packaging, or is used for glass or resin base
The through-hole interconnection technique of body, but being also required to of the through-hole side wall plating in the technology, increase the difficulty of technique, reliability compared with
It is low.
Through-hole (Via last) technology is lower-cost scheme in through silicon via technology afterwards.Main processing step includes core
The techniques such as ball are planted in piece thinning back side, silicon etching, the silicon back side and side wall insulating layer preparation, weld pad dielectric layer opening, metal filling.
But semi-conductor industry development under the premise of pursuing guarantee reliability, reduces cost always.Through-hole technology is also required to further afterwards
Reduce cost.
Currently, the main height being longitudinally superimposed by reducing 3D, and hole depth needed for reducing TSV, it is TSV manufacturing technology
Using obstacle is reduced, cost is reduced.From reducing in terms of cost angle, the deep hole physical vapor of rear through-hole (Via last) technology is heavy
Product, plating, it is main cost structure that the back side is routed again.In addition, the through-silicon via structure that rear through-hole (Via last) technology is formed
It is usually to be partially filled with mode, bottom hole and weld pad coupling part are relatively thin, the problems such as be easy to causeing layering, be broken, and without dielectric layer
Filling protection will lead to the oxidation of metal, fail caused by corrosion and stress.
Summary of the invention
In order to solve the deep hole physical vapour deposition (PVD) of Via last through silicon via, plating, the cost that the back side is routed again is excessively high, with
And bring technical problem and reliability above-mentioned technical problem are filled in weld pad connection and hole, the present invention proposes a kind of inexpensive core
Piece back silicon through hole interconnection structure and preparation method thereof woth no need to change plating through-silicon via sidewall, and can avoid using deep hole physics gas
Mutually deposition and Deep hole electroplating have at low cost, simple process and high reliability.
The technical scheme of the present invention is realized as follows:
A kind of low-cost chip back silicon through hole interconnection structure has the chip of weld pad, the core including at least one front
The piece back side is formed with the through-hole of the corresponding weld pad, and the bottom opening exposure weld pad and size of the through-hole are less than the weldering
The size of pad；Insulating layer is covered on the side wall of the chip back and the through-hole；The bottom opening exposure of the through-hole
Certain thickness metal layer is formed with using the method for changing plating on weld pad surface；It is filled in the through-hole using the method for electroless coating
Conductive material is expired.
Further, the material of the weld pad is one of aluminium, aluminium alloy, copper and copper alloy.
Further, it the weld pad front portion or is all covered by inorganic dielectric layer or organic polymer dielectric layer, institute
Weld pad dorsal edge is stated to be covered by inorganic dielectric layer.
Further, the material of the insulating layer is one of silica, silicon nitride, insulating material of polymer.
Further, the through-hole is the combination of straight hole or inclined hole or straight hole and inclined hole.
Further, the metal layer is one layer of structure or multilayered structure, every layer of material be nickel, nickel phosphorus, silver, copper, cobalt,
One of gold, palladium.
Further, the thickness of the metal layer is greater than 0.2 micron.
Further, the conductive material filled in the through-hole protrudes the back side of the chip, forms salient point.
A kind of preparation method of low-cost chip back silicon through hole interconnection structure, includes the following steps:
A, a wafer including an at least chip is provided, the chip front side has weld pad and dielectric layer, and the weld pad is embedding
Enter in the dielectric layer, the front of the chip is bonded together with a slide glass；
B, the chip back is thinned, passes through the chip back of photoetching process after bonding position system corresponding with weld pad
Make through-hole, the bottom opening of the through-hole exposes the dielectric layer；
C, a layer insulating is deposited in the chip back and the through-hole；
D, the insulating layer and dielectric layer for etching the via bottoms, expose the corresponding weld pad back side of the through-hole；
E, in the weld pad back side plating metal of the via bottoms, metal layer is formed；
F, full conductive material is filled in the through-hole, and the conductive material of filling is made to protrude the back side of the chip, shape
At salient point；
G, scribing.
Further, the preparation of the insulating layer is deposited using low temperature chemical vapor or polymer sprays or polymer spin coating
Method.
Further, etching is plasma dry etch in step d.
Further, after the conductive material is by reflux filling formation after plant ball or by the filling that flows back after Solder-Paste Printing
It is formed by curing.
Further, the conductive material is formed by curing after being filled by conducting resinl printing process or by conducting resinl dispensing
It is formed by curing after method filling.
Further, chip is torn open before scribing with slide glass and is bonded, then chip cleaned, scribing.
The beneficial effects of the present invention are:
The present invention provides a kind of chip back silicon through hole interconnection structure, passes through the weld pad table of the bottom opening exposure in through-hole
Certain thickness metal layer is formed using the method for changing plating on face, and by using the method filling of electroless coating completely to lead in through-hole
The reliability that conductive material is connect with weld pad can be enhanced in electric material, and solution is partially filled with bottom hole and weld pad coupling part is relatively thin,
Caused by layering, fracture the problems such as；Since preparation method only changes the side wall for having plated through silicon via bottom without changing plating through silicon via,
Therefore, the difficulty of technique is greatly reduced, reliability is higher；And conductive material is using the solder reflux filling of electroless coating or conduction
Offset printing brush/dispensing fills to be formed, and avoids using deep hole physical vapour deposition (PVD) and Deep hole electroplating, greatly reduces rear through-hole (Via
Last) the process costs of technology, therefore, the present invention have at low cost, simple process and high reliability.
Detailed description of the invention
Fig. 1 is the structural schematic diagram after wafer of the present invention is bonded with slide glass；
Fig. 2 is the structural schematic diagram that the present invention corresponds to bond pad locations etching through silicon via in backside of wafer；
Fig. 3 prepares the structural schematic diagram of insulating layer in backside of wafer whole face for the present invention；
Fig. 4 is present invention etching removal via bottoms insulating layer and dielectric layer, exposes the structural schematic diagram at the weld pad back side；
Fig. 5 is structural schematic diagram of the present invention in via bottoms weld pad back side metal cladding；
Fig. 6 be the present invention using solder flow back or conductive paste in the way of filling silicon through holes structural schematic diagram；
Fig. 7 wafer of the present invention be bonded with slide glass solution after structural schematic diagram；
Fig. 8 is structural schematic diagram when through silicon via is inclined hole in the present invention；
Fig. 9 is an application example structural schematic diagram of the invention；
Figure 10 is another application exemplary construction schematic diagram of the present invention；
1- chip, 2- weld pad, 3- through-hole, 4- insulating layer, 5- metal layer, 6- conductive material, 7- dielectric layer, 8- slide glass, 9-
It is bonded glue, 10-cavitys, 11- cover board
Specific embodiment
It is more understandable to enable the invention to, a specific embodiment of the invention is done specifically with reference to the accompanying drawing
It is bright.For convenience of description, each component part does not press normal rates scaling in the structure of embodiment attached drawing, therefore does not represent each in embodiment
The practical relative size of structure.
As shown in fig. 7, a kind of low-cost chip back silicon through hole interconnection structure, including at least one front with weld pad 2
Chip 1, the chip back are formed with the through-hole 3 of the corresponding weld pad, the bottom opening exposure weld pad of the through-hole and
Size is less than the size of the weld pad；Insulating layer 4 is covered on the side wall of the chip back and the through-hole；The through-hole
Certain thickness metal layer 5 is formed with using the method for changing plating on the weld pad surface of bottom opening exposure；It is used in the through-hole
The method of electroless coating, which is filled out, is filled with conductive material 6.In this way, being changed by being used on the weld pad surface of the bottom opening of through-hole exposure
The method of plating forms certain thickness metal layer, and the method by using electroless coating in through-hole fills full conductive material, can
To enhance the reliability that conductive material is connect with weld pad, solution is partially filled with bottom hole and weld pad coupling part is relatively thin, caused by divide
The problems such as layer, fracture；Since preparation method only changes the side wall for having plated through silicon via bottom without changing plating through silicon via, greatly
The difficulty of technique is reduced greatly, and reliability is higher；And conductive material using electroless coating solder reflux filling or conducting resinl printing/
Dispensing fills to be formed, and avoids using deep hole physical vapour deposition (PVD) and Deep hole electroplating, greatly reduces rear through-hole (Via last)
The process costs of technology, therefore, the present invention have at low cost, simple process and high reliability.
Preferably, the depth of the through-hole is to expose chip pad not through chip pad, to avoid etching chip
Weld pad is excessive, causes integrity problem.
Preferably, the material of the weld pad is one of aluminium, aluminium alloy, copper and copper alloy.
Preferably, it the weld pad front portion or is all covered by inorganic dielectric layer or organic polymer dielectric layer, it is described
Weld pad dorsal edge is covered by inorganic dielectric layer.
Preferably, the material of the insulating layer is one of silica, silicon nitride, insulating material of polymer.
Preferably, the through-hole is the combination of straight hole or inclined hole or straight hole and inclined hole.Conductive through hole in the present embodiment is
Straight hole, i.e., through-hole side wall is perpendicular to chip back.In other embodiments, referring to Fig. 8, through-hole is inclined hole, and hole chip without leave
Weld pad is sequentially increased to chip back, i.e., through-hole side wall is not orthogonal to chip back, and it is vertical that the benefit of inclined hole is that of avoiding production
The process complexity of through-hole, simple process, cost is relatively low.
Preferably, the metal layer is one layer of structure or multilayered structure, every layer of material be nickel, nickel phosphorus, silver, copper, cobalt,
One of gold, palladium.More preferably, the outermost metal of the metal layer is the metal with anti-oxidation effect, such as one in silver, gold, palladium
Kind, it is also possible that lower with the resistance of conductive material (conducting resinl or solder).
Preferably, the thickness of the metal layer is greater than 0.2 micron.The thickness be enhance conductive material connect with weld pad can
By the preferred forms of property, being not excluded for other thickness certainly may.
Preferably, the conductive material filled in the through-hole protrudes the back side of the chip, forms salient point, is used for and outside
The tie point of device electrical connection.
Referring to Fig. 1 to Fig. 7, a kind of preparation method of low-cost chip back silicon through hole interconnection structure includes the following steps:
A, referring to Fig. 1, a wafer including an at least chip 1 is provided, the chip front side has weld pad 2 and dielectric layer 7,
The weld pad is embedded in the dielectric layer, and the back side of the chip and a slide glass 8 are temporarily bonded together；
Preferably, wafer is combined with slide glass by being temporarily bonded glue.
B, through-hole 3, institute referring to fig. 2, are made by the chip back of photoetching process after bonding position corresponding with weld pad
The bottom opening for stating through-hole exposes the dielectric layer；Preferably, the conductive through hole in the present embodiment is perpendicular to chip.
C, referring to Fig. 3, a layer insulating 4 is deposited in the chip back and the through-hole；The material of insulating layer can be with
It is inorganic insulating material such as silica or organic Jie's insulating materials.
D, the insulating layer and dielectric layer for referring to fig. 4, etching the via bottoms expose the corresponding weld pad back of the through-hole
Face；
E, metal layer 5 is formed in the weld pad back side plating metal of the via bottoms referring to Fig. 5；Change plating metal be nickel,
One or more of nickel phosphorus, silver, copper, cobalt, gold, palladium.Preferably, which is the gold with anti-oxidation effect
Belong to, one of such as silver, gold, palladium；It is also possible that lower with the resistance of conducting resinl or solder.
F, referring to Fig. 6, full conductive material 6 is filled in the through-hole, and the conductive material of filling is made to protrude the chip
The back side, formed salient point.
G, disk is torn open with slide glass and is bonded, and cleans to chip, scribing.
Preferably, the preparation of the insulating layer is using low temperature chemical vapor deposition or polymer spraying or polymer spin coating
Method.
Preferably, etching is plasma dry etch in step d.
Preferably, the conductive material is formed or by reflux filling after planting ball by solid after reflux filling after Solder-Paste Printing
Change and is formed.
Preferably, the conductive material is formed by curing after being filled by conducting resinl printing process or by conducting resinl dispensing side
It is formed by curing after method filling.
As shown in figure 9, being an application example structural schematic diagram of low-cost chip back of the present invention silicon through hole interconnection structure；
Chip front side combines after being bonded with slide glass solution with a cover board, forms a kind of MEMS chip encapsulating structure with cavity；Its
In, there is cover board protection and sealing function, through-hole to be perpendicular to the straight hole of chip back.
As shown in Figure 10, illustrate for the another application exemplary construction of low-cost chip back of the present invention silicon through hole interconnection structure
Figure, wherein through-hole is the inclined hole for being not orthogonal to chip back.
Above embodiments are referring to attached drawing, to a preferred embodiment of the present invention will be described in detail.Those skilled in the art
Member by above-described embodiment carry out various forms on modification or change, but without departing substantially from essence of the invention in the case where, all
It falls within the scope and spirit of the invention.
Claims (14)
1. a kind of low-cost chip back silicon through hole interconnection structure, it is characterised in that: including at least one front with weld pad (2)
Chip (1), the chip back are formed with the through-hole (3) of the corresponding weld pad, the bottom opening exposure weldering of the through-hole
Pad and size are less than the size of the weld pad；Insulating layer (4) are covered on the side wall of the chip back and the through-hole；It is described
Certain thickness metal layer (5) are formed with using the method for changing plating on the weld pad surface of the bottom opening exposure of through-hole；It is described logical
Method in hole using electroless coating, which is filled out, is filled with conductive material (6).
2. low-cost chip back according to claim 1 silicon through hole interconnection structure, it is characterised in that: the material of the weld pad
Matter is one of aluminium, aluminium alloy, copper and copper alloy.
3. low-cost chip back according to claim 1 silicon through hole interconnection structure, it is characterised in that: the weld pad front
It is partly or entirely covered by inorganic dielectric layer or organic polymer dielectric layer, the weld pad dorsal edge is covered by inorganic dielectric layer
Lid.
4. low-cost chip back according to claim 1 silicon through hole interconnection structure, it is characterised in that: the insulating layer
Material is one of silica, silicon nitride, insulating material of polymer.
5. low-cost chip back according to claim 1 silicon through hole interconnection structure, it is characterised in that: the through-hole is straight
The combination of hole or inclined hole or straight hole and inclined hole.
6. low-cost chip back according to claim 1 silicon through hole interconnection structure, it is characterised in that: the metal layer is
One layer of structure or multilayered structure, every layer of material are one of nickel, nickel phosphorus, silver, copper, cobalt, gold, palladium.
7. low-cost chip back according to claim 1 silicon through hole interconnection structure, it is characterised in that: the metal layer
Thickness is greater than 0.2 micron.
8. low-cost chip back according to claim 1 silicon through hole interconnection structure, it is characterised in that: filled out in the through-hole
The conductive material filled protrudes the back side of the chip, forms salient point.
9. a kind of preparation method of low-cost chip back silicon through hole interconnection structure, which comprises the steps of:
A, a wafer including an at least chip (1) is provided, the chip front side has weld pad (2) and dielectric layer (7), the weldering
Pad is embedded in the dielectric layer, and the front of the chip is bonded together with a slide glass (8)；
B, the chip back is thinned, is made by the chip back of photoetching process after bonding position corresponding with weld pad logical
Hole (3), the bottom opening of the through-hole expose the dielectric layer；
C, it is deposited in the chip back and the through-hole layer insulating (4)；
D, the insulating layer and dielectric layer for etching the via bottoms, expose the corresponding weld pad back side of the through-hole；
E, it in the weld pad back side plating metal of the via bottoms, is formed metal layer (5)；
F, full conductive material (6) are filled in the through-hole, and the conductive material of filling is made to protrude the back side of the chip, formed
Salient point；
G, scribing.
10. the preparation method of low-cost chip back according to claim 9 silicon through hole interconnection structure, it is characterised in that:
The preparation of the insulating layer is using low temperature chemical vapor deposition or the method for polymer spraying or polymer spin coating.
11. the preparation method of low-cost chip back according to claim 9 silicon through hole interconnection structure, it is characterised in that:
Etching is plasma dry etch in step d.
12. the preparation method of low-cost chip back according to claim 9 silicon through hole interconnection structure, it is characterised in that:
The conductive material is formed or by reflux filling after planting ball by being formed by curing after the filling that flows back after Solder-Paste Printing.
13. the preparation method of low-cost chip back according to claim 9 silicon through hole interconnection structure, it is characterised in that:
The conductive material is formed by curing after being filled by conducting resinl printing process or solidifies shape after filling by adhesive dots gluing method
At.
14. the preparation method of low-cost chip back according to claim 9 silicon through hole interconnection structure, it is characterised in that:
Chip is torn open with slide glass before scribing and is bonded, then chip is cleaned, scribing.
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106711105A (en) * | 2017-03-01 | 2017-05-24 | 华天科技（昆山）电子有限公司 | Packaging structure covering metal layer filling hole or slot and manufacturing method |
| CN107644839B (en) | 2017-08-31 | 2018-10-02 | 长江存储科技有限责任公司 | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage |
| US10679941B2 (en) | 2017-08-31 | 2020-06-09 | Yangtze Memory Technologies Co., Ltd. | Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof |
| CN110783264A (en) * | 2019-10-31 | 2020-02-11 | 长江存储科技有限责任公司 | Wafer protection structure and protection method |
| CN111370375A (en) * | 2020-03-23 | 2020-07-03 | 苏州晶方半导体科技股份有限公司 | Packaging structure, semiconductor device and packaging method |
| CN113903706A (en) * | 2021-10-29 | 2022-01-07 | 苏州晶方半导体科技股份有限公司 | Manufacturing method of wafer-level through silicon via packaging structure and through silicon via packaging structure |
| CN114883251A (en) * | 2022-04-29 | 2022-08-09 | 华进半导体封装先导技术研发中心有限公司 | Method for filling dielectric layer of straight-hole silicon through hole |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102496605A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Wafer level packaging structure |
| CN104269362A (en) * | 2014-09-10 | 2015-01-07 | 南通富士通微电子股份有限公司 | Manufacturing method for through silicon via metal column back face protruding blocks |
| CN104617035A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor device |
| CN105047629A (en) * | 2010-03-19 | 2015-11-11 | 精材科技股份有限公司 | Image sensor package and fabrication method thereof |
| CN205335254U (en) * | 2016-01-11 | 2016-06-22 | 华天科技（昆山）电子有限公司 | Low -cost chip back silicon through -hole interconnect structure |
-
2016
- 2016-01-11 CN CN201610015756.2A patent/CN105655320B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047629A (en) * | 2010-03-19 | 2015-11-11 | 精材科技股份有限公司 | Image sensor package and fabrication method thereof |
| CN102496605A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Wafer level packaging structure |
| CN104617035A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor device |
| CN104269362A (en) * | 2014-09-10 | 2015-01-07 | 南通富士通微电子股份有限公司 | Manufacturing method for through silicon via metal column back face protruding blocks |
| CN205335254U (en) * | 2016-01-11 | 2016-06-22 | 华天科技（昆山）电子有限公司 | Low -cost chip back silicon through -hole interconnect structure |
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