CN106129023A - The fan-out packaging structure of two-sided attachment and method for packing - Google Patents

The fan-out packaging structure of two-sided attachment and method for packing Download PDF

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Publication number
CN106129023A
CN106129023A CN201610768360.5A CN201610768360A CN106129023A CN 106129023 A CN106129023 A CN 106129023A CN 201610768360 A CN201610768360 A CN 201610768360A CN 106129023 A CN106129023 A CN 106129023A
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Prior art keywords
chip
pad
fan
silicon substrate
metal
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Inventor
于大全
肖智轶
黄真瑞
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Huatian Technology Kunshan Electronics Co Ltd
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Huatian Technology Kunshan Electronics Co Ltd
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Priority to CN201610768360.5A priority Critical patent/CN106129023A/en
Publication of CN106129023A publication Critical patent/CN106129023A/en
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Abstract

The present invention discloses fan-out packaging structure and the method for packing thereof of a kind of two-sided attachment, front is contained conductive pad and the chip buried in the subsidence trough of silicon substrate first surface of pad is contained at the back side, and with the first metal, the conductive pad in front is rerouted extraction；Making through hole at silicon substrate second surface and expose the pad of chip back at the bottom of subsidence trough, and reroute extraction with the second metal, during wherein the first metal rewiring or the second metal reroute, at least a circuit extends on the silicon substrate surface outside chip area.This encapsulating structure is as the two-sided fan-out package body having ball structure, it is provided that preferably the encapsulation of 3D wafer scale fan-out selects.

Description

The fan-out packaging structure of two-sided attachment and method for packing
Technical field
The present invention relates to a kind of field of semiconductor package, especially relate to fan-out packaging structure and the envelope of a kind of two-sided attachment Dress method.
Technical background
Fan-out WLP is the embedded encapsulation of a kind of wafer level processing, is also that I/O number is more, good main of integrated motility One of Advanced Packaging, and the multi-chip that it can realize vertically and horizontally in a package without substrate is integrated, institute With, current fan-out WLP technology is just towards such as multi-chip, thin encapsulation and these encapsulation of future generation of 3D SiP (system in package) Direction is developed.In order to meet ever-increasing interconnection pitch mismatch, add have difference in functionality various chips and with Reduce package dimension under the area occupied of sample, need to develop new 3D wafer scale fan-out encapsulation solution.
Summary of the invention
The present invention is for meeting above-mentioned challenge, it is provided that the fan-out packaging structure of a kind of two-sided attachment and method for packing thereof.
The technical scheme is that and be achieved in that:
A kind of fan-out packaging structure of two-sided attachment, including silicon substrate and chip, described silicon substrate have first surface and Second surface corresponding thereto, described first surface is formed at least one subsidence trough towards second surface, and at least one Individual described chip back mounts the bottom land of described subsidence trough down, and described chip front side includes conductive pad；Described chip Fill with first medium layer between all sides and described subsidence trough sidewall；It is formed in described chip front side and described first surface Second dielectric layer；The first metal weight cloth that at least one of which is connected it is formed with the conductive pad of described chip in described second dielectric layer Line, one layer of first metal of outermost reroutes and is coated with the first passivation layer；Described chip back or described subsidence trough bottom land set There is pad described in pad and be carved with through hole between described second surface；The 3rd dielectric layer it is formed with on described second surface；Described The second metal rewiring that at least one of which electrically connects, outermost one it is formed with described pad on 3rd dielectric layer and in described through hole Layer the second metal reroutes and is coated with the second passivation layer；Wherein said first metal reroutes or described second metal reroutes In at least a circuit extend on the silicon substrate surface outside described chip area.
Further, described pad is: chip back itself includes pad, or in the conduction by described chip front side Pad electrically causes the pad formed on the metallic circuit of described chip back, or is electrically being drawn by the conductive pad of described chip front side The pad formed to the metallic circuit of described subsidence trough bottom land.
Further, the distance between sidewall and the described chip of described subsidence trough is more than 1 micron.
Further, the difference in height between the first surface of described chip front side and described silicon substrate is less than 50 microns.
Further, the material of described first medium layer and described second dielectric layer is polymer latex.
Further, described first metal reroutes and/or described second metal reroutes upper connection and has soldered ball/salient point.
Further, described chip back installs to the bottom land of described subsidence trough by cohering sticker, described in cohere glue Thickness is less than 50 microns, more than 1 micron.
Further, cohering glue described in is polymer latex.
Further, the number of chips of same subsidence trough is imbedded more than or equal to 2.
The method for packing of the fan-out packaging structure of a kind of two-sided attachment, comprises the following steps:
A. provide one to have first surface and second surface silicon substrate disk corresponding thereto, described first surface is formed Having at least one subsidence trough towards second surface, at least one chip back mounts the groove of described subsidence trough down The end, described chip front side includes conductive pad, and described chip back includes pad；Described chip front side and described silicon substrate the One flush or close to concordant, the conductive pad of described chip front side is rerouted by the first metal formed in chip front side and draws Going out, at least one the first metals reroute and extend on silicon substrate first surface；Described chip back is by cohering gluing being attached to On the bottom land of described subsidence trough；
B. on described silicon substrate disk second surface, the position of corresponding chip back pad carries out through hole；
C. on the described silicon substrate disk second surface and described through-hole wall makes and connects described chip back pad Second metal reroutes；
D. silicon substrate disk is carried out scribing, forms the fan-out packaging structure of single slice two-sided attachment.
The Advantageous Effects of the present invention is as follows:
The fan-out packaging structure of the two-sided attachment of the present invention and method for packing thereof, use embedment silicon substrate fan-out encapsulation technology, Improve I/O density；Form Double-face adhesive assembling structure and carry out chip-stacked, it is not necessary to keyset, reduce the height of overall package body Degree, the thermal coefficient of expansion of this encapsulating structure is more much smaller than substrate simultaneously, and after encapsulating structure welding, reliability improves；Silicon substrate heat conduction Property is good, enhances the heat dispersion of chip.This encapsulating structure is as the two-sided fan-out package body having ball structure, it is provided that more Good 3D wafer scale fan-out encapsulation selects.
Accompanying drawing explanation
Fig. 1 a is the generalized section of chips one embodiment of the present invention；
Fig. 1 b is the generalized section of another embodiment of chips of the present invention；
Fig. 2 is the encapsulating structure generalized section after one embodiment of the invention step A embedment chip；
Fig. 3 is the encapsulating structure generalized section after one embodiment of the invention step B makes through hole；
Fig. 4 is that the encapsulating structure section after one embodiment of the invention step C makes the second metal rewiring in through hole shows It is intended to；
Fig. 5 is that the encapsulating structure section after one embodiment of the invention makes soldered ball/salient point on the second metal reroutes shows It is intended to；
Fig. 6 is the fan-out packaging structure generalized section of the two-sided attachment of one embodiment of the invention；
Fig. 7 is the fan-out packaging structure generalized section of the two-sided attachment of another embodiment of the present invention；
In conjunction with accompanying drawing, make the following instructions:
100 silicon substrate 101 first surfaces
102 second surface 200 chips
201 conductive pad 202 pads
203 metallic circuits
300 through holes 1 cohere glue
2 first medium layer 3 second mediums
4 first metals reroute 5 first passivation layers
6 first soldered ball/the first salient point 7 the 3rd dielectric layers
8 second metals reroute 9 second passivation layers
10 second soldered ball/the second salient points
Detailed description of the invention
In order to be more clearly understood that the technology contents of the present invention, describing in detail especially exemplified by following example, its purpose is only It is to be best understood from present disclosure rather than limits the scope of the invention.Each ingredient in the structure of embodiment accompanying drawing Do not press normal rates scaling, therefore do not represent the actual relative size of each structure in embodiment.
Embodiment 1
As shown in Figure 6, the fan-out packaging structure of a kind of two-sided attachment, including silicon substrate 100 and chip 200, chip front side Including conductive pad 201, described silicon substrate has first surface 101 and second surface corresponding thereto 102, described first surface On be formed with at least one subsidence trough towards second surface, this subsidence trough is preferably straight trough or sidewall and exists with bottom surface angle The skewed slot of 80～120, does not limits.The present embodiment schematic diagram is straight trough shape.Can place at least in described subsidence trough One chips 200, for placed a chips in the present embodiment, and described chip front side is close to described first surface；Described core Having between the bottom land of the sheet back side and described subsidence trough and cohere glue 1, chip coheres by cohering the bottom land of glue and subsidence trough And solidify, it is achieved the attachment of chip, with more preferable fixed chip, prevent chip offset.
Fill with first medium layer 2 between chip surrounding and subsidence trough sidewall；Described chip front side and described first table Second dielectric layer 3 it is formed with on face；The conductive pad 201 of at least one of which and described chip front side it is formed with in described second dielectric layer The first metal connected reroutes 4, and outermost layer of metal reroutes and is coated with the first passivation layer 5, and this first metal weight cloth It is formed with the ubm layer for planting soldered ball on line, described first passivation layer offers to should ubm layer Opening, described ubm layer is implanted with the first soldered ball or the first salient point 6；At least a soldered ball or salient point in the present embodiment And the ubm layer of correspondence is positioned on the first surface of described silicon substrate.
The pad 202 of chip back, relative with the bottom land of subsidence trough, the pad of chip back can be chip itself Conductive pad, it is also possible to for the pad formed on the metallic circuit 203 that the conductive pad of chip front side is electrically caused chip back 202, it can be to be positioned at the vertical conduction through-hole structure in the middle part of chip that the conductive pad of chip front side electrically causes chip back, ginseng See Fig. 1 a, it is also possible to for being positioned at the metal communication line of chip edge, see Fig. 1 b；In other embodiments, it is also possible to inciting somebody to action The conductive pad of chip front side electrically causes formation pad 202 on the metallic circuit 203 of subsidence trough bottom land；It is specially along silicon substrate Subsidence trough inwall extend to the metal communication line of cell body, pad is by the first metal weight cloth with silicon substrate first surface Line connects, it is achieved chip front side weld pad is electrically caused back, sees Fig. 7.
It is carved with through hole 300 between pad 202 and the silicon substrate second surface of chip back；On described silicon substrate second surface It is formed with the 3rd dielectric layer 7；The second metal that at least one of which is connected it is formed with the pad 202 of chip back on 3rd dielectric layer Rerouting 8, one layer of second metal of outermost reroutes and is coated with the second passivation layer 9, and this second metal reroutes and is formed For planting the ubm layer of soldered ball, described second passivation layer offers to should the opening of ubm layer, described The second soldered ball or the second salient point 10 it is implanted with on ubm layer；Second soldered ball or the second salient point and chip back in the present embodiment Relatively, in other embodiments, can reroute on the silicon substrate second surface extending to outside chip area by the second metal, On the silicon substrate second surface that the ubm layer i.e. having the second soldered ball or the second salient point and correspondence thereof is positioned at outside chip area.
Preferably, the distance between sidewall and the described chip of described subsidence trough is more than 1 micron, to facilitate chip to put into The bottom land of subsidence trough.
Preferably, the distance between bottom land and the second surface of described silicon substrate of described subsidence trough is more than 1 micron, with It is beneficial to the silicon substrate support to chip.
Preferably, the difference in height between the first surface of described chip front side and described silicon substrate is less than 50 microns, to protect The homogeneity of card packaging body surfacing.
Preferably, the material of described first medium layer is polymer latex, and addition of vacuum is coated with, and fills out in making subsidence trough gap It is full of this polymer latex, with fixed chip, ensures insulating properties simultaneously.
Preferably, the material of described first medium layer and described second dielectric layer is same polymer latex, to improve The reliability of packaging body.
Preferably, described in cohere glue be non-conductive polymer glue or thin film, adhering chip is in the bottom land of subsidence trough, it is ensured that In ensuing technique, chip position does not offsets, in order to obtain preferable alignment precision, it is thus achieved that thinner connects up again Lines.Polymer latex can be by preparing in chip die backsize mode, and thin film can be by pressing at the chip die back side Prepared by film mode.
Preferably, the material that described first, second metal reroutes is copper or aluminum.
Preferably, described first, second soldered ball is stannum ball.
Preferably, described ubm layer is the one in Ni/Au, CrW/Cu, Ti/W/Cu/Ni/Au, Ti/Cu, figure Show and be not drawn into.
As a kind of preferred embodiment, the manufacture method of this embedment silicon substrate fan-out package structure is real as follows Execute:
A., the packaging body of one chip buried silicon substrate disk first surface, chip front side and silicon substrate flush are provided, And chip front side has conductive pad, chip front side conductive pad is rerouted by the first metal on chip and draws；Chip back is positioned at silicon Matrix subsidence trough bottom land, chip back has pad, and chip back bonds with subsidence trough bottom land by cohering glue.
Specifically, silicon substrate disk has first surface and second surface corresponding thereto, at described silicon substrate disk First surface etching forms at least one and has setting shape and the subsidence trough of the degree of depth；Place at least in described subsidence trough One chip to be packaged, described chip front side is close to the first surface of described silicon substrate, and described chip is recessed with described sinking Between the sidewall of groove, there is gap；By coating process, in the gap between the sidewall and described chip of described subsidence trough Fill colloid, form first medium layer；In described chip front side and on the first surface of described silicon substrate, form one layer absolutely The second dielectric layer of edge；Open the second dielectric layer above the conductive pad of described chip, and the company of making on second dielectric layer The first metal connecing whole conductive pad of chip reroutes；One layer of first passivation layer of making above is rerouted, the at the first metal One metal needs the position planting soldered ball to open the first passivation layer on rerouting, and reroutes preparation at the first metal exposed required Ubm layer, then carry out salient point preparation or plant soldered ball, forming encapsulating structure as shown in Figure 2；
It is also preferred that the left coating process uses polymer latex, second dielectric layer and first medium layer are same polymer latex, with Improve the reliability of packaging body.
Preferably, the second surface of silicon substrate disk, before and after salient point preparation or planting soldered ball, is subtracted by silicon substrate first surface Thin to desired thickness.
Preferably, described chip back scribbles and coheres glue, and described chip is by cohering the bottom of glue and described subsidence trough Cohere.Concrete operations are, at the chip disk back side, brush coheres glue, form single chips after scribing, will be with by pick tool Cohere the chip of glue to be positioned on described silicon substrate in subsidence trough.
Preferably, in the space between the sidewall and described chip of described subsidence trough, colloid is filled under vacuum conditions Implement, it is possible to reduce bubble, it is ensured that gapfill.
Preferably, described second dielectric layer be can photoetching material, the first passivation layer is can photoetching material.So as use photoetching Processing procedure forms opening, exposes the conductive pad of chip front side, makes the first metal reroute and connects conductive pad.
B. on said structure salient point or soldered ball face, form one layer of temporary protective material, and right to the pad 202 of chip back Answer position to carry out opening hole, form encapsulating structure as shown in Figure 3, then formed absolutely on silicon substrate second surface and in through hole 3rd dielectric layer of edge, and expose the pad in through hole, and on the 3rd dielectric layer, make the pad connecting chip back Second metal reroute, see Fig. 4；
C. on the second metal reroutes, make one layer of second passivation layer, need to plant soldered ball on the second metal reroutes Position open the second passivation layer, expose second metal reroute on prepare required ubm layer, then carry out Soldered ball is prepared or planted to salient point, forms an embedment silicon substrate fan-out package structure, sees Fig. 5.
D. see Fig. 6, silicon substrate disk is carried out scribing, and by silicon substrate first surface salient point or the interim guarantor in soldered ball face Sheath is removed, and forms the two-sided fan-out packaging body having ball structure.
Above example is referring to the drawings, to a preferred embodiment of the present invention will be described in detail.Those skilled in the art Member by above-described embodiment being carried out the amendment on various forms or change, but without departing substantially from the essence of the present invention in the case of, all Fall within the scope and spirit of the invention.

Claims (10)

1. the fan-out packaging structure of a two-sided attachment, it is characterised in that include silicon substrate (100) and chip (200), described silicon Matrix has first surface (101) and second surface (102) corresponding thereto, and described first surface is formed at least one court To the subsidence trough of second surface, at least one described chip back mounts the bottom land of described subsidence trough, described core down Sheet front includes conductive pad (201)；Described chip week side and described subsidence trough sidewall between fill out with first medium layer (2) Fill；Second dielectric layer (3) it is formed with in described chip front side and described first surface；It is formed at least in described second dielectric layer One layer of first metal being connected with the conductive pad (201) of described chip reroutes (4), and one layer of first metal of outermost reroutes overlying It is stamped the first passivation layer (5)；Described chip back or described subsidence trough bottom land are provided with pad (202) described pad and described the Through hole (300) it is carved with between two surfaces；The 3rd dielectric layer (7) it is formed with on described second surface；On described 3rd dielectric layer and The second metal rewiring (8) that at least one of which electrically connects, outermost one layer second it is formed with described pad (202) in described through hole Metal is coated with the second passivation layer (9) on rerouting；Wherein said first metal reroutes or in described second metal rewiring At least a circuit extends on the silicon substrate surface outside described chip area.
The fan-out packaging structure of two-sided attachment the most according to claim 1, it is characterised in that described pad is: chip is carried on the back Face itself includes pad, or on the metallic circuit that the conductive pad of described chip front side is electrically caused described chip back The pad formed, or formed on the metallic circuit that the conductive pad of described chip front side is electrically caused described subsidence trough bottom land Pad.
The fan-out packaging structure of two-sided attachment the most according to claim 1, it is characterised in that: the sidewall of described subsidence trough And the distance between described chip is more than 1 micron.
The fan-out packaging structure of two-sided attachment the most according to claim 1, it is characterised in that: described chip front side and described Difference in height between the first surface of silicon substrate is less than 50 microns.
The fan-out packaging structure of two-sided attachment the most according to claim 1, it is characterised in that described first medium layer and institute The material stating second dielectric layer is polymer latex.
The fan-out packaging structure of two-sided attachment the most according to claim 1, it is characterised in that described first metal reroutes And/or described second metal reroutes upper connection and has soldered ball/salient point.
The fan-out packaging structure of two-sided attachment the most according to claim 1, it is characterised in that described chip back is by glutinous Gum deposit (1) attachment to the bottom land of described subsidence trough, described in cohere the thickness of glue less than 50 microns, more than 1 micron.
The fan-out packaging structure of two-sided attachment the most according to claim 7, it is characterised in that described in cohere glue be polymer Glue.
The fan-out packaging structure of two-sided attachment the most according to claim 1, it is characterised in that imbed same subsidence trough Number of chips is more than or equal to 2.
10. the method for packing of the fan-out packaging structure of a two-sided attachment, it is characterised in that comprise the following steps:
A. provide and one there is first surface and second surface silicon substrate disk corresponding thereto, described first surface is formed to A few subsidence trough towards second surface, at least one chip back mounts the bottom land of described subsidence trough, institute down Stating chip front side and include conductive pad, described chip back includes pad；Described chip front side and described silicon substrate the first table Face is concordant or close to concordant, the conductive pad of described chip front side is rerouted by the first metal formed in chip front side and draws, extremely Few first metal reroutes and extends on silicon substrate first surface；Described chip back by cohere gluing be attached to described under On the bottom land of heavy groove；
B. on described silicon substrate disk second surface, the position of corresponding chip back pad carries out through hole；
C. on described silicon substrate disk second surface and described through-hole wall make connect described chip back pad second Metal reroutes；
D. silicon substrate disk is carried out scribing, forms the fan-out packaging structure of single slice two-sided attachment.
CN201610768360.5A 2016-08-30 2016-08-30 The fan-out packaging structure of two-sided attachment and method for packing Pending CN106129023A (en)

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CN107452689A (en) * 2017-09-14 2017-12-08 厦门大学 The embedded fan-out-type silicon pinboard and preparation method of three-dimensional systematic package application
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Application publication date: 20161116