CN104600039A - Double-side interconnecting fan-out process - Google Patents

Double-side interconnecting fan-out process Download PDF

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Publication number
CN104600039A
CN104600039A CN201410831056.1A CN201410831056A CN104600039A CN 104600039 A CN104600039 A CN 104600039A CN 201410831056 A CN201410831056 A CN 201410831056A CN 104600039 A CN104600039 A CN 104600039A
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described
conductive pole
layer
end face
metal layer
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CN201410831056.1A
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Chinese (zh)
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CN104600039B (en
Inventor
丁万春
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南通富士通微电子股份有限公司
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Priority to CN201410831056.1A priority Critical patent/CN104600039B/en
Publication of CN104600039A publication Critical patent/CN104600039A/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

Abstract

The invention relates to a double-side interconnecting fan-out process. The method comprises the steps of forming a plurality of blind holes in the top surface of a wafer; forming a first conductive column and a reproduced chip in the blind holes; forming a plastic sealing layer on the top surface of the wafer, wherein the plastic sealing layer exposes from the top surfaces of the first conductive column and a second conductive column; forming a first re-wiring metal layer on the plastic sealing layer; forming a first passivating layer on the first re-wiring metal layer, wherein a first opening is formed in the first passivating layer; forming an upper convex point at the first opening; thinning the wafer until exposing the bottom surface of the first conductive column; forming a second passivating layer on the bottom surface of the wafer, wherein a second opening for exposing the bottom surface of the first conductive column and the top surface of the chip is formed in the second passivating layer; forming a rear electric terminal structure at the second opening. The chips prepared by the process can be stacked and packaged; meanwhile, the rear electric terminal structure forms a metal layer at the second opening to radiate and reduce the heat resistance of the chips, in particular the high-power-consumption chips, and moreover, the chips can work normally.

Description

Two-sided interconnected fan-out technique

Technical field

The present invention relates to technical field of semiconductor encapsulation, particularly relate to a kind of two-sided interconnected fan-out technique.

Background technology

At present, in the fan-out technique of semiconductor machining, usually adopt the technique of one side lamination to process, by this kind of processing technology, one single chip can be realized to amplify, or realize multiple chip and connect side by side.But, the stacked package of chip can not be realized.

Summary of the invention

Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.

The object of the present invention is to provide a kind of two-sided interconnected fan-out technique.The invention provides a kind of two-sided interconnected fan-out technique, comprise the following steps:

The end face of wafer offers multiple blind hole;

In described blind hole, form the first conductive pole, and lay at least one chip in an inverted manner, the weld pad of described chip is formed with the second conductive pole, the top of described first conductive pole and the top of described second conductive pole are all higher than the end face of described wafer;

The end face of described wafer is formed plastic packaging layer, and described plastic packaging layer exposes the end face of described first conductive pole and described second conductive pole;

Described plastic packaging layer is formed the first interconnection metal layer be again connected with described first conductive pole and described second conductive pole;

Described first again interconnection metal layer form the first passivation layer, and described first passivation layer is formed with the first opening exposing the described first interconnection metal layer again;

Formed and the described first upper salient point of being connected of interconnection metal layer again at described first opening part;

Carry out thinning to the bottom of described wafer, until expose the bottom surface of described first conductive pole;

The bottom surface of the described wafer after thinning forms the second passivation layer, and described second passivation layer is provided with the second opening exposing described first conductive pole bottom surface and described chip end face;

Back power connection mechanism is formed at described second opening part.

The chip adopting present invention process to be formed, all defines the structure connecing electricity at top and bottom, make the chip using present invention process to be formed can carry out the stacked package of chip.In addition, when forming back power connection mechanism, the second opening part formation metal level at chip top can be exposed at the second passivation layer simultaneously, this metal level can be used for dispelling the heat to chip, reduce thermal resistance, particularly for the chip of high power consumption, it can better ensure the normal work of chip.

Accompanying drawing explanation

Below with reference to the accompanying drawings illustrate embodiments of the invention, above and other objects, features and advantages of the present invention can be understood more easily.Parts in accompanying drawing are just in order to illustrate principle of the present invention.In the accompanying drawings, same or similar technical characteristic or parts will adopt same or similar Reference numeral to represent.

The flow chart of the two-sided interconnected fan-out technique that Fig. 1 provides for the embodiment of the present invention.

The structural representation that each step of two-sided interconnected fan-out technique that Fig. 2 a-Fig. 2 o provides for the enforcement embodiment of the present invention is formed.

Embodiment

With reference to the accompanying drawings embodiments of the invention are described.The element described in an accompanying drawing of the present invention or a kind of execution mode and feature can combine with the element shown in one or more other accompanying drawing or execution mode and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.

The flow chart of the two-sided interconnected fan-out technique that Fig. 1 provides for the embodiment of the present invention.As shown in Figure 1, the two-sided interconnected fan-out technique that the embodiment of the present invention provides, comprises the following steps:

S101: offer multiple blind hole on the end face of wafer;

S102: form the first conductive pole in described blind hole, and lay at least one chip in an inverted manner, the weld pad of described chip is formed with the second conductive pole, the top of described first conductive pole and the top of described second conductive pole are all higher than the end face of described wafer;

S103: form plastic packaging layer on the end face of described wafer, described plastic packaging layer exposes the end face of described first conductive pole and described second conductive pole;

S104: form the first interconnection metal layer be again connected with described first conductive pole and described second conductive pole on described plastic packaging layer;

S105: form the first passivation layer on described first again interconnection metal layer, described first passivation layer is formed with the first opening exposing the described first interconnection metal layer again;

S106: formed and the described first upper salient point of being connected of interconnection metal layer again at described first opening part;

S107: carry out thinning to the bottom of described wafer, until expose the bottom surface of described first conductive pole;

S108: the bottom surface of the described wafer after thinning forms the second passivation layer, described second passivation layer is provided with the second opening exposing described first conductive pole bottom surface and described chip end face;

S109: form back power connection mechanism at described second opening part.

The chip adopting present invention process to be formed, all defines the structure connecing electricity at top and bottom, make the chip using present invention process to be formed can carry out the stacked package of chip.In addition, when forming back power connection mechanism, the second opening part formation metal level at chip top can be exposed at the second passivation layer simultaneously, this metal level can be used for dispelling the heat to chip, reduce thermal resistance, particularly for the chip of high power consumption, it can better ensure the normal work of chip.

Implement the two-sided interconnected fan-out technique that the embodiment of the present invention provides, particularly, as shown in Figure 2 a, provide a wafer 1, at the radium-shine etching mark of the end face of wafer 1.As shown in Figure 2 b, the position end face of wafer 1 corresponding to etching mark forms multiple blind hole 2.Multiple blind hole 2 can be processed by the mode of etching.As shown in Figure 2 c, in blind hole 2, form the first conductive pole 3, first conductive pole 3 setting position and magnitude setting are determined according to actual needs.The top of the first conductive pole 3 is higher than the end face of wafer 1.Can implementation as one, the first conductive pole 3 can adopt copper post.As shown in Figure 2 d, in blind hole, place at least one chip with inverted form, chip is between the first conductive pole.Can arrange one or more chip 4 in each blind hole 2, the magnitude setting of chip 4 is determined according to actual needs.It should be noted that, then before being positioned in blind hole by chip, first reproduce chip, also namely on the weld pad of chip, form the second conductive pole, the second conductive pole can be copper post.As shown in Figure 2 e, form plastic packaging layer 5 at the top of wafer 1, the second conductive pole 6 top on coated first conductive pole 3 of plastic packaging layer 5 and chip 4.As shown in figure 2f, the top of described plastic packaging layer 5 of polishing, until the end face of described first conductive pole 3 and described second conductive pole 6 exposes the end face of described plastic packaging layer, and the end face of described first conductive pole 3 and described second conductive pole and the either flush of described plastic packaging layer.As shown in Figure 2 g, plastic packaging layer 5 is formed the first interconnection metal layer 7 be again connected with described first conductive pole 3 and described second conductive pole 6.As shown in fig. 2h, first again interconnection metal layer 7 are formed the first opening 9 that the first passivation layer 8, first passivation layer 8 is formed with exposure first interconnection metal layer 7 again.As shown in fig. 2i, formed and the first upper salient point 10 of being connected of interconnection metal layer 7 again at the first opening part 9.As shown in figure 2j, the first passivation layer 8 is formed coated on the adhesive layer 11 of salient point 10, by adhesive layer 11, the crystal circle structure after forming upper salient point is bonded on carrier 12.As shown in Fig. 2 k, carry out thinning to the bottom of wafer 1, until expose the bottom surface of the first conductive pole 3 and the bottom surface of chip 4.Thinning operation can be carried out to wafer 1 by the mode of polishing.As illustrated in figure 21, the bottom surface of the wafer after thinning forms the second opening 14 that the second passivation layer 13, second passivation layer 13 is provided with exposure first conductive pole 3 bottom surface and chip 4 end face.At the second opening 14 place formation back power connection mechanism.Back power connection mechanism as required, can be designed to various structures form, and such as, as shown in Fig. 2 m, power connection mechanism can be formation second interconnection metal layer 15 again on the second passivation layer 13, and forms pad 16 on second again interconnection metal layer.Certainly, power connection mechanism can also be formed in the lower salient point on the second passivation layer, or is formed in the interconnection metal layer again of second on the second passivation layer, and the lower salient point formed on second again interconnection metal layer.As shown in Fig. 2 n, be cut to adhesive layer from the second passivation layer, between adjacent encapsulation, form cutting groove 17.As shown in figure 2o, remove adhesive layer, form multiple two-sided interconnected packaged chip 18.

In equipment of the present invention and method, obviously, each parts or each step reconfigure after can decomposing, combine and/or decomposing.These decompose and/or reconfigure and should be considered as equivalents of the present invention.Also it is pointed out that the step performing above-mentioned series of processes can order naturally following the instructions perform in chronological order, but do not need necessarily to perform according to time sequencing.Some step can walk abreast or perform independently of one another.Simultaneously, above in the description of the specific embodiment of the invention, the feature described for a kind of execution mode and/or illustrate can use in one or more other execution mode in same or similar mode, combined with the feature in other execution mode, or substitute the feature in other execution mode.

Claims (6)

1. a two-sided interconnected fan-out technique, is characterized in that, comprise the following steps:
The end face of wafer offers multiple blind hole;
In described blind hole, form the first conductive pole, and lay at least one chip in an inverted manner, the weld pad of described chip is formed with the second conductive pole, the top of described first conductive pole and the top of described second conductive pole are all higher than the end face of described wafer;
The end face of described wafer is formed plastic packaging layer, and described plastic packaging layer exposes the end face of described first conductive pole and described second conductive pole;
Described plastic packaging layer is formed the first interconnection metal layer be again connected with described first conductive pole and described second conductive pole;
Described first again interconnection metal layer form the first passivation layer, and described first passivation layer is formed with the first opening exposing the described first interconnection metal layer again;
Formed and the described first upper salient point of being connected of interconnection metal layer again at described first opening part;
Carry out thinning to the bottom of described wafer, until expose the bottom surface of described first conductive pole;
The bottom surface of the described wafer after thinning forms the second passivation layer, and described second passivation layer is provided with the second opening exposing described first conductive pole bottom surface and described chip end face;
Back power connection mechanism is formed at described second opening part.
2. two-sided interconnected fan-out technique as claimed in claim 1, is characterized in that, described at described second opening part formation back power connection mechanism, is specially:
Salient point under described second passivation layer is formed; Or,
Described second passivation layer forms the second interconnection metal layer again, described second again interconnection metal layer is connected with the bottom surface of described first conductive pole and the end face of described chip respectively, salient point under formation on described second again interconnection metal layer; Or,
Described second passivation layer forms the second interconnection metal layer again, described second again interconnection metal layer be connected with the bottom surface of described first conductive pole and the end face of described chip respectively, described second again interconnection metal layer form pad.
3. two-sided interconnected fan-out technique as claimed in claim 1, is characterized in that, describedly on the end face of described wafer, forms plastic packaging layer, and described plastic packaging layer exposes the end face of described first conductive pole and described second conductive pole, is specially:
The end face of described wafer is formed plastic packaging layer, the top of coated described first conductive pole of described plastic packaging layer and described second conductive pole, the top of thinning described plastic packaging layer, until the end face of described first conductive pole and described second conductive pole exposes the end face of described plastic packaging layer, and the either flush of the end face of described first conductive pole and described second conductive pole and described plastic packaging layer.
4. two-sided interconnected fan-out technique as claimed in claim 1, is characterized in that, described described first opening part formed with after the described first upper salient point that interconnection metal layer is connected again, also comprise:
Described first passivation layer is formed coated described on the adhesive layer of salient point, by described adhesive layer, the crystal circle structure after forming upper salient point is bonded on carrier.
5. two-sided interconnected fan-out technique as claimed in claim 4, is characterized in that, be cut to described adhesive layer, remove described adhesive layer from described second passivation layer, forms multiple two-sided interconnected chip.
6. the two-sided interconnected fan-out technique as described in any one of claim 1-4, is characterized in that, described first conductive pole and described second conductive pole are copper post.
CN201410831056.1A 2014-12-26 2014-12-26 Two-sided interconnection is fanned out to technique CN104600039B (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097565A (en) * 2015-06-30 2015-11-25 南通富士通微电子股份有限公司 Formation method of package structure
CN105097728A (en) * 2015-06-30 2015-11-25 南通富士通微电子股份有限公司 Packaging structure
CN106024657A (en) * 2016-06-24 2016-10-12 南通富士通微电子股份有限公司 Embedded package structure
CN106129023A (en) * 2016-08-30 2016-11-16 华天科技(昆山)电子有限公司 The fan-out packaging structure of two-sided attachment and method for packing
CN106449555A (en) * 2016-12-09 2017-02-22 华进半导体封装先导技术研发中心有限公司 Chip packaging process and chip packaging structure

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CN103021984A (en) * 2013-01-04 2013-04-03 日月光半导体制造股份有限公司 Wafer level packaging structure and manufacturing method thereof
CN202871783U (en) * 2012-08-31 2013-04-10 江阴长电先进封装有限公司 Chip-embedded type stacking-wafer level packaging structure
CN103681468A (en) * 2012-09-14 2014-03-26 新科金朋有限公司 Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP
CN103748700A (en) * 2011-06-01 2014-04-23 香港科技大学 Submount with cavities and through vias for LED packaging

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103748700A (en) * 2011-06-01 2014-04-23 香港科技大学 Submount with cavities and through vias for LED packaging
CN202871783U (en) * 2012-08-31 2013-04-10 江阴长电先进封装有限公司 Chip-embedded type stacking-wafer level packaging structure
CN103681468A (en) * 2012-09-14 2014-03-26 新科金朋有限公司 Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP
CN103021984A (en) * 2013-01-04 2013-04-03 日月光半导体制造股份有限公司 Wafer level packaging structure and manufacturing method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097565A (en) * 2015-06-30 2015-11-25 南通富士通微电子股份有限公司 Formation method of package structure
CN105097728A (en) * 2015-06-30 2015-11-25 南通富士通微电子股份有限公司 Packaging structure
CN105097565B (en) * 2015-06-30 2018-01-30 通富微电子股份有限公司 The forming method of encapsulating structure
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CN106024657A (en) * 2016-06-24 2016-10-12 南通富士通微电子股份有限公司 Embedded package structure
CN106129023A (en) * 2016-08-30 2016-11-16 华天科技(昆山)电子有限公司 The fan-out packaging structure of two-sided attachment and method for packing
CN106449555A (en) * 2016-12-09 2017-02-22 华进半导体封装先导技术研发中心有限公司 Chip packaging process and chip packaging structure

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