CN110600383A - 2.5D silicon-based adapter plate packaging method and structure - Google Patents

2.5D silicon-based adapter plate packaging method and structure Download PDF

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CN110600383A
CN110600383A CN201910924797.7A CN201910924797A CN110600383A CN 110600383 A CN110600383 A CN 110600383A CN 201910924797 A CN201910924797 A CN 201910924797A CN 110600383 A CN110600383 A CN 110600383A
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layer
silicon
silicon substrate
tsg
rewiring
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CN110600383B (en
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王成迁
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CETC 58 Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a 2.5D silicon-based adapter plate packaging method and structure, and belongs to the technical field of integrated circuit packaging. Firstly, providing a silicon substrate and a glass carrier plate, wherein the front surface of the silicon substrate is bonded with the glass carrier plate through a cut-off layer; etching a TSG groove on the back surface of the silicon substrate, forming a passivation layer and a first layer of rewiring, and forming a metal welding pad array at the bottom of the TSG groove; filling the TSG groove with a high polymer material, opening the first layer of rewiring, and realizing interconnection through n layers of rewirings; interconnecting heterogeneous chips with n layers of rewirings through micro-bumps, and plastically packaging the heterogeneous chips by using a plastic packaging material; removing the glass carrier plate to expose the cut-off layer, and opening at the metal welding pad; and sequentially forming n layers of rewiring, a solder mask layer and salient points, and finally cutting into single packaged chips to finish final packaging.

Description

2.5D silicon-based adapter plate packaging method and structure
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a 2.5D silicon-based adapter plate wafer-level packaging method and structure.
Background
At present, the traditional single-function chip package can not meet the development requirements of integration, miniaturization and intellectualization of electronic products. There is an increasing interest in implementing multi-functional chip system-in-package (soc) packages by fan-out (e.g., integrated fan-out package InFO and silicon-on-chip fan-out package eSiFO) and interposer (e.g., chip-on-wafer (cofos) and embedded multi-chip interconnect bridge (EMIB)). The application of these advanced packaging technologies breaks through the physical limit barriers of wafer fabrication, and continues moore's law. Therefore, the realization of heterogeneous chip system-level integration by reconstructing wafer fan-out packages and three-dimensional stacked packages becomes the research and development focus of advanced packages and high-performance wafer-level packages at the present stage. Among them, TSV (Through Silicon Vias) interconnection is the basis of three-dimensional stacked package technology, and vertical interconnection Through TSV is also a trend of high-density integrated package. However, the TSV technology is difficult, and expensive etching, electroplating, deposition and chemical mechanical polishing equipment are required, which is difficult to be accepted by common packaging factories.
Disclosure of Invention
The invention aims to provide a 2.5D silicon-based adapter plate packaging method and a 2.5D silicon-based adapter plate packaging structure, which are used for completing interconnection of front and back sides of a silicon substrate by manufacturing a TSG groove and forming a metal welding pad at the bottom of the TSG groove without manufacturing a TSV (through silicon via) so as to solve the problems of high difficulty and high cost of the manufacturing process of the TSV in the conventional three-dimensional integrated packaging.
In order to solve the above technical problem, the present invention provides a 2.5D silicon-based interposer packaging method, including:
providing a silicon substrate and a glass carrier plate, wherein the front surface of the silicon substrate is bonded with the glass carrier plate through a cut-off layer;
etching a TSG groove on the back surface of the silicon substrate and forming a passivation layer and a first layer of rewiring;
forming a metal welding pad array at the bottom of the TSG groove;
filling the TSG groove with a high polymer material, opening the first layer of rewiring, and realizing interconnection through n layers of rewirings;
interconnecting heterogeneous chips with n layers of rewirings through micro-bumps, and plastically packaging the heterogeneous chips by using a plastic packaging material;
removing the glass carrier plate to expose the cut-off layer, and opening at the metal welding pad;
and sequentially forming n layers of rewiring, a solder mask layer and salient points, and finally cutting into single packaged chips to finish final packaging.
Optionally, the glass carrier plate comprises bonding glass and a temporary bonding laser reaction layer formed on the bonding glass;
the temporary bonding laser reaction layer is bonded with the cut-off layer through temporary bonding glue;
the thickness of the bonding glass is not less than 100 μm; the thickness of the temporary bonding glue is not less than 1 μm, and the thickness of the temporary bonding laser reaction layer is not less than 0.1 μm.
Optionally, etching a TSG groove on the silicon substrate back surface and forming a passivation layer and a first layer of rewiring includes:
thinning the back surface of the silicon substrate to a target thickness by a grinding or etching process;
etching a TSG groove on the back surface of the silicon substrate by using dry etching;
after the TSG groove is etched, depositing a passivation layer on the back surface of the silicon substrate;
and manufacturing a first layer of rewiring on the back surface of the silicon substrate by photoetching, physical vapor deposition, electroplating and chemical plating processes.
Optionally, the depth of the TSG groove is more than 1 μm, the groove angle θ is an obtuse angle, i.e., 90 ° < θ <180 °, and the number is not less than 1.
Optionally, the material of the cut-off layer is one or more of inorganic materials, the thickness of the cut-off layer is not less than 0.1 μm,
the inorganic material includes SiO2, SiC, and SiN.
Optionally, the length and width of the metal pad are both more than 1 μm, the thickness is more than 0.1 μm, and the material is one or more of metal materials; wherein,
the metal material includes Cu, Ni, Sn, Ag and Au.
Optionally, the passivation layer is one or more of inorganic materials or passivation glue of high polymer materials; the thickness of the film is not less than 0.1 μm,
the inorganic material includes SiO2, SiC, and SiN.
Optionally, the molding compound is a resin material.
The invention also provides a 2.5D silicon-based adapter plate packaging structure, which comprises:
the front surface of the silicon substrate is deposited with a cut-off layer, and the back surface of the silicon substrate is etched with a TSG groove and filled with a high polymer material; a passivation layer and a first layer of rewiring are formed between the silicon substrate and the high polymer material;
n layers of rewiring lines connected to the first layer of rewiring lines;
the heterogeneous chips are welded on the n layers of redistribution lines through the micro-bumps;
the cut-off layer is provided with an opening, and n layers of rewiring, a solder mask layer and salient points are formed.
Optionally, the heterogeneous chip is plastically packaged by a plastic packaging material.
The invention provides a 2.5D silicon-based adapter plate packaging method and a structure, firstly providing a silicon substrate and a glass carrier plate, wherein the front surface of the silicon substrate is bonded with the glass carrier plate through a cut-off layer; etching a TSG groove on the back surface of the silicon substrate and forming a passivation layer and a first layer of rewiring; then forming a metal welding pad array at the bottom of the TSG groove; filling the TSG groove with a high polymer material, opening the first layer of rewiring, and realizing interconnection through n layers of rewirings; interconnecting heterogeneous chips with n layers of rewirings through micro-bumps, and plastically packaging the heterogeneous chips by using a plastic packaging material; removing the glass carrier plate to expose the cut-off layer, and opening at the metal welding pad; and sequentially forming n layers of rewiring, a solder mask layer and salient points, and finally cutting into single packaged chips to finish final packaging.
The invention provides the silicon-based front-back interconnection method with simple and convenient process and low cost, the 2.5D silicon-based adapter plate is manufactured without TSV, the three-dimensional integrated packaging of chips with different functions and different processes is realized, the production efficiency is improved, and the silicon-based front-back interconnection method is suitable for large-scale mass production.
Drawings
Fig. 1 is a schematic flow chart of a 2.5D silicon-based interposer packaging method according to the present invention;
FIG. 2 is a schematic diagram of a silicon-based front side deposition stop layer;
FIG. 3 is a schematic view of a glass carrier structure;
FIG. 4 is a schematic diagram of a bonded glass carrier and silicon substrate;
FIG. 5 is a schematic diagram of the silicon substrate after etching the TSG groove and depositing a passivation layer;
FIG. 6 is a schematic diagram of a first layer of rewiring on a silicon-based backside;
FIG. 7 is a schematic top view of a metal pad array formed at the bottom of a TSG groove;
FIG. 8 is a schematic view of the TSG groove filled with polymer material and then subjected to n-layer redistribution;
FIG. 9 is a schematic diagram of a silicon-based backside flip-chip bonded heterogeneous chip;
FIG. 10 is a schematic diagram of a heterogeneous chip after molding;
FIG. 11 is a schematic view after an opening is etched in the stop layer;
fig. 12 is a schematic diagram of a solder resist layer and bumps fabricated and diced into individual packages.
Detailed Description
The following describes a 2.5D silicon-based interposer packaging method and structure according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a 2.5D silicon-based adapter plate packaging method, the flow of which is shown in figure 1, and the method comprises the following steps:
step S11, providing a silicon substrate and a glass carrier plate, wherein the front surface of the silicon substrate is bonded with the glass carrier plate through a cut-off layer;
step S12, etching a TSG groove on the back surface of the silicon substrate and forming a passivation layer and a first layer of rewiring;
step S13, forming a metal pad array at the bottom of the TSG groove;
step S14, filling the TSG groove with high polymer material, opening at the first layer rewiring position, and realizing interconnection through n layers of rewiring;
s15, interconnecting heterogeneous chips with n layers of rewiring through micro-bumps, and plastically packaging the heterogeneous chips by using a plastic package material;
step S16, removing the glass carrier plate to expose the cut-off layer, and opening at the metal welding pad;
and step S17, sequentially forming n layers of rewiring, solder mask and salient points, and finally cutting into single packaged chips to finish final packaging.
Specifically, a silicon substrate 101 and a glass carrier are provided first. As shown in fig. 2, a cut-off layer 102 is deposited on the front surface of the silicon substrate 101, the cut-off layer 102 is made of one or more inorganic materials, the thickness of the cut-off layer is not less than 0.1 μm, and the inorganic materials include SiO2, SiC and SiN; as shown in fig. 3, the glass carrier plate comprises a bonding glass 201 and a temporary bonding laser reaction layer 202 formed on the bonding glass 201, wherein the thickness of the bonding glass 201 is not less than 100 μm; the thickness of the temporary bonding laser reaction layer 202 is not less than 0.1 μm. The temporary bonding laser reaction layer 202 is bonded with the cut-off layer 102 through a temporary bonding glue 203, as shown in fig. 4; the thickness of the temporary bonding paste 203 is not less than 1 μm.
Referring to fig. 5, the back surface of the silicon substrate 101 is thinned to a target thickness by a grinding or etching process; and etching a TSG groove 114 on the back surface of the silicon substrate 101 by using dry etching, wherein the size of the TSG groove 114 is determined according to the electrical interconnection density of the front surface and the back surface of the silicon substrate 101, the depth is more than 1 mu m, the groove angle theta is an obtuse angle, namely 90 degrees < theta <180 degrees, and the number is not less than 1. After the TSG groove 114 is etched, depositing a passivation layer 103 on the back surface of the silicon substrate 101, wherein the passivation layer 103 is one or more of inorganic materials or passivation glue of high polymer materials; the thickness of the material is not less than 0.1 μm, and the inorganic material comprises SiO2, SiC and SiN; then, a first layer of rewiring 104 is manufactured on the back surface of the silicon substrate 101 through photolithography, physical vapor deposition, electroplating and electroless plating processes, as shown in fig. 6.
Forming a metal pad 110 at the bottom of the TSG groove 114, and forming an array by a plurality of metal pads 110, as shown in fig. 7; preferably, the length and the width of the metal pad 110 are both more than 1 μm, the thickness is more than 0.1 μm, and the material is one or more of metal materials; wherein the metal material comprises Cu, Ni, Sn, Ag and Au;
as shown in fig. 8, the TSG groove 114 is filled with the polymer material 105, and is opened at the first layer re-wiring 104, and interconnection with the first layer re-wiring 104 is achieved by the n-layer re-wiring 106;
as shown in fig. 9, heterogeneous chips (including heterogeneous chip 301 and heterogeneous chip 302) are interconnected with n-layer rewiring 106 through micro bumps 303 by a flip-chip bonding process; then, as shown in fig. 10, the heterogeneous chip is plastically packaged by a plastic package material 107; the plastic packaging material 107 is a resin material;
removing the glass carrier, cleaning the temporary bonding glue 203 to expose the stop layer 102, and forming an opening 108 at the metal pad 110 by dry etching, wherein the size of the opening 108 is smaller than that of the metal pad 110, as shown in fig. 11;
finally, an n-layer rewiring 112 is formed by using a rewiring process, the solder mask layer 111 and the bumps 113 are manufactured, and finally, the semiconductor chip is cut into single packaged chips to complete final packaging, as shown in fig. 12.
The 2.5D silicon-based interposer package structure prepared by the 2.5D silicon-based interposer package method is shown in fig. 12, and includes a silicon substrate 101, n layers of rewiring 106, and a plurality of heterogeneous chips; the front surface of the silicon substrate 101 is deposited with a cut-off layer 102, and the back surface is etched with a TSG groove and filled with a high polymer material 105; a passivation layer 103 and a first rewiring 104 are formed between the silicon substrate 101 and the high polymer material 105; the n-layer rewiring 106 is connected to the first-layer rewiring 104; a plurality of heterogeneous chips (including heterogeneous chip 301 and heterogeneous chip 302) are soldered on the n-layer rewiring 106 through micro bumps 303.
Specifically, the cut-off layer 102 is provided with an opening, and n layers of rewiring 112, a solder resist layer 111 and a bump 113 are formed; the heterogeneous chip is plastically packaged by a plastic packaging material 107, and the plastic packaging material 107 is a resin material.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A2.5D silicon-based interposer packaging method is characterized by comprising the following steps:
providing a silicon substrate and a glass carrier plate, wherein the front surface of the silicon substrate is bonded with the glass carrier plate through a cut-off layer;
etching a TSG groove on the back surface of the silicon substrate and forming a passivation layer and a first layer of rewiring;
forming a metal welding pad array at the bottom of the TSG groove;
filling the TSG groove with a high polymer material, opening the first layer of rewiring, and realizing interconnection through n layers of rewirings;
interconnecting heterogeneous chips with n layers of rewirings through micro-bumps, and plastically packaging the heterogeneous chips by using a plastic packaging material;
removing the glass carrier plate to expose the cut-off layer, and opening at the metal welding pad;
and sequentially forming n layers of rewiring, a solder mask layer and salient points, and finally cutting into single packaged chips to finish final packaging.
2. The 2.5D silicon-based interposer package method of claim 1, wherein the glass carrier comprises a bonding glass and a temporary bonding laser reaction layer formed on the bonding glass;
the temporary bonding laser reaction layer is bonded with the cut-off layer through temporary bonding glue;
the thickness of the bonding glass is not less than 100 μm; the thickness of the temporary bonding glue is not less than 1 μm, and the thickness of the temporary bonding laser reaction layer is not less than 0.1 μm.
3. The method of packaging a 2.5D silicon-based interposer as recited in claim 1, wherein etching a TSG recess in the silicon-based backside and forming a passivation layer and a first layer of rewiring comprises:
thinning the back surface of the silicon substrate to a target thickness by a grinding or etching process;
etching a TSG groove on the back surface of the silicon substrate by using dry etching;
after the TSG groove is etched, depositing a passivation layer on the back surface of the silicon substrate;
and manufacturing a first layer of rewiring on the back surface of the silicon substrate by photoetching, physical vapor deposition, electroplating and chemical plating processes.
4. The method of packaging a 2.5D silicon-based interposer as recited in any of claims 1-3, wherein the TSG grooves have a depth of 1 μm or more, and the groove angle θ is obtuse, i.e., 90 ° < θ <180 °, and the number is not less than 1.
5. The method for encapsulating a 2.5D silicon-based interposer as claimed in claim 1, wherein the stop layer is made of one or more inorganic materials with a thickness not less than 0.1 μm,
the inorganic material includes SiO2, SiC, and SiN.
6. The packaging method of the 2.5D silicon-based interposer as claimed in claim 1, wherein the metal pads have a length and a width of 1 μm or more and a thickness of 0.1 μm or more, and are made of one or more metal materials; wherein,
the metal material includes Cu, Ni, Sn, Ag and Au.
7. The method for encapsulating a 2.5D silicon-based interposer as claimed in claim 1, wherein the passivation layer is one or more of inorganic materials or passivation glue of polymer materials; the thickness of the film is not less than 0.1 μm,
the inorganic material includes SiO2, SiC, and SiN.
8. The method of claim 1, wherein the molding compound is a resin material.
9. The utility model provides a 2.5D silica-based keysets packaging structure which characterized in that includes:
the silicon substrate (101), a cut-off layer (102) is deposited on the front surface of the silicon substrate (101), and a TSG groove is etched on the back surface of the silicon substrate and is filled with a high polymer material (105); wherein a passivation layer (103) and a first layer rewiring (104) are formed between the silicon substrate (101) and the high polymer material (105);
n-layer rewirings (106) connected to the first-layer rewirings (104);
the heterogeneous chips are welded on the n layers of rewirings (106) through micro bumps (303);
the cut-off layer (102) is provided with an opening, and n layers of rewiring (112), a solder resist layer (111) and a bump (113) are formed.
10. The 2.5D silicon-based interposer package structure of claim 9, wherein the heterogeneous chip is encapsulated by a molding compound (107).
CN201910924797.7A 2019-09-27 2019-09-27 2.5D silicon-based adapter plate packaging method and structure Active CN110600383B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111463137A (en) * 2020-05-22 2020-07-28 中国电子科技集团公司第五十八研究所 Silicon-based three-dimensional fan-out integrated packaging method and structure thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157316A1 (en) * 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
US20150214077A1 (en) * 2014-01-24 2015-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of Packaging and Dicing Semiconductor Devices and Structures Thereof
CN106129023A (en) * 2016-08-30 2016-11-16 华天科技（昆山）电子有限公司 The fan-out packaging structure of two-sided attachment and method for packing
CN109300837A (en) * 2017-07-25 2019-02-01 华天科技（昆山）电子有限公司 Slim 3D fan-out packaging structure and wafer-level packaging method
CN210296298U (en) * 2019-09-27 2020-04-10 中国电子科技集团公司第五十八研究所 2.5D silicon-based keysets packaging structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157316A1 (en) * 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
US20150214077A1 (en) * 2014-01-24 2015-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of Packaging and Dicing Semiconductor Devices and Structures Thereof
CN106129023A (en) * 2016-08-30 2016-11-16 华天科技（昆山）电子有限公司 The fan-out packaging structure of two-sided attachment and method for packing
CN109300837A (en) * 2017-07-25 2019-02-01 华天科技（昆山）电子有限公司 Slim 3D fan-out packaging structure and wafer-level packaging method
CN210296298U (en) * 2019-09-27 2020-04-10 中国电子科技集团公司第五十八研究所 2.5D silicon-based keysets packaging structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111463137A (en) * 2020-05-22 2020-07-28 中国电子科技集团公司第五十八研究所 Silicon-based three-dimensional fan-out integrated packaging method and structure thereof
CN111463137B (en) * 2020-05-22 2024-05-28 中国电子科技集团公司第五十八研究所 Silicon-based three-dimensional fan-out integrated packaging method and structure thereof

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