CN210296298U

CN210296298U - 2.5D silicon-based keysets packaging structure

Info

Publication number: CN210296298U
Application number: CN201921627126.6U
Authority: CN
Inventors: 王成迁
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2019-09-27
Filing date: 2019-09-27
Publication date: 2020-04-10
Anticipated expiration: 2029-09-27

Abstract

The utility model discloses a 2.5D silica-based keysets packaging structure belongs to integrated circuit packaging technology field. The 2.5D silicon-based adapter plate packaging structure comprises a silicon substrate, n layers of rewiring and a plurality of heterogeneous chips; the front surface of the silicon substrate is deposited with a cut-off layer, and the back surface of the silicon substrate is etched with a TSG groove and filled with a high polymer material; a passivation layer and a first layer of rewiring are formed between the silicon substrate and the high polymer material, and a metal welding pad is formed at the bottom of the TSG groove; the n-layer rewiring is connected with the first-layer rewiring; a plurality of heterogeneous chips are welded on the n layers of redistribution lines through the micro-bumps; the cut-off layer is provided with an opening, and n layers of rewiring, a solder mask layer and salient points are formed. The utility model discloses can realize the preparation of the 2.5D silicon-based keysets of no TSV through-hole, reach the three-dimensional integrated encapsulation of different functions, the heterogeneous chip of processing procedure, with low costs, simple process, production efficiency improves, is fit for extensive volume production and uses.

Description

2.5D silicon-based keysets packaging structure

Technical Field

The utility model relates to an integrated circuit packaging technology field, in particular to silicon-based keysets wafer level packaging structure of 2.5D.

Background

At present, the traditional single-function chip package can not meet the development requirements of integration, miniaturization and intellectualization of electronic products. There is an increasing interest in implementing multi-functional chip system-in-package (soc) packages by fan-out (e.g., integrated fan-out package InFO and silicon-on-chip fan-out package eSiFO) and interposer (e.g., chip-on-wafer (cofos) and embedded multi-chip interconnect bridge (EMIB)). The application of these advanced packaging technologies breaks through the physical limit barriers of wafer fabrication, and continues moore's law. Therefore, the realization of heterogeneous chip system-level integration by reconstructing wafer fan-out packages and three-dimensional stacked packages becomes the research and development focus of advanced packages and high-performance wafer-level packages at the present stage. Among them, TSV (Through Silicon Vias) interconnection is the basis of three-dimensional stacked package technology, and vertical interconnection Through TSV is also a trend of high-density integrated package. However, the TSV technology is difficult, and expensive etching, electroplating, deposition and chemical mechanical polishing equipment are required, which is difficult to be accepted by common packaging factories.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a 2.5D silicon-based keysets packaging structure, through preparation TSG recess and form the metal weld pad in its bottom, need not the preparation of TSV through-hole, accomplish the interconnection of silicon-based positive and negative to solve the big and with high costs problem of the three-dimensional integrated packaging of TSV through-hole preparation technology degree of difficulty.

In order to solve the technical problem, the utility model provides a 2.5D silica-based keysets packaging structure, include:

the front surface of the silicon substrate is deposited with a cut-off layer, and the back surface of the silicon substrate is etched with a TSG groove and filled with a high polymer material; a passivation layer and a first layer of rewiring are formed between the silicon substrate and the high polymer material, and a metal welding pad is formed at the bottom of the TSG groove;

n layers of rewiring lines connected to the first layer of rewiring lines;

the heterogeneous chips are welded on the n layers of redistribution lines through the micro-bumps;

the cut-off layer is provided with an opening, and n layers of rewiring, a solder mask layer and salient points are formed.

Optionally, the heterogeneous chip is plastically packaged by a plastic packaging material, and the plastic packaging material is a resin material.

Optionally, the depth of the TSG groove is more than 1 μm, the groove angle θ is an obtuse angle, i.e., 90 ° < θ <180 °, and the number is not less than 1.

Optionally, the material of the cut-off layer is one or more of inorganic materials, the thickness of the cut-off layer is not less than 0.1 μm,

the inorganic material includes SiO2, SiC, and SiN.

Optionally, the passivation layer is one or more of inorganic materials or passivation glue of high polymer materials; the thickness of the film is not less than 0.1 μm,

the inorganic material includes SiO2, SiC, and SiN.

Optionally, the length and width of the metal pad are both more than 1 μm, the thickness is more than 0.1 μm, and the material is one or more of metal materials; wherein the content of the first and second substances,

the metal material includes Cu, Ni, Sn, Ag and Au.

The 2.5D silicon-based adapter plate packaging structure provided by the utility model comprises a silicon substrate, n layers of rewiring and a plurality of heterogeneous chips; the front surface of the silicon substrate is deposited with a cut-off layer, and the back surface of the silicon substrate is etched with a TSG groove and filled with a high polymer material; a passivation layer and a first layer of rewiring are formed between the silicon substrate and the high polymer material, and a metal welding pad is formed at the bottom of the TSG groove; the n-layer rewiring is connected with the first-layer rewiring; a plurality of heterogeneous chips are welded on the n layers of redistribution lines through the micro-bumps; the cut-off layer is provided with an opening, and n layers of rewiring, a solder mask layer and salient points are formed. The utility model discloses can realize the preparation of 2.5D silica-based keysets, reach the three-dimensional integrated encapsulation of different functions, the heterogeneous chip of processing procedure, production efficiency improves, is fit for extensive volume production and uses.

Drawings

Fig. 1 is a schematic view of a 2.5D silicon-based interposer package structure provided in the present invention;

FIG. 2 is a schematic diagram of a silicon-based front side deposition stop layer;

FIG. 3 is a schematic view of a glass carrier structure;

FIG. 4 is a schematic diagram of a bonded glass carrier and silicon substrate;

FIG. 5 is a schematic diagram of the silicon substrate after etching the TSG groove and depositing a passivation layer;

FIG. 6 is a schematic diagram of a first layer of rewiring on a silicon-based backside;

FIG. 7 is a schematic top view of a metal pad array formed at the bottom of a TSG groove;

FIG. 8 is a schematic view of the TSG groove filled with polymer material and then subjected to n-layer redistribution;

FIG. 9 is a schematic diagram of a silicon-based backside flip-chip bonded heterogeneous chip;

FIG. 10 is a schematic diagram of a heterogeneous chip after molding;

fig. 11 is a schematic view after an opening is etched in the stop layer.

Detailed Description

The following provides a further detailed description of the 2.5D silicon-based interposer package structure according to the present invention with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Example one

The utility model provides a 2.5D silicon-based adapter plate packaging structure, the structure of which is shown in figure 1 and comprises a silicon substrate 101, n layers of rewiring 106 and a plurality of heterogeneous chips; specifically, a cut-off layer 102 is deposited on the front surface of the silicon substrate 101, and a TSG groove is etched on the back surface and filled with a polymer material 105; the material of the cut-off layer 102 is one or more of inorganic materials, the thickness of the cut-off layer is not less than 0.1 μm, and the inorganic materials comprise SiO2, SiC and SiN; the depth of the TSG groove is more than 1 μm, the groove angle theta is an obtuse angle, namely 90 degrees < theta <180 degrees, and the number is not less than 1;

a passivation layer 103 and a first layer rewiring 104 are formed between the silicon substrate 101 and the high polymer material 105, and a metal pad 110 is formed at the bottom of the TSG groove; the passivation layer 103 is one or more of inorganic materials or passivation glue of high polymer materials; the thickness of the material is not less than 0.1 μm, and the inorganic material comprises SiO2, SiC and SiN; the n-layer rewiring 106 is connected to the first-layer rewiring 104; a plurality of heterogeneous chips (including heterogeneous chip 301 and heterogeneous chip 302) are soldered on the n-layer rewiring 106 through micro bumps 303.

Specifically, the cut-off layer 102 is provided with an opening, and n layers of rewiring 112, a solder resist layer 111 and a bump 113 are formed; the heterogeneous chip is plastically packaged by a plastic packaging material 107, and the plastic packaging material 107 is a resin material.

The utility model provides a 2.5D silica-based keysets packaging structure prepares through following method:

a silicon substrate 101 and a glass carrier plate are first provided. As shown in fig. 2, a cut-off layer 102 is deposited on the front surface of the silicon substrate 101, the cut-off layer 102 is made of one or more inorganic materials, the thickness of the cut-off layer is not less than 0.1 μm, and the inorganic materials include SiO2, SiC and SiN; as shown in fig. 3, the glass carrier plate comprises a bonding glass 201 and a temporary bonding laser reaction layer 202 formed on the bonding glass 201, wherein the thickness of the bonding glass 201 is not less than 100 μm; the thickness of the temporary bonding laser reaction layer 202 is not less than 0.1 μm. The temporary bonding laser reaction layer 202 is bonded with the cut-off layer 102 through a temporary bonding glue 203, as shown in fig. 4; the thickness of the temporary bonding paste 203 is not less than 1 μm.

Referring to fig. 5, the back surface of the silicon substrate 101 is thinned to a target thickness by a grinding or etching process; and etching a TSG groove 114 on the back surface of the silicon substrate 101 by using dry etching, wherein the size of the TSG groove 114 is determined according to the electrical interconnection density of the front surface and the back surface of the silicon substrate 101, the depth is more than 1 mu m, the groove angle theta is an obtuse angle, namely 90 degrees < theta <180 degrees, and the number is not less than 1. After the TSG groove 114 is etched, depositing a passivation layer 103 on the back surface of the silicon substrate 101, wherein the passivation layer 103 is one or more of inorganic materials or passivation glue of high polymer materials; the thickness of the material is not less than 0.1 μm, and the inorganic material comprises SiO2, SiC and SiN; then, a first layer of rewiring 104 is manufactured on the back surface of the silicon substrate 101 through photolithography, physical vapor deposition, electroplating and electroless plating processes, as shown in fig. 6.

Forming a metal pad 110 at the bottom of the TSG groove 114, and forming an array by a plurality of metal pads 110, as shown in fig. 7; preferably, the length and the width of the metal pad 110 are both more than 1 μm, the thickness is more than 0.1 μm, and the material is one or more of metal materials; wherein the metal material comprises Cu, Ni, Sn, Ag and Au;

as shown in fig. 8, the TSG groove 114 is filled with the polymer material 105, and is opened at the first layer re-wiring 104, and interconnection with the first layer re-wiring 104 is achieved by the n-layer re-wiring 106;

as shown in fig. 9, heterogeneous chips (including heterogeneous chip 301 and heterogeneous chip 302) are interconnected with n-layer rewiring 106 through micro bumps 303 by a flip-chip bonding process; then, as shown in fig. 10, the heterogeneous chip is plastically packaged by a plastic package material 107; the plastic packaging material 107 is a resin material;

removing the glass carrier, cleaning the temporary bonding glue 203 to expose the stop layer 102, and forming an opening 108 at the metal pad 110 by dry etching, wherein the size of the opening 108 is smaller than that of the metal pad 110, as shown in fig. 11;

finally, an n-layer rewiring 112 is formed by using a rewiring process, a solder mask layer 111 and bumps 113 are manufactured, and finally, the semiconductor chip is cut into single packaged chips to complete final packaging, as shown in fig. 1.

The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.

Claims

1. The utility model provides a 2.5D silica-based keysets packaging structure which characterized in that includes:

the silicon substrate (101), a cut-off layer (102) is deposited on the front surface of the silicon substrate (101), and a TSG groove is etched on the back surface of the silicon substrate and is filled with a high polymer material (105); a passivation layer (103) and a first layer of rewiring (104) are formed between the silicon substrate (101) and the high polymer material (105), and a metal bonding pad (110) is formed at the bottom of the TSG groove;

n-layer rewirings (106) connected to the first-layer rewirings (104);

the heterogeneous chips are welded on the n layers of rewirings (106) through micro bumps (303);

the cut-off layer (102) is provided with an opening, and n layers of rewiring (112), a solder resist layer (111) and a bump (113) are formed.

2. The 2.5D silicon-based interposer package structure of claim 1, wherein the heterogeneous chip is encapsulated by a molding compound (107), and the molding compound (107) is a resin material.

3. The 2.5D silicon-based interposer package of claim 1, wherein the TSG recess has a depth of 1 μm or more, and a recess angle θ is an obtuse angle, i.e., 90 ° < θ <180 °, and the number is not less than 1.

4. The 2.5D silicon-based interposer package structure of claim 1, wherein the material of the stop layer (102) is one or more inorganic materials, the thickness of which is not less than 0.1 μm,

the inorganic material includes SiO2, SiC, and SiN.

5. The 2.5D silicon-based interposer package structure of claim 1, wherein the passivation layer (103) is one or more of inorganic materials or passivation glue of polymer materials; the thickness of the film is not less than 0.1 μm,

the inorganic material includes SiO2, SiC, and SiN.

6. The 2.5D silicon-based interposer package structure of claim 1, wherein the metal pads (110) have a length and a width of 1 μm or more and a thickness of 0.1 μm or more, and are made of one or more metal materials; wherein the content of the first and second substances,

the metal material includes Cu, Ni, Sn, Ag and Au.