CN110610868A - 3D fan-out type packaging method and structure - Google Patents

3D fan-out type packaging method and structure Download PDF

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Publication number
CN110610868A
CN110610868A CN201910924788.8A CN201910924788A CN110610868A CN 110610868 A CN110610868 A CN 110610868A CN 201910924788 A CN201910924788 A CN 201910924788A CN 110610868 A CN110610868 A CN 110610868A
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layer
silicon substrate
chip
rewiring
tsg
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王成迁
明雪飞
吉勇
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CETC 58 Research Institute
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CETC 58 Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
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    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • General Physics & Mathematics (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a 3D fan-out type packaging method and a structure, and belongs to the technical field of integrated circuit packaging. Firstly, providing a silicon substrate and a glass carrier plate, wherein the front surface of the silicon substrate is bonded with the glass carrier plate through a cut-off layer; etching a TSG (through Silicon groove) groove and a TSV Silicon through hole on the back surface of the Silicon substrate, and forming a passivation layer and a first layer of rewiring; then manufacturing a metal welding pad and a through hole welding pad, manufacturing a buffer layer on the back surface of the silicon substrate and opening the surface of the buffer layer; embedding the chip into the TSG groove, filling a gap between the chip and the silicon substrate with a dry film material, and opening a bonding pad of the chip and a first layer of wiring; then, wiring the n layers again, interconnecting the heterogeneous chips with the n layers of rewiring through the micro-bumps, and plastically packaging the heterogeneous chips through a plastic package material; removing the glass carrier plate to expose the cut-off layer, and opening the metal welding pads and the through hole welding pads; and sequentially forming n layers of rewiring, a solder mask layer and salient points, and finally cutting into single packaged chips to finish final packaging.

Description

3D fan-out type packaging method and structure
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a 3D fan-out type wafer level packaging method and structure.
Background
The dsp module is the core and brain of electronic products, and the microsystem technology based on high performance wafer level packaging is a necessary choice in the post-molarity (More Moore). Microsystem technology can realize high-density integration of differential heterogeneous functional chips, which accelerates and promotes the development of miniaturization, intellectualization, multi-functionalization and low power consumption of electronic devices. In the post-molar age, from the whole system level, how to integrate the supply chains of the chips that are linked by the loops is the center of gravity for future development, and the sealing and testing will also play an important role. With advanced packaging technology, the semiconductor world will be another situation, which has also led to the growth of packaging technology that has been silent for thirty years.
Among them, three-dimensional (3D) fan-out type wafer level packaging can achieve differentiated functional chip integration, and while the integration is high, the final packaging size is reduced, and the performance of the microsystem assembly is improved. Representative are the English-flying-eWLB, Taiji-elctric InFO and Huatian-technology eSiFO. Generally, to achieve three-dimensional integration, via technologies, including through-silicon vias (TSVs) and through-resin vias (TMVs), are required. As chip fabrication moves toward 7nm process and smaller pitches, the number of I/os of chips increases, the density of substrate (including silicon-based and resin-based) front-back interconnects in three-dimensional fan-out increases, and more vias are needed. In order to ensure the interconnection of the front and back sides of the substrate, the fan-out area needs to be increased or the aperture of the through hole needs to be reduced, which increases the packaging size or technical difficulty and the manufacturing cost.
Disclosure of Invention
The invention aims to provide a 3D fan-out type packaging method and a structure, which can increase the number of vertical interconnection I/O (input/output) of the front side and the back side of 3D fan-out type packaging by manufacturing metal welding pads capable of realizing interconnection of the front side and the back side of a silicon substrate at the bottom of a buried chip, and solve the problems of large fan-out area, large process difficulty and high cost of high-density vertical interconnection in the conventional three-dimensional fan-out integrated packaging.
In order to solve the technical problem, the invention provides a 3D fan-out packaging method, which includes:
providing a silicon substrate and a glass carrier plate, wherein the front surface of the silicon substrate is bonded with the glass carrier plate through a cut-off layer;
etching the TSG groove and the TSV on the back surface of the silicon substrate, forming a passivation layer and a first layer of rewiring, and forming a metal welding pad and a through hole welding pad on the bottom of the TSG groove and the bottom of the TSV respectively;
manufacturing a buffer layer on the back surface of the silicon substrate and opening the surface of the buffer layer;
embedding the chip into the TSG groove, filling a gap between the chip and the silicon substrate with a dry film material, and opening a bonding pad of the chip and a first layer of wiring;
re-wiring the n layers, interconnecting the heterogeneous chips with the n layers of re-wiring lines through the micro-bumps, and plastically packaging the heterogeneous chips through a plastic packaging material;
removing the glass carrier plate to expose the cut-off layer, and opening the metal welding pads and the through hole welding pads;
and sequentially forming n layers of rewiring, a solder mask layer and salient points, and finally cutting into single packaged chips to finish final packaging.
Optionally, the glass carrier plate comprises bonding glass and a temporary bonding laser reaction layer formed on the bonding glass;
the temporary bonding laser reaction layer is bonded with the cut-off layer through temporary bonding glue;
the thickness of the bonding glass is not less than 100 μm; the thickness of the temporary bonding glue is not less than 1 μm, and the thickness of the temporary bonding laser reaction layer is not less than 0.1 μm.
Optionally, etching the TSG groove and the TSV through silicon via on the back side of the silicon substrate and forming the passivation layer and the first layer of rewiring includes:
thinning the back surface of the silicon substrate to a target thickness by a grinding or etching process;
etching a TSG groove and a TSV silicon through hole on the back surface of the silicon substrate by using a dry etching method, wherein the depth of the TSG groove is more than 1 mu m, the groove angle theta is an obtuse angle, namely 90 degrees < theta <180 degrees, and the number of the grooves is not less than 1; the diameter of the TSV silicon through holes is more than 0.1 mu m, the depth of the TSV silicon through holes is consistent with that of the TSG grooves, and the number of the TSV silicon through holes is not less than 1;
depositing a passivation layer on the back surface of the silicon substrate;
and preparing a first layer of rewiring on the back surface of the silicon substrate through photoetching, physical vapor deposition, electroplating and chemical plating processes, wherein the first layer of rewiring is distributed on the back surface of the silicon substrate and in the TSV.
Optionally, the length and width of the metal pad are both more than 1 μm, and the thickness is more than 0.1 μm; the diameter of the through hole welding pad is more than 0.1 mu m, and the thickness of the through hole welding pad is more than 0.1 mu m; the metal welding pad and the through hole welding pad are made of one or more metal materials; wherein the content of the first and second substances,
the metal material includes Cu, Ni, Sn, Ag and Au.
Optionally, the chip is bonded to the buffer layer by a permanent bonding adhesive, and the chip is a functional chip or an interconnection chip;
the functional chip comprises RF, FPGA, DSP, GPU and CPU;
the interconnect chip includes a bridge chip.
Optionally, the material of the cut-off layer is one or more of inorganic materials, the thickness of the cut-off layer is not less than 0.1 μm,
the inorganic material includes SiO2, SiC, and SiN.
Optionally, the passivation layer is one or more of inorganic materials or passivation glue of high polymer materials; the thickness of the film is not less than 0.1 μm,
the inorganic material includes SiO2, SiC, and SiN.
Optionally, the buffer layer is one or more of inorganic materials or a high polymer material, and the thickness of the buffer layer is more than 1 μm; wherein the content of the first and second substances,
the inorganic material includes SiO2, SiN, and SiC;
the polymer material includes a resin and a polyimide material.
The invention also provides a 3D fan-out type packaging structure, which comprises:
the front surface of the silicon substrate is deposited with a stop layer, the back surface of the silicon substrate is etched with a TSG groove and a TSV silicon through hole, and a chip is embedded in the TSG groove;
the n layers of rewiring wires are connected with the bonding pads of the chip;
the heterogeneous chips are welded on the n layers of redistribution lines through the micro-bumps; the heterogeneous chip is plastically packaged by a plastic packaging material;
the cut-off layer is provided with an opening, and n layers of rewiring, a solder mask layer and salient points are formed.
Optionally, a passivation layer, a first rewiring layer and a buffer layer are sequentially formed on the back surface of the silicon substrate; the first layer of rewiring is distributed on the back surface of the silicon substrate and in the TSV.
The invention provides a 3D fan-out type packaging method and a structure, firstly, a silicon substrate and a glass carrier plate are provided, and the front surface of the silicon substrate is bonded with the glass carrier plate through a cut-off layer; etching the TSG groove and the TSV on the back surface of the silicon substrate, forming a passivation layer and a first layer of rewiring, and forming a metal welding pad and a through hole welding pad on the bottom of the TSG groove and the bottom of the TSV respectively; manufacturing a buffer layer on the back surface of the silicon substrate and opening the surface of the buffer layer; embedding the chip into the TSG groove, filling a gap between the chip and the silicon substrate with a dry film material, and opening a bonding pad of the chip and a first layer of wiring; then, wiring the n layers again, interconnecting the heterogeneous chips with the n layers of rewiring through the micro-bumps, and plastically packaging the heterogeneous chips through the plastic package substrate; removing the glass carrier plate to expose the cut-off layer, and opening the metal welding pads and the through hole welding pads; and sequentially forming n layers of rewiring, a solder mask layer and salient points, and finally cutting into single packaged chips to finish final packaging.
According to the invention, the metal welding pad and the through hole welding pad are manufactured on the back surface of the silicon substrate, so that the vertical interconnection density of the silicon substrate in unit area is greatly increased, the interconnection problem of a high-density I/O chip is solved, the three-dimensional integration density is increased, the manufacturing method is simple and convenient, and the method is suitable for large-scale mass production.
Drawings
FIG. 1 is a flow diagram of a 3D fan-out packaging method provided by the present invention;
FIG. 2 is a schematic illustration of a silicon-based front side deposition stop layer;
FIG. 3 is a schematic view of a glass carrier plate;
FIG. 4 is a schematic diagram of a bonded glass carrier and silicon substrate;
FIG. 5 is a schematic diagram of a silicon-based backside etched TSG trench and TSV silicon vias;
FIG. 6 is a schematic illustration of a silicon-based backside with a passivation layer and a first layer of rewiring;
FIG. 7 is a schematic diagram of a metal pad and via pad array;
FIG. 8 is a schematic diagram of a silicon-based backside buffer layer and openings;
FIG. 9 is a schematic diagram of a silicon-based backside buried chip;
FIG. 10 is a schematic view of a silicon-based backside filled with dry film material and openings;
FIG. 11 is a schematic diagram of a silicon-based backside after n layers are formed and re-routed;
FIG. 12 is a schematic diagram of a silicon-based backside flip-chip bonded heterogeneous chip;
FIG. 13 is a schematic diagram of a silicon-based backside after plastic encapsulation;
FIG. 14 is a schematic diagram of a front side of a silicon substrate with a glass carrier removed and an opening etched;
fig. 15 is a schematic diagram of a solder resist layer and bumps fabricated and diced into individual packages.
Detailed Description
The following describes a 3D fan-out packaging method and structure according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a 3D fan-out type packaging method, the flow of which is shown in figure 1, and the method comprises the following steps:
step S11, providing a silicon substrate and a glass carrier plate, wherein the front surface of the silicon substrate is bonded with the glass carrier plate through a cut-off layer;
step S12, etching the TSG groove and the TSV on the back surface of the silicon substrate and forming a passivation layer and a first layer of rewiring;
step S13, respectively forming a metal welding pad and a through hole welding pad at the bottom of the TSG groove and the bottom of the TSV, manufacturing a buffer layer on the back surface of the silicon substrate and opening the surface of the buffer layer;
step S14, embedding the chip into the TSG groove, filling the gap between the chip and the silicon substrate with a dry film material, and opening the bonding pad of the chip and the first layer of wiring;
step S15, performing n-layer rewiring, interconnecting heterogeneous chips with n-layer rewiring through micro-bumps, and plastically packaging the heterogeneous chips through plastic packaging materials;
step S16, removing the glass carrier plate to expose the cut-off layer, and opening at the metal welding pad and the through hole welding pad;
and step S17, sequentially forming n layers of rewiring, solder mask and salient points, and finally cutting into single packaged chips to finish final packaging.
Specifically, a silicon substrate 101 and a glass carrier are provided first. As shown in fig. 2, a cut-off layer 102 is deposited on the front surface of the silicon substrate 101, and the cut-off layer 102 is made of one or more inorganic materials, such as SiO2, SiC, SiN, and the like, and has a thickness not less than 0.1 μm; the glass carrier plate is shown in fig. 3 and comprises bonding glass 201 and a temporary bonding laser reaction layer 202 formed on the bonding glass 201, wherein the temporary bonding laser reaction layer 202 is bonded with the cut-off layer 102 through a temporary bonding glue 203, as shown in fig. 4; wherein the thickness of the bonding glass 201 is not less than 100 μm; the thickness of the temporary bonding glue 203 is not less than 1 μm, and the thickness of the temporary bonding laser reaction layer 202 is not less than 0.1 μm.
And then, thinning the back side of the silicon substrate 101 to a target thickness through a grinding or etching process, and etching the TSG groove 103 and the TSV silicon through hole 117 on the back side of the silicon substrate 101 by using a dry etching method, as shown in fig. 5. The size of the TSG groove 103 is determined according to the size of a chip to be embedded, the depth is more than 1 μm, the groove angle theta is an obtuse angle, namely 90 degrees < theta <180 degrees, and the number is not less than 1; the diameter of the TSV 117 is more than 0.1 mu m, the depth of the TSV is consistent with that of the TSG groove, and the number of the TSV is not less than 1 according to the interconnection density of the front side and the back side of the silicon substrate 101; then depositing a passivation layer 104 on the back surface of the silicon substrate 101; preparing a first layer rewiring 105 on the back surface of the silicon substrate 101 through photoetching, physical vapor deposition, electroplating and electroless plating processes, as shown in FIG. 6; further, the passivation layer 104 may be one or more of inorganic materials, such as SiO2, SiC, SiN, and the like, and may also be a passivation glue of a polymer material, and the thickness of the passivation layer 104 is more than 0.1 μm, so as to meet the requirement of electrical connection; further, the first layer rewiring 105 is distributed on the back surface of the silicon substrate 101 and in the TSV 117.
Forming a metal pad 112 at the bottom of the TSG groove 103, forming a via pad 116 at the bottom of the TSV silicon via 117, and forming an array by the plurality of metal pads 112 and the plurality of via pads 116, as shown in fig. 7; the length and the width of the metal welding pad 112 are both more than 1 μm, the thickness is more than 0.1 μm, the diameter of the through hole welding pad is more than 0.1 μm, and the thickness is more than 0.1 μm; the metal welding pad and the through hole welding pad are made of one or more metal materials; wherein the metal material comprises Cu, Ni, Sn, Ag and Au; manufacturing a buffer layer 106 on the back surface of the silicon substrate 101 by using a spraying method and opening the surface of the buffer layer, as shown in fig. 8, so that the first layer rewiring 105 can be connected with the outside; the buffer layer 106 is one or more of inorganic materials, including SiO2, SiN, SiC, etc.; the material can also be a high molecular material, including resin and polyimide materials, and the thickness of the material is more than 1 μm;
embedding a chip 301 in the TSG groove 103, wherein the chip 301 is bonded to the buffer layer 106 by a permanent adhesive 305 with a bonding pad 304 facing outwards, as shown in fig. 9; the chip 301 is a functional chip including RF, FPGA, DSP, GPU, and CPU, or an interconnect chip including a bridge chip; referring to fig. 10, a dry film material 107 is used to fill the gap between the chip 301 and the silicon substrate 101, and is opened at the bonding pad 304 and the first layer of wiring 105;
as shown in fig. 11, n-layer rewiring 108 is formed using photolithography, physical vapor deposition, electroplating, and electroless plating processes; as shown in fig. 12, heterogeneous chips (including heterogeneous chip 302 and heterogeneous chip 303) are interconnected with the n-layer rewiring 108 through micro bumps 306 by using a flip-chip bonding process, wherein the heterogeneous chips include RF, FPGA, DSP, AD, DA, and other functional chips; as shown in fig. 13, the heterogeneous chip is plastically packaged by a plastic package material 109;
next, referring to fig. 14, the glass carrier is removed and the temporary bonding glue 203 is cleaned to expose the stop layer 102, an opening 110 is formed at the metal pad 112 and the via pad 116 by dry etching, and the size of the opening 110 is smaller than the size of the metal pad 112 and the size of the TSV 117;
as shown in fig. 15, an n-layer rewiring 115 is formed by a rewiring process, and a solder resist layer 113 and bumps 114 are formed, and finally cut into single packaged chips to complete the final package.
The 3D fan-out type packaging structure manufactured by the 3D fan-out type packaging method is shown in fig. 15 and comprises a silicon substrate 101, n layers of rewiring 108 and a plurality of heterogeneous chips, wherein a stop layer 102 is deposited on the front surface of the silicon substrate 101, a TSG groove and a TSV silicon through hole are etched on the back surface of the silicon substrate, and a chip 301 is embedded in the TSG groove; the n-layer rewiring 108 is connected with a bonding pad 304 of the chip 301; a plurality of heterogeneous chips (including heterogeneous chip 302 and heterogeneous chip 303) welded on the n layers of rewirings 108 through micro bumps 306; the heterogeneous chip is plastically packaged by a plastic packaging material 109;
the cut-off layer 102 is formed with an opening, and n layers of rewiring 115, solder resist 113, and bumps 114 are formed.
Specifically, with reference to fig. 15, a passivation layer 104, a first redistribution layer 105 and a buffer layer 106 are sequentially formed on the back surface of the silicon substrate 101; the first layer rewiring 105 is distributed on the back surface of the silicon substrate 101 and in the TSV.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A3D fan-out packaging method, comprising:
providing a silicon substrate and a glass carrier plate, wherein the front surface of the silicon substrate is bonded with the glass carrier plate through a cut-off layer;
etching the TSG groove and the TSV on the back surface of the silicon substrate and forming a passivation layer and a first layer of rewiring;
respectively forming a metal welding pad and a through hole welding pad at the bottom of the TSG groove and the bottom of the TSV, manufacturing a buffer layer on the back surface of the silicon substrate and opening the surface of the buffer layer;
embedding the chip into the TSG groove, filling a gap between the chip and the silicon substrate with a dry film material, and opening a bonding pad of the chip and a first layer of wiring;
re-wiring the n layers, interconnecting the heterogeneous chips with the n layers of re-wiring lines through the micro-bumps, and plastically packaging the heterogeneous chips through a plastic packaging material;
removing the glass carrier plate to expose the cut-off layer, and opening the metal welding pads and the through hole welding pads;
and sequentially forming n layers of rewiring, a solder mask layer and salient points, and finally cutting into single packaged chips to finish final packaging.
2. The 3D fan-out packaging method of claim 1, wherein the glass carrier comprises a bonding glass and a temporary bonding laser reaction layer formed on the bonding glass;
the temporary bonding laser reaction layer is bonded with the cut-off layer through temporary bonding glue;
the thickness of the bonding glass is not less than 100 μm; the thickness of the temporary bonding glue is not less than 1 μm, and the thickness of the temporary bonding laser reaction layer is not less than 0.1 μm.
3. The 3D fan-out packaging method of claim 1, wherein etching the TSG groove and the TSV through silicon via on the back side of the silicon substrate and forming the passivation layer and the first layer rewiring comprises:
thinning the back surface of the silicon substrate to a target thickness by a grinding or etching process;
etching a TSG groove and a TSV silicon through hole on the back surface of the silicon substrate by using a dry etching method, wherein the depth of the TSG groove is more than 1 mu m, the groove angle theta is an obtuse angle, namely 90 degrees < theta <180 degrees, and the number of the grooves is not less than 1; the diameter of the TSV silicon through holes is more than 0.1 mu m, the depth of the TSV silicon through holes is consistent with that of the TSG grooves, and the number of the TSV silicon through holes is not less than 1;
depositing a passivation layer on the back surface of the silicon substrate;
and preparing a first layer of rewiring on the back surface of the silicon substrate through photoetching, physical vapor deposition, electroplating and chemical plating processes, wherein the first layer of rewiring is distributed on the back surface of the silicon substrate and in the TSV.
4. The 3D fan-out packaging method of claim 1, wherein the metal pads are each more than 1 μm long and wide and more than 0.1 μm thick; the diameter of the through hole welding pad is more than 0.1 mu m, and the thickness of the through hole welding pad is more than 0.1 mu m; the metal welding pad and the through hole welding pad are made of one or more metal materials; wherein the content of the first and second substances,
the metal material includes Cu, Ni, Sn, Ag and Au.
5. The 3D fan-out packaging method of claim 1, in which the die is bonded to the buffer layer by a permanent adhesive glue, the die being a functional die or an interconnect die;
the functional chip comprises RF, FPGA, DSP, GPU and CPU;
the interconnect chip includes a bridge chip.
6. The 3D fan-out packaging method of claim 1, wherein the material of the stop layer is one or more inorganic materials, the thickness of the stop layer is not less than 0.1 μm,
the inorganic material includes SiO2, SiC, and SiN.
7. The 3D fan-out packaging method of claim 1, wherein the passivation layer is one or more of an inorganic material or a passivation glue of a polymer material; the thickness of the film is not less than 0.1 μm,
the inorganic material includes SiO2, SiC, and SiN.
8. The 3D fan-out packaging method of claim 1, wherein the buffer layer is one or more of inorganic materials or a polymer material, and the thickness of the buffer layer is more than 1 μm; wherein the content of the first and second substances,
the inorganic material includes SiO2, SiN, and SiC;
the polymer material includes a resin and a polyimide material.
9. A3D fan-out package structure, comprising:
the silicon substrate (101), a cut-off layer (102) is deposited on the front surface of the silicon substrate (101), a TSG groove and a TSV silicon through hole are etched on the back surface of the silicon substrate, and a chip (301) is buried in the TSG groove;
n layers of rewiring lines (108) connected to pads (304) of the chip (301);
a plurality of heterogeneous chips welded on the n layers of rewirings (108) through micro-bumps (306); the heterogeneous chip is plastically packaged by a plastic packaging material (109);
the cut-off layer (102) is provided with an opening (110), and n layers of rewiring (115), a solder resist layer (113) and a bump (114) are formed.
10. The 3D fan-out package structure of claim 9, wherein a passivation layer (104), a first layer of rewiring (105) and a buffer layer (106) are sequentially formed on the back side of the silicon substrate (101); the first layer of rewiring (105) is distributed on the back surface of the silicon substrate (101) and in the TSV.
CN201910924788.8A 2019-09-27 2019-09-27 3D fan-out type packaging method and structure Pending CN110610868A (en)

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