CN114334905A - System-level heterogeneous integrated packaging structure and preparation method thereof - Google Patents
System-level heterogeneous integrated packaging structure and preparation method thereof Download PDFInfo
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- CN114334905A CN114334905A CN202111451555.4A CN202111451555A CN114334905A CN 114334905 A CN114334905 A CN 114334905A CN 202111451555 A CN202111451555 A CN 202111451555A CN 114334905 A CN114334905 A CN 114334905A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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Abstract
The invention relates to a system-level heterogeneous integrated packaging structure and a preparation method thereof, belonging to the technical field of integrated circuit wafer-level packaging. The system-level heterogeneous integrated packaging structure comprises a vertical interconnection structure formed by a functional chip A and a functional chip B with a TSV structure, wherein the functional chip B with the TSV structure is firstly bonded onto a wafer carrier, then the functional chip A and the functional chip B with the TSV structure form the vertical interconnection structure through wafer-level bonding, and the vertical interconnection structure is subjected to re-wiring to form a three-dimensional packaging body. The invention prepares the high-precision vertical interconnection structure of the chip and the chip by utilizing the processes of inter-metal bonding of the chip, the wafer and the like, and then carries out advanced packaging on the vertical interconnection structure, thereby having high packaging density and efficiency and realizing multi-functional interconnection among systems.
Description
Technical Field
The embodiment of the invention relates to the technical field of integrated circuit packaging, in particular to a system-level heterogeneous integrated packaging structure and a preparation method thereof.
Background
With the increasing level of IC manufacturing, the industry recognized Moore Law (Moore Law) will go to the end: on one hand, the more the nodes of the previous manufacturing process are developed, the more tens or hundreds of times the research, development and production cost is increased; moore's law, on the other hand, ends up with its physical limits. One of the methods for extending the lifetime of moore's law is advanced packaging technology, including fan-out wafer level packaging (FOWLP), 2.5D/3D IC packaging, and further into 3D wafer stack packaging capable of heterogeneous integration. In 2016, the wafer level packaging technology developed by station accumulation has opened a new sky for everyone, and since the beginning of the world, the development of various large packaging factories and wafer factories has been intensively shifted to the fan-out type packaging technology. Through three-dimensional heterogeneous integration, chips with different functions are integrated together, system-in-package is realized, the packaging volume is remarkably reduced, the product performance is greatly improved, and the ultra molar age (More Moore) is started from now on. Through Silicon Via (TSV) technology realizes vertical interconnection between chips, through punching through holes on silicon, interconnection between chips is carried out, no lead bonding is needed, interconnection length is effectively shortened, signal transmission delay and loss are reduced, signal transmission speed and bandwidth are improved, power consumption and packaging volume are reduced, and multifunctional, high-performance, high-reliability, lighter, thinner and smaller chip system-level packaging is realized.
Disclosure of Invention
In the packaging structure, firstly, a functional chip B with a TSV structure is bonded to a slide wafer through bonding of a chip and the wafer, and then the functional chip A and the functional chip B with the TSV structure form a vertical interconnection structure through bonding of the wafer and the wafer, so that a system level function can be realized; and advanced packaging is carried out on the chip, so that multifunctional, high-performance and high-reliability chip system level packaging is realized.
In order to solve the above technical problems, the system-level heterogeneous integrated package structure of the present invention is characterized in that: the packaging structure is a packaging structure with a plurality of chips vertically interconnected and comprises a top layer, a medium layer and a bottom layer which are sequentially stacked together from top to bottom. The interposer is a functional chip B with a TSV structure, the active layer of the interposer is provided with at least one rewiring interconnection layer and a welding Pad, and TSV pads are manufactured on the back face of the active layer. The bottom layer includes a functional chip a having an active layer with pads and facing the active layer of the interposer. The intermediate layer and the bottom layer are vertically interconnected with each other through a wafer-to-wafer intermetallic bonding process; the top layer structure is formed by performing advanced packaging on the active layer of the intermediate layer to form at least one rewiring interconnection layer with micro solder balls or solder pads.
Further, the interposer of the vertical interconnection structure is a functional chip B with a TSV structure, and the chip is a single silicon-based chip.
Further, the bottom layer of the vertical interconnection structure is a functional chip A for manufacturing an integrated circuit, and the chip is an 8-inch or 12-inch wafer.
Furthermore, the top layer of the vertical interconnection structure is at least one layer of rewiring interconnection layer and is provided with micro solder balls or solder pads, and the circuit layer is made of metal materials and comprises one or more of Ti, W, Cu, Ni and Au.
Furthermore, the number of the intermediate layers formed by the functional chip B with the TSV structure is more than or equal to 1, and finally 1 or more vertical interconnection structures with the TSV structure functional chips are formed.
Further, the advanced packaging of the top layer may be a fan-out packaging process or a fan-in packaging process.
The invention also provides a manufacturing method of the system-level heterogeneous integrated packaging structure, which comprises the following steps:
step S1: providing a slide glass wafer, pasting temporary bonding glue on the surface of the slide glass wafer, and pasting the active layer surface of the functional chip B with the TSV structure of the intermediate layer downwards on the temporary bonding glue;
step S2: depositing an insulating layer on the back of the functional chip B;
step S3: continuously depositing a bonding film on the back surface of the functional chip B, and carrying out graphical processing on the bonding film so as to form a metal graph of the active surface of the functional chip A;
step S4: repeating the step S2 to the step S3 to form a bottom functional chip A wafer with the bonding film on the surface, aligning and bonding the back surface of the functional chip B with the upper surface of the functional chip A to form a bonding pair, and forming a wafer stacking structure with the metal bonding layer in the middle through bonding the wafer and the wafer through the processes of activation, cleaning, wafer alignment, pre-bonding, annealing and the like to realize the electrical vertical interconnection between the chip A and the chip B;
step S5: removing the carrier by performing a bonding removal process on the wafer stacking structure, and cleaning the temporary bonding glue;
step S6: and manufacturing a metal circuit layer and a passivation layer on the upper surface of the formed wafer top layer structure to form n layers of rewiring, growing a bump on the uppermost layer, and finally thinning, cutting and separating to finally form a single three-dimensional system-in-package unit.
Further, the step S4 includes a step of filling the bonding pair formed after bonding with resin.
The invention has the following advantages:
1) wafer level packaging is employed with the carrier wafer as the substrate, greatly reducing the risk of high warpage of the wafer due to CTE mismatch.
2) And the manufacturing process is repeated in stacking and standardized operation is adopted, so that the mass production industrialization is easy to realize.
3) And the wafer is bonded in the manufacturing process, so that the alignment precision is high, the precision can be controlled within 1 mu m, and the yield is improved.
4) By designing various chips into a vertically interconnected laminated structure, interconnection mismatch among chips with different sizes and layouts can be effectively solved, and three-dimensional system integrated packaging of chips with different functions and substrates can be flexibly realized.
Drawings
In order that the present disclosure may be more readily and clearly understood, reference will now be made in detail to the present disclosure, examples of which are illustrated in the accompanying drawings.
Fig. 1 is a schematic diagram of a functional chip B with a TSV structure attached to a carrier wafer.
Fig. 2 is a schematic view of a device wafer of functional chips a diced without thinning.
FIG. 3 is a schematic diagram of the alignment and bonding of the back side of the interposer wafer and the front side of the base wafer in the manufacturing method according to the embodiment of the invention.
Fig. 4 is a schematic diagram of the manufacturing method according to the embodiment of the invention after bonding is released.
Fig. 5 is a schematic diagram illustrating a top metal line layer after fabrication in the manufacturing method according to the embodiment of the invention. Wherein a is a fan-in wiring structure and wherein b is a fan-out wiring structure.
Fig. 6 is a schematic diagram of a vertical interconnection structure based on a plurality of functional chips with TSV structures.
As shown in the figure: 101. functional chip B, 102, TSV structure, 103, bonding film, 104, slide wafer, 105, temporary bonding glue, 206, device wafer, 207, functional chip A, 208, cutting channel, 209, chip bonding pad, 510, rewiring layer, 511 and micro solder balls.
Detailed Description
The embodiment provides a system-level heterogeneous integrated package structure, which is a multi-chip vertical interconnection package structure and comprises a top layer, an intermediate layer and a bottom layer which are sequentially stacked from top to bottom. The interposer is a functional chip B101 with a TSV structure, the active layer of the interposer is provided with at least one rewiring interconnection layer and a welding Pad, and TSV pads are manufactured on the back face of the active layer. The bottom layer includes functional die a 207 with its active layer having pads 209 and facing the active layer of the interposer. The interposer and the bottom layer achieve vertical interconnection of the functional chip a and the functional chip B through the process of inter-metal bonding of the wafer 206 to the wafer 104, and the top layer structure is formed by advanced packaging at the active layer level of the interposer, and has at least one layer of redistribution interconnect layer 510 with micro solder balls or pads 511.
The interposer of the vertical interconnection structure is a functional chip B which is provided with a TSV structure, and the chip is a single silicon-based chip.
The bottom layer of the vertical interconnection structure is a functional chip A for manufacturing an integrated circuit, and the chip is an 8-inch or 12-inch wafer.
The top layer of the vertical interconnection structure is at least one layer of rewiring interconnection layer and is provided with a micro solder ball or a solder pad, and the circuit layer is made of metal materials and comprises one or more of Ti, W, Cu, Ni and Au.
The number of the intermediate layers formed by the functional chip B with the TSV structure is more than or equal to 1, and finally, 1 or more vertical interconnection structures with the TSV structure functional chips are formed.
The advanced packaging of top layer can be fan-out packaging technology or fan-in packaging technology, and this application packaging structure mode counterpoint accuracy limit can reach 0.5 um.
The invention provides a preparation method of a system-level heterogeneous integrated packaging structure, which comprises the following steps:
step S1: providing a slide wafer 104, attaching a temporary bonding adhesive 105 on the surface of the slide wafer, and attaching the active layer of the functional chip B101 with the TSV through hole structure to the temporary bonding adhesive in a downward manner, as shown in fig. 1;
step S2: depositing an insulating layer on the back surface of the functional chip B101;
step S3: depositing a bonding film 103 on the back surface of the functional chip B101, and performing patterning processing on the bonding film, so as to form a metal pattern on the active surface of the functional chip A207, as shown in FIG. 1;
step S4: repeating the steps S2 to S3 to form a bottom functional chip a wafer 206 with the bonding film on the surface, as shown in fig. 2; aligning and bonding the back surface of the functional chip B101 and the upper surface of the functional chip a 207 to form a bonding pair, and performing processes such as activation, cleaning, wafer alignment, pre-bonding, annealing and the like to form a wafer stacking structure with the metal bonding layer in the middle through bonding between a wafer and a wafer, so as to realize the electrical vertical interconnection between the chip a and the chip B, as shown in fig. 3;
step S5: the carrier is removed by performing a de-bonding process on the wafer stack structure, and the temporary bonding paste is cleaned, as shown in fig. 4.
Step S6: carrying out wafer-level plastic packaging by using a wafer plastic packaging technology, wherein the material used for plastic packaging is a resin material; performing fan-in packaging or fan-out packaging on the upper surface of the formed wafer top layer structure, manufacturing a passivation layer and a metal circuit layer 510, forming n layers of rewiring, growing a bump 511 on the uppermost layer, finally thinning and cutting for separation, and finally forming a single three-dimensional system-in-package unit, as shown in fig. 5.
Step six: and manufacturing a metal circuit layer and a passivation layer on the upper surface of the formed wafer top layer structure to form n layers of rewiring, growing a bump on the uppermost layer, and finally thinning, cutting and separating to finally form a single three-dimensional system-in-package unit.
Further, the above steps are repeated, the number of the interposer layers formed by the functional chip B with the TSV structure is not less than 1, and finally, 1 or more vertical interconnection structures with TSV structure functional chips are formed, as shown in fig. 6.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the spirit or scope of the invention.
Claims (8)
1. A system-level heterogeneous integrated package structure is characterized in that: the packaging structure is a multi-chip vertical interconnection packaging structure and comprises a top layer, an intermediate layer and a bottom layer which are sequentially stacked together from top to bottom; the interposer is a functional chip B with a TSV structure, the active layer of the interposer is provided with at least one rewiring interconnection layer and a welding Pad, and the back of the active layer is provided with a TSV Pad; the bottom layer comprises a functional chip A, an active layer of which is provided with a welding pad and faces the active layer of the intermediate layer; the intermediate layer and the bottom layer are vertically interconnected with each other through a wafer-to-wafer intermetallic bonding process; the top layer structure is formed by performing advanced packaging on the active layer of the intermediate layer to form at least one rewiring interconnection layer with micro solder balls or solder pads.
2. The system-in-a-package heterogeneous integrated package structure of claim 1, wherein: the interposer of the vertical interconnection structure is a functional chip B which is provided with a TSV structure, and the chip is a single silicon-based chip.
3. The system-in-a-package heterogeneous integrated package structure of claim 1, wherein: the bottom layer of the vertical interconnection structure is a functional chip A for manufacturing an integrated circuit, and the chip is an 8-inch or 12-inch wafer.
4. The system-in-a-package heterogeneous integrated package structure of claim 1, wherein: the top layer of the vertical interconnection structure is at least one layer of rewiring interconnection layer and is provided with a micro solder ball or a solder pad, and the circuit layer is made of metal materials and comprises one or more of Ti, W, Cu, Ni and Au.
5. The system-in-a-package heterogeneous integrated package structure of claim 1, wherein: the number of the intermediate layers formed by the functional chip B with the TSV structure is more than or equal to 1, and finally, 1 or more vertical interconnection structures with the TSV structure functional chips are formed.
6. The system-in-a-package heterogeneous integrated package structure of claim 1, wherein: the advanced packaging of the top layer may be a fan-out packaging process or a fan-in packaging process.
7. A system-level heterogeneous integrated package manufacturing method is characterized by comprising the following steps: the manufacturing method of the vertical interconnection structure is based on the system-level heterogeneous integrated package structure building design of claim 1, and comprises the following steps:
step S1: providing a slide glass wafer, pasting temporary bonding glue on the surface of the slide glass wafer, and pasting the active layer surface of the functional chip B with the TSV structure of the intermediate layer downwards on the temporary bonding glue;
step S2: depositing an insulating layer on the back of the functional chip B;
step S3: continuously depositing a bonding film on the back surface of the functional chip B, and carrying out graphical processing on the bonding film so as to form a metal graph of the active surface of the functional chip A;
step S4: repeating the step S2 to the step S3 to form a bottom functional chip A wafer with the bonding film on the surface, aligning and bonding the back surface of the functional chip B with the upper surface of the functional chip A to form a bonding pair, and forming a wafer stacking structure with the metal bonding layer in the middle through bonding the wafer and the wafer through the processes of activation, cleaning, wafer alignment, pre-bonding, annealing and the like to realize the electrical vertical interconnection between the chip A and the chip B;
step S5: removing the carrier by performing a bonding removal process on the wafer stacking structure, and cleaning the temporary bonding glue;
step S6: and manufacturing a metal circuit layer and a passivation layer on the upper surface of the formed wafer top layer structure to form n layers of rewiring, growing a bump on the uppermost layer, and finally thinning, cutting and separating to finally form a single three-dimensional system-in-package unit.
8. The system-in-package hetero-integrated manufacturing method of claim 7, wherein: the step S4 includes resin filling of the bond pair formed after bonding.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117542794A (en) * | 2024-01-10 | 2024-02-09 | 浙江集迈科微电子有限公司 | Three-dimensional stacked packaging structure based on adapter plate and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117542794A (en) * | 2024-01-10 | 2024-02-09 | 浙江集迈科微电子有限公司 | Three-dimensional stacked packaging structure based on adapter plate and manufacturing method thereof |
| CN117542794B (en) * | 2024-01-10 | 2024-04-16 | 浙江集迈科微电子有限公司 | Three-dimensional stacked packaging structure based on adapter plate and manufacturing method thereof |
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