WO2014134758A1 - Manufacturing method for multichip system-level packaging structure - Google Patents

Manufacturing method for multichip system-level packaging structure Download PDF

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Publication number
WO2014134758A1
WO2014134758A1 PCT/CN2013/000457 CN2013000457W WO2014134758A1 WO 2014134758 A1 WO2014134758 A1 WO 2014134758A1 CN 2013000457 W CN2013000457 W CN 2013000457W WO 2014134758 A1 WO2014134758 A1 WO 2014134758A1
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chip
wafer
adapter
packaging structure
manufacturing
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PCT/CN2013/000457
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French (fr)
Chinese (zh)
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于大全
刘海燕
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华进半导体封装先导技术研发中心有限公司
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Publication of WO2014134758A1 publication Critical patent/WO2014134758A1/en

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    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
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    • H01L2224/812—Applying energy for connecting
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    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
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    • H01L2224/818—Bonding techniques
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the invention relates to a method for fabricating a multi-chip system-level package structure, in particular to a method for fabricating a 2.5D package structure in which a plurality of chips are integrated on a silicon adapter plate.
  • TSV through-silicon via
  • the package structure is formed by interconnecting the substrate with the substrate to implement certain specific functions of the electronic device. This multi-chip package increases package density and reduces pin-to-pin distance between chips, significantly increasing bandwidth between adjacent chips and reducing power consumption.
  • the object of the present invention is to overcome the deficiencies in the prior art and provide a method for manufacturing a multi-chip system-level package structure, which can be widely applied to system integration of different types of chips, and can effectively reduce the holding of the adapter board chip. Difficulty, improve the production efficiency and product yield of the chip package.
  • the method for fabricating the multi-chip system-level package structure includes the following steps:
  • step 6 performing a second electrical performance test on the adapter chip package structure formed in step 6;
  • the large-sized chip is electrically interconnected with the interposer wafer by reflow or thermocompression bonding; the small-sized chip or small-sized chip stack is completed by reflow or thermocompression bonding and the interposer Electrical interconnection of the chip.
  • the interposer wafer has a TSV vertical through silicon via metallization filling structure, and the filling material is one of copper or tungsten.
  • the large size chip area is larger than the small size chip.
  • the large size chip can be a central processing unit
  • the small size chip may be a micro mechanical system (MEMS), a CMOS image sensor, or a memory chip.
  • MEMS micro mechanical system
  • CMOS image sensor or a memory chip.
  • the advantages of the present invention are: The present invention is used to realize a multi-chip system-level package having a large difference in size. First, a large-sized chip is flip-chip mounted on an interposer wafer to form an electrical interconnection, and then the interposer wafer is cut into A single substrate is used to interconnect the small-sized chip with a single interposer chip.
  • the system-level packaging of the multi-chip is realized by the method, and the disadvantage that the ultra-thin adapter board is difficult to handle is avoided; after the electrical connection between the large-sized chip and the adapter board is completed, the electrical performance test is performed, and the partial electrical connection can be eliminated first.
  • the failed package structure improves the yield of the product; the large-size chip and the small-sized chip are respectively interconnected with the adapter board to meet different interconnection process requirements.
  • Figure 1 is a cross-sectional view of an interposer wafer with TSV and bump structures.
  • Figure 2 is a schematic diagram of the temporary bonding of the interposer wafer and the carrier wafer.
  • Figure 3 is a schematic illustration of flipping a large size chip onto an interposer wafer.
  • FIG. 4 is a schematic view of the completed adapter wafer and the carrier wafer being detached.
  • Figure 5 is a schematic illustration of flipping a small size chip onto an interposer chip.
  • Figure 6 is a schematic diagram of interconnecting an interposer chip with a substrate.
  • the package structure involved in the present invention includes:
  • Adapter plate wafer 1 having TSV through silicon via 2 and bump 3 structure, as shown in FIG. 1 , BGA (Ball Grid Array) solder joint 4 under the transfer plate wafer 1; TSV via metallization filling structure Filling material Can be one of copper or tungsten;
  • At least two types of chips to be assembled one of which is a large-sized chip 7, and the other is a small-sized chip or a small-sized chip stack 8, as shown in FIG. 5;
  • the large size chip is flipped onto the wafer 1 of the interposer;
  • the small-sized chip or small-sized chip stack 8 is mounted on the interposer chip that has completed the package once.
  • the implementation method of the multi-chip system-level package structure of the present invention is as follows:
  • the interposer wafer 1 having the vertical through silicon via 2 and the bump 3 structure is temporarily bonded to the carrier wafer 6 by using the adhesive 5;
  • the large-sized chip 7 is flip-chip mounted on the first surface of the first surface of the interposer wafer 1, and the electrical interconnection between the two is completed by reflow or thermocompression bonding;
  • the small-sized chip or the small-sized chip stack 8 is flipped onto the first surface of the first surface of the electrically good adapter chip, and the reflow (or thermocompression bonding) is completed. Electrical interconnection
  • the second surface of the adapter chip having good electrical properties is placed on the substrate, and the interconnection between the interposer and the substrate 9 is completed by return flow to form a final package structure.
  • the large-sized chip 7 of the present invention has a larger area than the small-sized chip 8.
  • the large size chip 7 can be a central processing unit (CPU), a microprocessor (MPU), a graphics processing unit (GPU), a digital signal processor (DSP), and a radio frequency transceiver.
  • the small size chip can be a micro mechanical system (MEMS), a CMOS image sensor, or a memory chip.
  • the present invention first interconnects the large size chip 7 with the interposer wafer 1, and the small size chip or small size chip stack 8 is interconnected with the diced single interposer chip. After the large-size chip 7 and the interposer wafer 1 are interconnected, the first electrical performance test is performed on the interposer chip package structure; after the small-size chip or the small-size chip stack 8 is interconnected with the interposer chip, The package structure is tested for the second electrical performance.
  • This manufacturing method avoids the problem that the ultra-thin silicon adapter plate is difficult to handle, and significantly improves the packaging efficiency and the yield of the product, and reduces the production cost.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The present invention discloses a manufacturing method for a multichip system-level packaging structure. The structure comprises an adapter panel chip having a TSV silicon through hole and a convex point structure, one chip of large size and a plurality of chips of small size or a stack of chips of small size. In the present invention, one large chip is reversely connected to an adapter panel wafer; then cutting and an electrical performance test of the adapter panel wafer are carried out; the chips of small size or the stack of chips of small size are connected with the adapter panel chip; the adapter panel packaging structure is subject to the electrical performance test again; and the adapter panel packaging structure is connected with a base plate to form a final packaging structure. The present invention has the advantage that: the manufacturing method of the present invention avoids the problem that an ultrathin silicon adapter panel is not easy to hold, obviously increases the packaging efficiency and the yield of products, and reduces the production cost.

Description

多芯片系统级封装结构的制作方法 技术领域  Multi-chip system-level package structure manufacturing method
本发明涉及一种多芯片系统级封装结构的制作方法， 具体是一种将多个芯 片集成于硅转接板上的 2.5D封装结构制作方法。  The invention relates to a method for fabricating a multi-chip system-level package structure, in particular to a method for fabricating a 2.5D package structure in which a plurality of chips are integrated on a silicon adapter plate.
背景技术 Background technique
随着电子产品不断向小型化、 多功能、 智能化的方向发展， 半导体器件的 集成度不断提高， 集成电路的特征尺寸也在不断缩小。但是， 当 IC的特征尺寸 接近物理极限时， 研究人员通过发展新技术、 新材料、 新设计方法， 研发出了 先进的封装形式来延续摩尔定律的发展。 以硅通孔 （TSV) 转接板技术为代表 的 2.5D、 3D封装形式， 将芯片集成于硅转接板上， 通过转接板进行扇出和芯 片互联， 可有效改善封装体的散热、 降低信号之间的串扰等问题。  As electronic products continue to develop in the direction of miniaturization, versatility, and intelligence, the integration of semiconductor devices continues to increase, and the feature sizes of integrated circuits are also shrinking. However, when the IC's feature size is close to the physical limit, the researchers developed advanced packaging methods to develop the development of Moore's Law by developing new technologies, new materials, and new design methods. The 2.5D and 3D packages, represented by through-silicon via (TSV) interposer technology, integrate the chip on the silicon transfer board, and perform fan-out and chip interconnection through the interposer board, which can effectively improve the heat dissipation of the package. Reduce crosstalk between signals and other issues.
在先进的封装形式中， 常需要将多个芯片集成于一个封装体中， 如将微处 理器芯片和 flash程序存储芯片、 图形处理器 （GPU) 和随机存储器 （RAM) 集成到一个转接板基片中， 再通过转接板与基板互连形成封装体结构， 以实现 电子器件的某些特定功能。 这种多芯片封装形式提高了封装密度， 缩短了芯片 之间的引脚距离， 可显著提高相邻芯片间的带宽并降低了功耗。  In advanced packaging, it is often necessary to integrate multiple chips into one package, such as integrating a microprocessor chip and a flash program memory chip, a graphics processing unit (GPU), and random access memory (RAM) into an interposer board. In the substrate, the package structure is formed by interconnecting the substrate with the substrate to implement certain specific functions of the electronic device. This multi-chip package increases package density and reduces pin-to-pin distance between chips, significantly increasing bandwidth between adjacent chips and reducing power consumption.
在现有封装工艺中，将多个 IC芯片集成到转接板上的方法主要有两种。美 国专利 US 8313982B2、 US2012/0098123A1采用芯片 -芯片 （chip to chip) 方式 完成多个 IC芯片与转接板芯片的互连。该方法首先将减薄后的转接板切割成单 颗芯片并临时键合到承载晶圆上， 然后完成多个 IC芯片和转接板芯片的互连， 最后通过转接板芯片和承载晶圆的拆键合， 将承载晶圆移除。 但随着半导体工 艺的发展和转接板厚度的不断减小， 大尺寸的超薄转接板芯片如何进行拿持是 该方法中的一个工艺难题。  In the existing packaging process, there are mainly two methods for integrating a plurality of IC chips onto an interposer board. The US patents US 8313982B2 and US2012/0098123A1 use a chip-to-chip method to interconnect a plurality of IC chips and an interposer chip. The method firstly cuts the thinned adapter plate into a single chip and temporarily bonds it to the carrier wafer, and then completes the interconnection of the plurality of IC chips and the interposer chip, and finally passes through the interposer chip and the carrier crystal. The round debonding removes the carrier wafer. However, with the development of the semiconductor process and the continuous reduction of the thickness of the adapter plate, how to hold the large-sized ultra-thin adapter plate chip is a process problem in the method.
美国专利 US 7915080B2给出的另外一种封装方法是将所有待组装芯片以 芯片 -晶圆 （chip to wafer) 方式集成到转接板晶圆上， 完成芯片的封装后对整 体封装结构进行测试， 最后对转接板晶圆切片， 形成最终的封装结构。 在该制 作方法中， 封装结构的测试在完成所有芯片的封装后进行， 导致了较低的产品 良率； 同时， 实际的封装工艺中， 由于待封装的多个芯片其凸点节距、 安装精 度可能存在较大差异， 需用热压键合、 回流等不同的方式完成其与转接板的互 连。 而该方法提供的芯片与转接板晶圆互连方式单一， 其应用受到一定限制。 发明内容  Another encapsulation method given in US Pat. No. 7,915,048 B2 is to integrate all the chips to be assembled into an interposer wafer by chip-to-wafer, and test the overall package structure after the package of the chip is completed. Finally, the interposer wafer is sliced to form the final package structure. In the manufacturing method, the test of the package structure is performed after the packaging of all the chips is completed, resulting in a lower product yield; meanwhile, in the actual packaging process, the bump pitch and the mounting of the plurality of chips to be packaged Accuracy may vary greatly, and interconnection with the interposer board is required in different ways such as thermocompression bonding and reflow. The chip provided by the method has a single interconnection mode with the interposer wafer, and its application is limited. Summary of the invention
本发明的目的是克服现有技术中存在的不足， 提供一种多芯片系统级封装 结构的制作方法， 该方法可广泛应用于不同种类芯片的系统集成， 可有效降低 转接板芯片拿持的难度， 提高芯片封装的生产效率和产品良率。  The object of the present invention is to overcome the deficiencies in the prior art and provide a method for manufacturing a multi-chip system-level package structure, which can be widely applied to system integration of different types of chips, and can effectively reduce the holding of the adapter board chip. Difficulty, improve the production efficiency and product yield of the chip package.
按照本发明提供的技术方案， 所述多芯片系统级封装结构的制作方法包括 以下步骤：  According to the technical solution provided by the present invention, the method for fabricating the multi-chip system-level package structure includes the following steps:
1 ) 利用粘结剂将具有垂直硅通孔和凸点结构的转接板晶圆临时键合到 承载晶圆上； 2) 将大尺寸芯片倒装在转接板晶圆的第一表面并完成互连；1) temporarily bonding an interposer wafer having a vertical through silicon via and a bump structure to the carrier wafer using an adhesive; 2) flipping the large-sized chip on the first surface of the interposer wafer and completing the interconnection;
3 ) 完成转接板晶圆和承载晶圆的拆键合，移除承载晶圆，形成转接板封 装结构； 3) completing the detachment of the transfer plate wafer and the carrier wafer, removing the carrier wafer, and forming the adapter board package structure;
4) 对步骤 3形成的转接板封装结构进行第一次电性能测试；  4) Perform the first electrical performance test on the adapter board package structure formed in step 3;
5 ) 将带有单颗大尺寸芯片的转接板晶圆切割成单颗芯片，称为转接板芯 片， 转接板晶圆的第一表面成为转接板芯片的第一表面；  5) cutting the interposer wafer with a single large-size chip into a single chip, called an interposer chip, and the first surface of the interposer wafer becomes the first surface of the interposer chip;
6) 将小尺寸芯片或小尺寸芯片堆叠倒装到电性能良好的转接板芯片的 第一表面并完成互连；  6) flipping the small-sized chip or the small-sized chip stack onto the first surface of the electrically good adapter plate chip and completing the interconnection;
7) 对步骤 6形成的转接板芯片封装结构进行第二次电性能测试； 7) performing a second electrical performance test on the adapter chip package structure formed in step 6;
8) 将电性能良好的转接板芯片的第二表面与基板互连,形成最终的封装 结构。 8) Interconnecting the second surface of the electrically conductive adapter chip with the substrate to form the final package structure.
所述大尺寸芯片通过回流或热压键合的方式完成与转接板晶圆的电气互 连； 所述小尺寸芯片或小尺寸芯片堆叠采用回流或热压键合的方式完成与转接 板芯片的电气互连。  The large-sized chip is electrically interconnected with the interposer wafer by reflow or thermocompression bonding; the small-sized chip or small-sized chip stack is completed by reflow or thermocompression bonding and the interposer Electrical interconnection of the chip.
所述转接板晶圆带有 TSV垂直硅通孔金属化填充结构，填充材料为铜或钨 中的一种。  The interposer wafer has a TSV vertical through silicon via metallization filling structure, and the filling material is one of copper or tungsten.
所述大尺寸芯片面积大于小尺寸芯片。 所述大尺寸芯片可以为中央处理器 The large size chip area is larger than the small size chip. The large size chip can be a central processing unit
(CPU), 微处理器 （MPU)、 图形处理器 （GPU)、 数字信号处理器 （DSP)、 射频收发器。 所述小尺寸芯片可以为微机械系统 （MEMS )、 CMOS 图像传感 器、 存储器芯片。 (CPU), Microprocessor (MPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP), RF Transceiver. The small size chip may be a micro mechanical system (MEMS), a CMOS image sensor, or a memory chip.
本发明的优点是： 本发明用于实现尺寸相差较大的多芯片系统级封装， 首 先将大尺寸芯片倒装在转接板晶圆上形成电气互连， 然后将转接板晶圆切割成 单颗基片， 再完成小尺寸芯片与单颗转接板芯片的互连。 通过该方法实现多芯 片的系统级封装， 避免了超薄转接板不易拿持的缺点； 在大尺寸芯片与转接板 完成电气互连后即进行一次电性能测试， 可率先淘汰部分电连接失效的封装结 构， 提高了产品的良率； 大尺寸芯片和小尺寸芯片分别与转接板完成互连， 可 满足不同的互连工艺需求。  The advantages of the present invention are: The present invention is used to realize a multi-chip system-level package having a large difference in size. First, a large-sized chip is flip-chip mounted on an interposer wafer to form an electrical interconnection, and then the interposer wafer is cut into A single substrate is used to interconnect the small-sized chip with a single interposer chip. The system-level packaging of the multi-chip is realized by the method, and the disadvantage that the ultra-thin adapter board is difficult to handle is avoided; after the electrical connection between the large-sized chip and the adapter board is completed, the electrical performance test is performed, and the partial electrical connection can be eliminated first. The failed package structure improves the yield of the product; the large-size chip and the small-sized chip are respectively interconnected with the adapter board to meet different interconnection process requirements.
附图说明 DRAWINGS
图 1是带有 TSV和凸点结构的转接板晶圆剖面图。  Figure 1 is a cross-sectional view of an interposer wafer with TSV and bump structures.
图 2是完成转接板晶圆和承载晶圆临时键合的示意图。  Figure 2 is a schematic diagram of the temporary bonding of the interposer wafer and the carrier wafer.
图 3是将大尺寸芯片倒装在转接板晶圆上的示意图。  Figure 3 is a schematic illustration of flipping a large size chip onto an interposer wafer.
图 4是完成转接板晶圆和承载晶圆拆键合后的示意图。  FIG. 4 is a schematic view of the completed adapter wafer and the carrier wafer being detached.
图 5是将小尺寸芯片倒装到转接板芯片上的示意图。  Figure 5 is a schematic illustration of flipping a small size chip onto an interposer chip.
图 6是将转接板芯片与基板互连的示意图。  Figure 6 is a schematic diagram of interconnecting an interposer chip with a substrate.
具体实施方式 detailed description
下面结合附图和实施例对本发明作进一步说明。  The invention will now be further described with reference to the accompanying drawings and embodiments.
本发明涉及的封装结构包括：  The package structure involved in the present invention includes:
具有 TSV硅通孔 2和凸点 3结构的转接板晶圆 1， 如图 1所示， 转接板晶 圆 1下方为 BGA(Ball Grid Array)焊点 4; TSV通孔金属化填充结构的填充材料 可以为铜或钨中的一种； Adapter plate wafer 1 having TSV through silicon via 2 and bump 3 structure, as shown in FIG. 1 , BGA (Ball Grid Array) solder joint 4 under the transfer plate wafer 1; TSV via metallization filling structure Filling material Can be one of copper or tungsten;
至少两类待组装的芯片， 其中一类为大尺寸芯片 7， 另一类为小尺寸芯片 或小尺寸芯片堆叠 8， 如图 5所示；  At least two types of chips to be assembled, one of which is a large-sized chip 7, and the other is a small-sized chip or a small-sized chip stack 8, as shown in FIG. 5;
大尺寸芯片 Ί倒装到转接板晶圆 1上；  The large size chip is flipped onto the wafer 1 of the interposer;
转接板晶圆 1切片成转接板芯片后， 小尺寸芯片或小尺寸芯片堆叠 8安装 到己完成一次封装的转接板芯片上。  After the interposer wafer 1 is sliced into an interposer chip, the small-sized chip or small-sized chip stack 8 is mounted on the interposer chip that has completed the package once.
本发明的多芯片系统级封装结构的制作方法， 其实施流程如下：  The implementation method of the multi-chip system-level package structure of the present invention is as follows:
1、如图 2所示，利用粘结剂 5将具有垂直硅通孔 2和凸点 3结构的转接板 晶圆 1临时键合到承载晶圆 6上；  1. As shown in FIG. 2, the interposer wafer 1 having the vertical through silicon via 2 and the bump 3 structure is temporarily bonded to the carrier wafer 6 by using the adhesive 5;
2、如图 3所示，将大尺寸芯片 7倒装在转接板晶圆 1的第一表面的相应位 置上， 以回流或热压键合方式完成两者的电气互连；  2. As shown in FIG. 3, the large-sized chip 7 is flip-chip mounted on the first surface of the first surface of the interposer wafer 1, and the electrical interconnection between the two is completed by reflow or thermocompression bonding;
3、如图 4所示， 完成转接板晶圆 1和承载晶圆 6的拆键合， 移除承载晶圆 6， 形成转接板封装结构；  3. As shown in FIG. 4, the detachment bonding between the carrier wafer 1 and the carrier wafer 6 is completed, and the carrier wafer 6 is removed to form an adapter board package structure;
4、 对步骤 3形成的转接板封装结构进行第一次电性能测试；  4. Perform the first electrical performance test on the adapter board package structure formed in step 3.
5、将带有单颗大尺寸芯片 7的转接板晶圆 1切割成单颗芯片，称为转接板 芯片， 转接板晶圆 1的第一表面也就是转接板芯片的第一表面；  5. Cutting the interposer wafer 1 with a single large size chip 7 into a single chip, called an interposer chip, and the first surface of the interposer wafer 1 is the first of the interposer chips. Surface
6、如图 5所示，将小尺寸芯片或小尺寸芯片堆叠 8倒装到电性能良好的转 接板芯片的第一表面的相应位置上， 回流（或热压键合）完成两者的电气互连;  6. As shown in FIG. 5, the small-sized chip or the small-sized chip stack 8 is flipped onto the first surface of the first surface of the electrically good adapter chip, and the reflow (or thermocompression bonding) is completed. Electrical interconnection
7、 对步骤 6形成的转接板芯片封装结构进行第二次电性能测试；  7. Perform a second electrical performance test on the adapter chip package structure formed in step 6;
8、如图 6所示， 将电性能良好的转接板芯片的第二表面放置在基板上， 回 流完成转接板和基板 9的互连， 形成最终的封装结构。  8. As shown in FIG. 6, the second surface of the adapter chip having good electrical properties is placed on the substrate, and the interconnection between the interposer and the substrate 9 is completed by return flow to form a final package structure.
本发明所述的大尺寸芯片 7面积大于小尺寸芯片 8。 如： 大尺寸芯片 7可 以为中央处理器 （CPU)、 微处理器 （MPU)、 图形处理器 （GPU)、 数字信号 处理器（DSP)、射频收发器。 小尺寸芯片可以为微机械系统（MEMS)、 CMOS 图像传感器、 存储器芯片。  The large-sized chip 7 of the present invention has a larger area than the small-sized chip 8. For example, the large size chip 7 can be a central processing unit (CPU), a microprocessor (MPU), a graphics processing unit (GPU), a digital signal processor (DSP), and a radio frequency transceiver. The small size chip can be a micro mechanical system (MEMS), a CMOS image sensor, or a memory chip.
本发明首先将大尺寸芯片 7与转接板晶圆 1完成互连， 小尺寸芯片或小尺 寸芯片堆叠 8与切割后的单颗转接板芯片互连。 大尺寸芯片 7与转接板晶圆 1 完成互连后， 对转接板芯片封装结构进行第一次电性能测试； 小尺寸芯片或小 尺寸芯片堆叠 8与转接板芯片互连后， 对封装结构进行第二次电性能测试。 该 制作方法避免了超薄的硅转接板不易拿持的问题， 并显著提高了封装效率和产 品的良率， 降低了生产成本。  The present invention first interconnects the large size chip 7 with the interposer wafer 1, and the small size chip or small size chip stack 8 is interconnected with the diced single interposer chip. After the large-size chip 7 and the interposer wafer 1 are interconnected, the first electrical performance test is performed on the interposer chip package structure; after the small-size chip or the small-size chip stack 8 is interconnected with the interposer chip, The package structure is tested for the second electrical performance. This manufacturing method avoids the problem that the ultra-thin silicon adapter plate is difficult to handle, and significantly improves the packaging efficiency and the yield of the product, and reduces the production cost.

Claims

权 利 要 求 书 claims
1、 多芯片系统级封装结构的制作方法， 其特征是， 包括以下步骤： 1. A method for manufacturing a multi-chip system-level packaging structure, which is characterized by including the following steps:
1 ) 利用粘结剂将具有垂直硅通孔（2)和凸点（3 )结构的转接板晶圆（1 ) 临时键合到承载晶圆 （6) 上； 1) Temporarily bond the adapter plate wafer (1) with the vertical through silicon via (2) and bump (3) structure to the carrier wafer (6) using an adhesive;
2) 将大尺寸芯片 （7) 倒装在转接板晶圆 （1 ) 的第一表面并完成互连； 2) Flip the large-size chip (7) onto the first surface of the adapter board wafer (1) and complete the interconnection;
3 ) 完成转接板晶圆（1 )和承载晶圆（6) 的拆键合， 移除承载晶圆（6)， 形成转接板封装结构； 3) Complete the debonding of the adapter plate wafer (1) and the carrier wafer (6), remove the carrier wafer (6), and form an adapter plate packaging structure;
4) 对步骤 3形成的转接板封装结构进行第一次电性能测试； 4) Conduct the first electrical performance test on the adapter board packaging structure formed in step 3;
5) 将带有单颗大尺寸芯片 （7) 的转接板晶圆 （1 ) 切割成单颗芯片， 称 为转接板芯片， 转接板晶圆 （1 ) 的第一表面成为转接板芯片的第一表面； 5) Cut the adapter board wafer (1) with a single large-size chip (7) into a single chip, called an adapter board chip, and the first surface of the adapter board wafer (1) becomes the adapter the first surface of the board chip;
6) 将小尺寸芯片或小尺寸芯片堆叠 （8) 倒装到电性能良好的转接板芯 片的第一表面并完成互连； 6) Flip the small size chip or small size chip stack (8) onto the first surface of the adapter board chip with good electrical properties and complete the interconnection;
7) 对步骤 6形成的转接板芯片封装结构进行第二次电性能测试； 7) Conduct a second electrical performance test on the adapter board chip packaging structure formed in step 6;
8) 将电性能良好的转接板芯片的第二表面与基板 （9) 互连， 形成最终 的封装结构。 8) Interconnect the second surface of the adapter board chip with good electrical properties and the substrate (9) to form the final packaging structure.
2、 如权利要求 1所述多芯片系统级封装结构的制作方法， 其特征是， 所述 大尺寸芯片 （7) 通过回流或热压键合的方式完成与转接板晶圆 （1 ) 的电气互 连； 所述小尺寸芯片或小尺寸芯片堆叠 （8) 采用回流或热压键合的方式完成与 转接板芯片的电气互连。 2. The method for manufacturing a multi-chip system-level packaging structure according to claim 1, wherein the large-size chip (7) is bonded to the adapter plate wafer (1) through reflow or thermocompression bonding. Electrical interconnection; The small-size chip or small-size chip stack (8) uses reflow or thermal pressure bonding to complete the electrical interconnection with the adapter board chip.
3、 如权利要求 1所述多芯片系统级封装结构的制作方法， 其特征是， 所述 转接板晶圆（1 )带有垂直硅通孔金属化填充结构，填充材料为铜或钨中的一种。 3. The method for manufacturing a multi-chip system-level package structure according to claim 1, wherein the adapter plate wafer (1) has a vertical through silicon via metallized filling structure, and the filling material is copper or tungsten. kind of.
4、 如权利要求 1所述多芯片系统级封装结构的制作方法， 其特征是， 所述 大尺寸芯片为中央处理器、 微处理器、 图形处理器、 数字信号处理器或射频收 发器。 4. The method for manufacturing a multi-chip system-in-package structure according to claim 1, wherein the large-size chip is a central processing unit, a microprocessor, a graphics processor, a digital signal processor or a radio frequency transceiver.
5、 如权利要求 1所述多芯片系统级封装结构的制作方法， 其特征是， 所述 小尺寸芯片为微机械系统 MEMS、 CMOS图像传感器或存储器芯片。 5. The method for manufacturing a multi-chip system-in-package structure according to claim 1, wherein the small-size chip is a micro-mechanical system MEMS, a CMOS image sensor or a memory chip.
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