CN104347494A - Back surface interconnection method for through silicon via metal posts - Google Patents
Back surface interconnection method for through silicon via metal posts Download PDFInfo
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- CN104347494A CN104347494A CN201410459812.2A CN201410459812A CN104347494A CN 104347494 A CN104347494 A CN 104347494A CN 201410459812 A CN201410459812 A CN 201410459812A CN 104347494 A CN104347494 A CN 104347494A
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- via metal
- metal post
- silicon via
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a back surface interconnection method for through silicon via metal posts. The method comprises the following steps of forming lower salient point metal layers on the surfaces of salient points which are the through silicon via metal posts extending to the back surface of a silicon substrate, wherein the silicon substrate comprises at least one through silicon via metal post; forming a solder ball on the lower salient point metal layers corresponding to a fixed number of adjacent salient points to realize the back surface interconnection of the corresponding through silicon via metal posts in a way that the solder ball surrounds the fixed number of lower salient point metal layers. According to the scheme, a process is simplified, and production and process risks are lowered.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of silicon via metal post back side interconnected method.
Background technology
At silicon through hole (through silicon via, in back side projection (bump) technique of TSV) technique, usually make the technique of traditional bump, carry out the processing of back side bump, by disk through physical vapour deposition (PVD) (Physical Vapor Deposition, PVD), photo (comprising gluing, exposure, development etc.), the process procedures such as plating, stripping, corrosion, its complex process, the probability gone wrong is larger.
Summary of the invention
The object of the present invention is to provide a kind of silicon via metal post back side interconnected method.
The invention provides a kind of silicon via metal post back side interconnected method, comprising:
To extend to the silicon via metal post at the silicon substrate back side as salient point, form ubm layer at described bump surface, described silicon substrate comprises at least one silicon via metal post; The described ubm layer that the described salient point of adjacent fixed number is corresponding forms tin ball, the described ubm layer of fixed number described in described tin ball bag, interconnected to realize the corresponding described silicon via metal post back side.
The silicon via metal post back side provided by the invention interconnected method, on silicon via metal post body, to extend to the silicon via metal post at the silicon substrate back side as salient point, forms the ubm layer that can weld at this bump surface; And then use ubm layer corresponding to multiple salient point on it, to form tin ball as base.Simplify technique, reduction can be produced and process risk.
Accompanying drawing explanation
Fig. 1 is the flow chart of a silicon via metal post back side interconnected method provided by the invention embodiment;
Fig. 2 is the flow chart of the silicon via metal post back side provided by the invention another embodiment of interconnected method;
Fig. 3 is silicon substrate back side thinning provided by the invention structural representation before treatment;
Fig. 4 is the structural representation after the bonded support wafer of silicon substrate front provided by the invention;
Fig. 5 is the structural representation after the thinning process of the silicon substrate back side provided by the invention;
Fig. 6 is the structural representation after the silicon substrate back side provided by the invention forms separator;
Fig. 7 is the structural representation after silicon via metal post thinning process provided by the invention;
Fig. 8 A is the structural representation after a kind of silicon substrate back side provided by the invention forms ubm layer;
Fig. 8 B is the structural representation after the another kind of silicon substrate back side provided by the invention forms ubm layer;
Fig. 9 provided by the inventionly forms the structural representation after tin ball on ubm layer;
Figure 10 is the structural representation after removal carrier wafer provided by the invention.
Embodiment
Fig. 1 is the flow chart of a silicon via metal post back side interconnected method provided by the invention embodiment, and as shown in Figure 1, the method specifically comprises:
S101, to extend to the silicon via metal post at the silicon substrate back side as salient point, forms ubm layer at bump surface, this silicon substrate comprises at least one silicon via metal post;
Adopt existing manufacture technics silicon via metal post, normally at least one silicon via metal post is arranged in silicon substrate, and one end of silicon via metal post is extended to the silicon substrate back side expose, for follow-up welding.The present embodiment is after completing silicon piercing process and forming silicon via metal post, and how what provide a kind ofly will need interconnected silicon via metal post to carry out interconnected method at the silicon substrate back side further.Concrete, the present embodiment is to extend to the silicon via metal post at the silicon substrate back side as salient point; Then ubm layer is formed at this bump surface.When forming this ubm layer, the mode of chemical plating can be adopted, namely first form Seed Layer, then go out ubm layer by mask plating.
S102, the ubm layer that the salient point of adjacent fixed number is corresponding forms tin ball, the ubm layer of fixed number described in this tin ball bag, interconnected to realize the silicon via metal post back side;
Choose the salient point treating interconnected fixed number at the silicon substrate back side, these salient points can be set to adjacent position relation when designing the position of silicon via metal post usually, complete interconnection technology so that follow-up.The ubm layer that the salient point be selected is corresponding forms tin ball, the above-mentioned ubm layer treating interconnected all fixed number of this Xi Qiuhuanbao, interconnected to make to realize between the ubm layer of these fixed number to be communicated with.Concrete, the mode forming above-mentioned tin ball can adopt tin ball reflux technique to realize the connection of itself and ubm layer.
The silicon via metal post back side provided by the invention interconnected method, to extend to the silicon via metal post at the silicon substrate back side as salient point, forms ubm layer at bump surface, described silicon substrate comprises at least one silicon via metal post; The ubm layer that the salient point of adjacent fixed number is corresponding forms tin ball, the ubm layer of fixed number described in this tin ball bag, interconnected at the silicon substrate back side to realize corresponding silicon via metal post.This solution simplifies technique, reduction can be produced and process risk.
Fig. 2 is the flow chart of the silicon via metal post back side provided by the invention another embodiment of interconnected method, and be a kind of specific implementation of the via metal post of silicon shown in Fig. 1 back side interconnected method, as shown in Figure 2, the method specifically comprises:
S201, carries out thinning process to the silicon substrate back side being provided with at least one silicon via metal post, to make silicon via metal post expose from the silicon substrate back side, and with the silicon substrate back side at a distance of the first predeterminable range;
Fig. 3 is silicon substrate back side thinning provided by the invention structural representation before treatment; As shown in Figure 3; in the prototype structure of silicon substrate 3 completing silicon piercing process formation silicon via metal post 31; silicon via metal post 31 is arranged on silicon substrate 3 inside; and distance silicon substrate 3 back side there is certain distance; silicon substrate 3 front is also provided with at least one top layer projection 32 usually, and what can be used between multilager base plate is interconnected.
Optionally, due to usually in silicon via process process, silicon substrate has been thinned to 100 microns, is not easy to technological operation.Therefore, as shown in Figure 4, the present embodiment to improve the integral thickness of silicon substrate as additional carrying performing before step 201 carrier wafer 34 that first can have fixed thickness in silicon substrate 3 front by bonded layer 33 bonding one deck, to improve the operability of perhaps technique.In the present embodiment subsequent method step, also with reference to Fig. 3, silicon via metal post back side interconnected method is described.
As shown in Figure 5, interconnected for realizing the silicon via metal post back side, first to carry out thinning process to silicon substrate 3 shown in Fig. 4, comprise as the method such as cmp, etching makes silicon via metal post 31 expose.Concrete, in the present embodiment, silicon substrate 3 back side after silicon via metal post 31 and thinning process is at a distance of the first predeterminable range.
S202, form separator at the silicon substrate back side of exposing silicon via metal post, the thickness of this separator is less than the first predeterminable range;
As shown in Figure 6, for the silicon substrate back side provided by the invention forms the structural representation after separator.Wherein, this separator 35 is dielectric material, as SiN, oxide etc., by spin-coating method, directly prints, or chemical vapour deposition (CVD) (Chemical vapor deposition, CVD)) etc. method formed.The thickness of this separator 35 is less than above-mentioned first predeterminable range, and namely silicon via metal post 31 exposes the surperficial segment distance of separator 35.
S203, carries out thinning process to the silicon via metal post being exposed to insulation surface, to make silicon via metal post surface and insulation surface at grade;
Fig. 7 is the structural representation after silicon via metal post thinning process provided by the invention; Wherein, carrying out the processing step of thinning process to silicon via metal post 31 in this step can see the thinning processing step in step 201.
S204, to extend to the silicon via metal post at the silicon substrate back side as salient point, forms ubm layer at this bump surface; The concrete implementation of this step can see the corresponding contents of step 101.
Fig. 8 A and Fig. 8 B is respectively the structural representation after formation ubm layer 36 in two kinds of silicon substrate 3 back sides provided by the invention.Concrete, as shown in Figure 8 A, form ubm layer 36 respectively at each bump surface, and the ubm layer 36 interval setting that each salient point is corresponding, be separated from each other.Or, as shown in Figure 8 B, form ubm layer 36 respectively at each bump surface, and be communicated with between ubm layer 36 corresponding to each salient point, special, be such as the Rotating fields of a unitary closed shown in 8B.
Concrete, this ubm layer 36 can be single metal also can be composite material; This gives several modes forming this ubm layer 36 at bump surface, comprising:
Chemical plating mode is used to form nickel dam and tin layers successively at bump surface, to form ubm layer 36;
Use chemical plating mode to form nickel dam at bump surface, then the bump surface of the nickel dam of formation is impregnated in soldering tin, to form ubm layer 36;
By bump surface direct impregnation in soldering tin, to form ubm layer 36.
S205, the ubm layer that the salient point of adjacent fixed number is corresponding forms tin ball, and this tin ball wraps the ubm layer stating fixed number, interconnected to realize the corresponding silicon via metal post back side; The concrete implementation of this step can see the corresponding contents of step 102.
Fig. 9 provided by the inventionly forms the structural representation after tin ball on ubm layer.
Further, as shown in Figure 10, if silicon substrate 3 front bonding carrier wafer 34 before step 201, after then forming tin ball 37 on ubm layer 36, also the carrier wafer 34 of silicon substrate 31 front by bonded layer 33 bonding to be got rid of, method is that the binding material adaptability that specifically can adopt according to bonded layer 33 adopts the method such as thermal decomposition or chemical breakdown to remove bonded layer 33, and then removes carrier wafer 34.
The silicon via metal post back side provided by the invention bump manufacturing method, carries out thinning process to the silicon substrate back side being provided with at least one silicon via metal post, to make silicon via metal post expose from the silicon substrate back side, and with the silicon substrate back side at a distance of the first predeterminable range; Form separator at the silicon substrate back side of exposing silicon via metal post, the thickness of this separator is less than the first predeterminable range; Thinning process is carried out to the silicon via metal post being exposed to insulation surface, to make silicon via metal post surface and insulation surface at grade; To extend to the silicon via metal post at the silicon substrate back side as salient point, form ubm layer at this bump surface; The ubm layer that the salient point of adjacent fixed number is corresponding forms tin ball, and this tin ball wraps the ubm layer stating fixed number, interconnected to realize the corresponding silicon via metal post back side.This solution simplifies technique, reduce production and process risk.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (7)
1. a silicon via metal post back side interconnected method, is characterized in that, comprising:
To extend to the silicon via metal post at the silicon substrate back side as salient point, form ubm layer at described bump surface, described silicon substrate comprises at least one silicon via metal post;
The described ubm layer that the described salient point of adjacent fixed number is corresponding forms tin ball, the described ubm layer of fixed number described in described tin ball bag, interconnected to realize the corresponding described silicon via metal post back side.
2. method according to claim 1, is characterized in that, described using the silicon via metal post extending to the silicon substrate back side as salient point, before described bump surface forms ubm layer, also comprises:
Thinning process is carried out to the silicon substrate back side being provided with at least one silicon via metal post, to make described silicon via metal post expose from the described silicon substrate back side, and with the described silicon substrate back side at a distance of the first predeterminable range;
Form separator at the described silicon substrate back side of exposing described silicon via metal post, the thickness of described separator is less than described first predeterminable range;
Thinning process is carried out to the described silicon via metal post being exposed to described insulation surface, to make described silicon via metal post surface and described insulation surface at grade.
3. method according to claim 2, is characterized in that, the described silicon substrate back side to being provided with at least one silicon via metal post also comprises before carrying out thinning process:
There is at described silicon substrate front bonding one deck the carrier wafer of fixed thickness.
4. method according to claim 3, is characterized in that, after the described described ubm layer corresponding at the described salient point of adjacent fixed number forms tin ball, also comprises:
The described carrier wafer of para-linkage carries out degumming process, to remove described carrier wafer.
5. method according to claim 1, is characterized in that, described using the silicon via metal post extending to the silicon substrate back side as salient point, forms ubm layer, comprising at described bump surface:
Ubm layer is formed respectively at each described bump surface, and the described ubm layer interval setting that each described salient point is corresponding.
6. method according to claim 1, is characterized in that, described using the silicon via metal post extending to the silicon substrate back side as salient point, forms ubm layer, comprising at described bump surface:
Form ubm layer respectively at each described bump surface, and be communicated with between described ubm layer corresponding to each described salient point.
7. method according to claim 1, is characterized in that, the described described ubm layer corresponding at the described salient point of adjacent fixed number forms tin ball, comprising:
Solder reflow process is adopted to form described tin ball on described ubm layer surface.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410459812.2A CN104347494A (en) | 2014-09-10 | 2014-09-10 | Back surface interconnection method for through silicon via metal posts |
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| CN201410459812.2A CN104347494A (en) | 2014-09-10 | 2014-09-10 | Back surface interconnection method for through silicon via metal posts |
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| CN104347494A true CN104347494A (en) | 2015-02-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109994425A (en) * | 2019-04-04 | 2019-07-09 | 上海迈铸半导体科技有限公司 | Fill preparation method, filling substrate and the micropore interconnection structure preparation method of substrate |
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| CN103165479A (en) * | 2013-03-04 | 2013-06-19 | 江苏物联网研究发展中心 | Manufacture method of multi-chip and system-level packaging structure |
| CN103219303A (en) * | 2013-03-28 | 2013-07-24 | 江苏物联网研究发展中心 | Packaging structure and method of TSV (Through Silicon Vias) back leakage hole |
| KR20140084517A (en) * | 2012-12-27 | 2014-07-07 | 하나 마이크론(주) | Interposer inculding buffer cavity, stack type interposer and method for manufacturing the same |
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2014
- 2014-09-10 CN CN201410459812.2A patent/CN104347494A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102299143A (en) * | 2010-06-25 | 2011-12-28 | 台湾积体电路制造股份有限公司 | Semiconductor element |
| KR20140084517A (en) * | 2012-12-27 | 2014-07-07 | 하나 마이크론(주) | Interposer inculding buffer cavity, stack type interposer and method for manufacturing the same |
| CN103165479A (en) * | 2013-03-04 | 2013-06-19 | 江苏物联网研究发展中心 | Manufacture method of multi-chip and system-level packaging structure |
| CN103219303A (en) * | 2013-03-28 | 2013-07-24 | 江苏物联网研究发展中心 | Packaging structure and method of TSV (Through Silicon Vias) back leakage hole |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109994425A (en) * | 2019-04-04 | 2019-07-09 | 上海迈铸半导体科技有限公司 | Fill preparation method, filling substrate and the micropore interconnection structure preparation method of substrate |
| CN109994425B (en) * | 2019-04-04 | 2021-07-30 | 上海迈铸半导体科技有限公司 | Preparation method of filling substrate, filling substrate and preparation method of micropore interconnection structure |
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Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
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Application publication date: 20150211 |
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