CN104681452A - Method for manufacturing wafer level package - Google Patents
Method for manufacturing wafer level package Download PDFInfo
- Publication number
- CN104681452A CN104681452A CN201410842488.2A CN201410842488A CN104681452A CN 104681452 A CN104681452 A CN 104681452A CN 201410842488 A CN201410842488 A CN 201410842488A CN 104681452 A CN104681452 A CN 104681452A
- Authority
- CN
- China
- Prior art keywords
- chip
- photoresist
- layer
- connecting column
- power connecting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
The invention relates to a method for manufacturing a wafer level package. The method comprises the following steps of forming a first photoresist on a first chip, and forming a plurality of opening parts in the first photoresist to expose the function surface of the first chip; forming convex point lower metal layers on the function surface exposed from the opening parts, and removing the first photoresist; connecting function convex points of a second chip with the convex point lower metal layer; forming a filling layer between the first chip and the second chip; forming power connection posts on the first chip, wherein the top surface of the power connection post is higher than the top surface of the second chip; planting a welding ball on the top surface of each power connection post. The first chip and the second chip are arranged face to face, the power connection posts are formed on the first chip, and a packaging structure is formed. In the subsequent inversion process, the packaging structure can be inversed by using height difference between the power connection posts on the first chip and the second chip, the packaging structure is not damaged, the second chip is not damaged during inversion, and the risk in a processing process is reduced.
Description
Technical field
The present invention relates to semiconductor making method, particularly relate to a kind of manufacture method of wafer-level packaging.
Background technology
Along with chip functions gets more and more, the requirement for encapsulation is also more and more higher, and upside-down mounting, lamination become trend.While upside-down mounting, lamination, also require that package thickness is as far as possible thin, as far as possible thin when so requiring chip package to a certain extent, thus cause the risk of the course of processing.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.
The invention provides a kind of manufacture method of wafer-level packaging, the first chip is formed the first photoresist, described first photoresist forms multiple first peristome, expose the functional surfaces of described first chip; Form ubm layer at the functional surfaces exposed from described multiple first peristome, then remove described first photoresist; The function salient point of described second chip is connected with described ubm layer; Packed layer is formed between described first chip and described second chip; Described first chip forms power connecting column, and the end face of described power connecting column is higher than described second chip end face; Soldered ball is planted at described power connecting column end face.
Compared to prior art, beneficial effect of the present invention at least comprises: the first chip and the second chip are arranged face-to-face, power connecting column is formed again on the first chip, the encapsulating structure formed thus is in follow-up reverse installation process, make use of the difference in height that power connecting column on the first chip and the second chip are formed, just by encapsulating structure upside-down mounting, and can not destroy encapsulating structure, namely can not damage the second chip during upside-down mounting, reduce the risk in the course of processing.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the flow chart of the manufacture method of wafer-level packaging of the present invention;
Fig. 2-10 is schematic diagram step by step in the process of the manufacture method adopting wafer-level packaging of the present invention;
Figure 11 is a kind of schematic diagram of the wafer level packaging structure adopting the manufacture method of wafer-level packaging of the present invention to manufacture;
Figure 12 is the another kind of schematic diagram of the wafer level packaging structure adopting the manufacture method of wafer-level packaging of the present invention to manufacture.
Reference numeral:
1-first chip; 2-second chip; 11-ubm layer; 21-function salient point; 3-power connecting column; 4-soldered ball; 5-packed layer; 6-first photoresist; 61-first peristome; 7-second photoresist; 71-second peristome.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.The element described in an accompanying drawing of the present invention or a kind of execution mode and feature can combine with the element shown in one or more other accompanying drawing or execution mode and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not paying creative work, all belongs to the scope of protection of the invention.
In the following embodiment of the present invention, the sequence number of embodiment and/or sequencing are only convenient to describe, and do not represent the quality of embodiment.The description of each embodiment is all emphasized particularly on different fields, in certain embodiment, there is no the part described in detail, can see the associated description of other embodiments.
The present invention discloses a kind of manufacture method of wafer-level packaging, comprise step 10, first chip 1 is formed the first photoresist 6 (as shown in Figure 2), described first photoresist 6 is formed multiple first peristome 61 (see Fig. 3), exposes the functional surfaces of described first chip 1; Step 20, forms ubm layer 11 (as Fig. 4) at the functional surfaces exposed from described multiple first peristome 61, then removes described first photoresist 6 (see Fig. 5); Step 30, is connected the function salient point 21 of described second chip 2 (as shown in Figure 6) with described ubm layer 11; Step 40, see Fig. 7, forms packed layer 5 between described first chip 1 and described second chip 2; Step 50, described first chip 1 forms power connecting column 3, and the end face of described power connecting column 3 is higher than described second chip 2 end face (as Figure 11 and 12); Step 60, continues see Figure 11 and 12, plants soldered ball 4 at described power connecting column 3 end face.
How the power connecting column 3 that the following describes in above-mentioned steps 50 is formed, step 51 can be comprised, form packed layer 5 (as Fig. 7) between described first chip 1 and described second chip 2 after, be made up of described first chip 1, second chip 2 and described packed layer 5 integrally-built above, form vapor phase deposition layer (not shown), described vapor phase deposition layer is formed the second photoresist 7 (as shown in Figure 8), and on described second photoresist 7, form multiple second peristome 71 (as shown in Figure 9), expose described vapor phase deposition layer; Step 52, as shown in Figure 10, the described vapor phase deposition layer exposed forms power connecting column 3; Step 53, removes described second photoresist 7 and exposes described vapor phase deposition layer.
Above-mentioned packed layer 5 is optionally resin material.
In the optional execution mode of one, in above-mentioned steps 51, vapor phase deposition layer can not be used, in step 53, certainly also just not need the operation of removing vapor phase deposition layer.
In the optional execution mode of one, with the upper surface of described first chip 1 for datum level, the end face forming described power connecting column 3 is 80-120 micron to the distance of this datum level; Described second chip 2 end face is less than 60 microns to the distance of described datum level.Obviously this is a kind of embodiment of power connecting column end face higher than the second chip end face.
Above-mentioned power connecting column 3 is optionally copper post, and this copper post can adopt the mode of plating to be formed.Connecing soldered ball 4 is optionally tin ball.
In the optional execution mode of one, before the first chip 1 is formed the first photoresist 6, first on described first chip 1, form protective layer, surface forms described first photoresist 6 (not shown) on the protection layer afterwards; Described first peristome 61 exposes the protective layer on described functional surfaces; Ubm layer 11 is formed at the upper surface of the protective layer exposed from described peristome; Here should know, since ubm layer 11 has been formed in the upper surface of protective layer, so this protective surface should conducting ubm layer 11 and the first chip 1.In protective layer upper surface, the part being formed with described ubm layer 11 is Part I, and what do not form described ubm layer 11 is Part II, after removing described photoresist, then removes described Part II.
As shown in figure 12, above-mentioned power connecting column 3 (copper post) has multiple, and multiple described power connecting column 3, around described second chip 2, is formed on the first chip 1.
Before formation soldered ball 4, can first form one deck tin layers at the end face of power connecting column 3, plant ball to facilitate
Although last it is noted that described the present invention and advantage thereof in detail above, be to be understood that and can carry out various change when not exceeding the spirit and scope of the present invention limited by appended claim, substituting and converting.And scope of the present invention is not limited only to the specific embodiment of process, equipment, means, method and step described by specification.One of ordinary skilled in the art will readily appreciate that from disclosure of the present invention, can use perform the function substantially identical with corresponding embodiment described herein or obtain and its substantially identical result, existing and that will be developed in the future process, equipment, means, method or step according to the present invention.Therefore, appended claim is intended to comprise such process, equipment, means, method or step in their scope.
Claims (8)
1. a manufacture method for wafer-level packaging, is characterized in that,
First chip is formed the first photoresist, described first photoresist forms multiple first peristome, expose the functional surfaces of described first chip;
Form ubm layer at the functional surfaces exposed from described multiple first peristome, then remove described first photoresist;
The function salient point of described second chip is connected with described ubm layer;
Packed layer is formed between described first chip and described second chip;
Described first chip forms power connecting column, and the end face of described power connecting column is higher than described second chip end face;
Soldered ball is planted at described power connecting column end face.
2. method according to claim 1, is characterized in that,
The method forming described power connecting column is:
Form packed layer between described first chip and described second chip after, be made up of described first chip, the second chip and described packed layer integrally-built above, form vapor phase deposition layer, described vapor phase deposition layer forms the second photoresist, and multiple second peristome is formed on described second photoresist, expose described vapor phase deposition layer;
The described vapor phase deposition layer exposed forms power connecting column;
Remove described second photoresist and expose described vapor phase deposition layer.
3. method according to claim 1, is characterized in that,
With the upper surface of described first chip for datum level, the end face forming described power connecting column is 80-120 micron to the distance of described datum level;
Described second chip end face is less than 60 microns to the distance of described datum level.
4. method according to claim 1, is characterized in that,
Before first chip is formed the first photoresist, first on described first chip, form protective layer, surface forms described first photoresist on the protection layer afterwards;
Described first peristome exposes the protective layer on described functional surfaces;
Described ubm layer is formed at the upper surface of the protective layer exposed from described peristome;
In described protective layer upper surface, the part being formed with described ubm layer is Part I, and what do not form described ubm layer is Part II, after removing described photoresist, then removes described Part II.
5. the method according to any one of claim 1-4, is characterized in that,
Described power connecting column is copper post.
6. the method according to any one of claim 1-4, is characterized in that,
The described soldered ball that connects is tin ball.
7. the method according to any one of claim 1-4, is characterized in that,
Described power connecting column has multiple, and multiple described power connecting column, around described second chip, is formed on described first chip.
8. the method according to any one of claim 1-4, is characterized in that,
Described packed layer is resin bed.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410842488.2A CN104681452A (en) | 2014-12-30 | 2014-12-30 | Method for manufacturing wafer level package |
| PCT/CN2015/095422 WO2016107336A1 (en) | 2014-12-30 | 2015-11-24 | Method for manufacturing wafer level package |
| US15/326,401 US10008478B2 (en) | 2014-12-30 | 2015-11-24 | Fabricating method for wafer-level packaging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410842488.2A CN104681452A (en) | 2014-12-30 | 2014-12-30 | Method for manufacturing wafer level package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104681452A true CN104681452A (en) | 2015-06-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410842488.2A Pending CN104681452A (en) | 2014-12-30 | 2014-12-30 | Method for manufacturing wafer level package |
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| CN (1) | CN104681452A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016107336A1 (en) * | 2014-12-30 | 2016-07-07 | 南通富士通微电子股份有限公司 | Method for manufacturing wafer level package |
| CN108461409A (en) * | 2018-03-29 | 2018-08-28 | 中国电子科技集团公司第四十三研究所 | A kind of CCGA devices plant column device and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1929092A (en) * | 2005-09-06 | 2007-03-14 | 日月光半导体制造股份有限公司 | Projection producing process and its structure |
| CN101266967A (en) * | 2008-05-04 | 2008-09-17 | 日月光半导体制造股份有限公司 | Stacking chip encapsulation structure and its making method |
| CN102446780A (en) * | 2011-12-19 | 2012-05-09 | 南通富士通微电子股份有限公司 | Wafer-level packaging method |
| CN103762187A (en) * | 2014-01-16 | 2014-04-30 | 苏州晶方半导体科技股份有限公司 | Chip packaging method and structure |
-
2014
- 2014-12-30 CN CN201410842488.2A patent/CN104681452A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1929092A (en) * | 2005-09-06 | 2007-03-14 | 日月光半导体制造股份有限公司 | Projection producing process and its structure |
| CN101266967A (en) * | 2008-05-04 | 2008-09-17 | 日月光半导体制造股份有限公司 | Stacking chip encapsulation structure and its making method |
| CN102446780A (en) * | 2011-12-19 | 2012-05-09 | 南通富士通微电子股份有限公司 | Wafer-level packaging method |
| CN103762187A (en) * | 2014-01-16 | 2014-04-30 | 苏州晶方半导体科技股份有限公司 | Chip packaging method and structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016107336A1 (en) * | 2014-12-30 | 2016-07-07 | 南通富士通微电子股份有限公司 | Method for manufacturing wafer level package |
| US10008478B2 (en) | 2014-12-30 | 2018-06-26 | Tongfu Microelectronics Co., Ltd. | Fabricating method for wafer-level packaging |
| CN108461409A (en) * | 2018-03-29 | 2018-08-28 | 中国电子科技集团公司第四十三研究所 | A kind of CCGA devices plant column device and method |
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Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
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Application publication date: 20150603 |