CN104332418B - Chip-level packaging method - Google Patents
Chip-level packaging method Download PDFInfo
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- CN104332418B CN104332418B CN201410426336.4A CN201410426336A CN104332418B CN 104332418 B CN104332418 B CN 104332418B CN 201410426336 A CN201410426336 A CN 201410426336A CN 104332418 B CN104332418 B CN 104332418B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
Abstract
The invention relates to a chip-level packaging method which includes the following steps: forming a convex-point lower metal layer on an aluminum pad exposed from a passivation layer of a wafer; etching the convex-point lower metal layer so that gaps are formed between the convex-point lower metal layer and the passivation layer; and forming protective interface layers in the gaps. The convex-layer lower metal layer is formed firstly and then the convex-point lower metal layer is etched so that the gaps are formed between the convex-point lower layer and the passivation layer and then the protective interface layers are formed in the gaps. On one hand, because the convex-point lower metal layer is formed firstly, adverse effects such as existence of the residual of the interface layers in the prior art do not exist between the convex-point lower metal layer and the aluminum pad; and on the other hand, descum does not need to be carried out on the protective interface layers and thus procedure is simplified.
Description
Technical field
The present invention relates to field of semiconductor package, more particularly to chip-scale packaging method.
Background technology
In the prior art, chip-scale packaging method is usually that interface layer, Ran Houzai are initially formed on wafer (wafer Wafer)
Form ubm layer.This method also needs to be etched interface layer, forms opening, exposes aluminum cushion layer opening, but
It is the interface layer after etching, residual is easily formed in opening, these residuals can directly affects ubm layer and aluminium pad
Contact, causes the failure of metal under salient point.In actual production, interface layer can be ashed (descum), to reduce residual
Influence, but thereby result in the crash rate of chip grade packaging structure still more than 30%.
The structure of wafer is as shown in fig. 7, with copper packing layer 10 ', the first passivation layer 20 ' is formed on copper packing layer, first is blunt
Changing layer has opening, copper packing layer 10 ' is exposed from the opening, aluminium pad 30 ' is formed on the copper packing layer exposed from opening, on aluminium pad
The second passivation layer 40 ' is re-formed, and the second passivation layer also has opening, aluminium pad is exposed from opening.
The content of the invention
It is given below on brief overview of the invention, to provide the basic reason on certain aspects of the invention
Solution.It should be appreciated that this general introduction is not on exhaustive general introduction of the invention.It is not intended to determine key of the invention
Or pith, nor is it intended to limit the scope of the present invention.Its purpose only provides some concepts in simplified form, with
This is used as the preamble in greater detail discussed after a while.
The present invention provides a kind of chip-scale packaging method, including step：The shape on the aluminium pad exposed from the passivation layer of wafer
Into ubm layer；The ubm layer is etched, makes to etch shape between the ubm layer and the passivation layer
Into gap；Protection interface layer is formed in the gap.
In an embodiment of the invention, at least have the advantages that：Ubm layer is initially formed, this is etched convex
Point lower metal layer makes it that gap is formed between passivation layer, and protection interface layer is formed in gap.On the one hand, because being initially formed convex
Point lower metal layer, it is not in such as the remaining harmful effect of interface layer in the prior art between aluminium pad；On the other hand, it is not necessary to
Protection interface layer is ashed, program is simplified.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is chip-scale packaging method block diagram of the present invention；
Fig. 2 be the inventive method in, on wafer formed ubm layer schematic diagram；
Fig. 3 is in the inventive method, etching forms the schematic diagram in gap between ubm layer and passivation layer；
Fig. 4 is the schematic diagram that protection interface layer is formed in the gap of Fig. 3；
Fig. 5 is the schematic diagram after processing protection interface layer in Fig. 4；
Fig. 6 is the schematic diagram of chip grade packaging structure of the present invention；
Fig. 7 is the structural representation of wafer.
Reference：
Crystal circle structure：10 '-copper packing layer；20 '-the first passivation layers；30 '-aluminium pad；40 '-the second passivation layers.
Chip grade packaging structure of the present invention：1- ubm layers；2- gaps；3- protects interface layer；4- soldered balls.
Specific embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments.Described in an accompanying drawing of the invention or a kind of implementation method
Element and the element that can be shown in one or more other accompanying drawings or implementation method of feature and feature be combined.Should
Note, for purposes of clarity, eliminated in accompanying drawing and explanation unrelated to the invention, known to persons of ordinary skill in the art
Part and the expression and description for the treatment of.Based on the embodiment in the present invention, those of ordinary skill in the art are not paying creation
Property work on the premise of the every other embodiment that is obtained, belong to the scope of protection of the invention.
In following embodiment of the invention, the sequence number and/or sequencing of embodiment are merely convenient of description, do not represent reality
Apply the quality of example.Description to each embodiment all emphasizes particularly on different fields, and does not have the part described in detail in certain embodiment, may refer to it
The associated description of his embodiment.
The present invention provides a kind of chip-scale packaging method, referring to Fig. 1-Fig. 5, including step：Step 200, from wafer
Ubm layer 1 (as shown in Figure 2) is formed on the aluminium pad that passivation layer exposes；Step, 300, etch the ubm layer
1, etching between ubm layer 1 and passivation layer is formed gap 2 (as shown in Figure 3)；Step 400, forms in gap 2 and protects
Shield interface layer 3 (as shown in Figures 4 and 5).Wafer with reference to shown in Fig. 7, above-mentioned gap 2 refers to ubm layer 1 blunt with second
Change the gap between layer 40 ', describe for convenience, referring to the gap between ubm layer and passivation layer below, be all
Refer to the gap between ubm layer and the second passivation layer.
Be initially formed ubm layer 1, etching the ubm layer 1 makes it that gap 2 is formed between passivation layer,
Protection interface layer 3 is formed in gap 2.On the one hand, because being initially formed ubm layer 1, it is not in as now between aluminium pad
There is the harmful effect of technical agency's surface layer remaining；On the other hand, it is not necessary to protection interface layer 3 is ashed, program is simplified.
It is to be understood that during etching ubm layer, except etching the gap between ubm layer and passivation layer
Outward, ubm layer can also be etched into required shape according to the actual requirements, such as shown in Fig. 3, etches plant soldered ball
Plant bulb (in Fig. 3 A signified).
In a kind of optional implementation method, ubm layer 1 includes sputtering layer and electrodeposited coating, it is to be understood that, convex
During point lower metal layer 1 is formed, will not be grown fully according to the orientation where aluminium pad, such as the passivation layer around aluminium pad
It is likely to form a part of ubm layer 1.When ubm layer 1 is etched, can be along gold under passivation layer etching salient point
Category layer 1, to form above-mentioned gap 2.When protection interface layer 3 is formed, for example, the protection material of interface layer 3 can be poured into gap
2, to form above-mentioned protection interface layer 3, specifically will be described hereinafter.
Above-mentioned ubm layer 1 includes sputtering layer and electrodeposited coating, when ubm layer 1 is formed, including step
210, first sputter titanium copper on aluminium pad, step 220, then any one in electro-coppering, nickel or tin silver on sputtering layer, forms
Electrodeposited coating.It should be understood that the material only optional embodiment that sputtering layer and electrodeposited coating are used here, is not limited to this
Invention, other can be used as the material of ubm layer 1, are also applied for the present invention.
In a kind of optional implementation method, before electrodeposited coating is formed, also including step 211, photoetching is applied in sputtering layer
Glue, exposure imaging form photoetching agent pattern；After electrodeposited coating is formed, also including step 221, above-mentioned photoresist is etched.Above-mentioned light
Photoresist is to limit the position of electrodeposited coating growth.
Protection interface layer material is preferably polyimides (PI) or polyparaphenylene's benzo dioxazole (PBO).Protected being formed
During shield interface layer, step 410 can be divided into, protection interface layer material is applied between gap 2；Step 420, exposure, development are simultaneously
Solidification protection interface layer material, forms protection interface layer 3.Protection interface layer shown in Fig. 4 and Fig. 5 is identical, and Fig. 5 can be with
It is that the protection interface layer in Fig. 4 is further processed, for example, etches, is processed into meeting the form of use demand.
For example, protection interface layer is shorter compared to height in fig. 4 in Figure 5, it is to avoid the step of influence subsequently plants soldered ball.
At step 420, because formerly having formd ubm layer 1, therefore, it is not necessary to will specially protect
The opening exposed for aluminium pad is etched in interface layer 3, therefore just without being specially directed at some parts during exposure, and can be use
Blind exposure (blind build), therefore the time for exposure can be saved.
In a kind of optional implementation method, before ubm layer 1 is formed, including step 101, cleaning wafer.
In a kind of optional implementation method, after ubm layer 1 is etched, including step 201, cleaning wafer.
Finally, soldered ball 4 is planted on ubm layer.Certainly also need to carry out further whole chip grade packaging structure
Treatment of details, form chip grade packaging structure as shown in Figure 6, specific processing mode is just repeated no more here.
By the above-mentioned method of the present invention, technical process is simplified, manufacturing cost is thereby also reduced, while also reducing
The crash rate of chip grade packaging structure.
Finally it should be noted that：Although the present invention and its advantage has below been described in detail it should be appreciated that not
Various changes can be carried out in the case of the spirit and scope of the present invention being defined by the claims appended hereto, substitute and
Conversion.And, the scope of the present invention is not limited only to process, equipment, means, the specific reality of method and steps described by specification
Apply example.One of ordinary skilled in the art will readily appreciate that from the disclosure, can be used according to the present invention and held
The row function essentially identical to corresponding embodiment described herein obtains result, the existing and future essentially identical with it
Process to be developed, equipment, means, method or step.Therefore, appended claim is directed at being wrapped in the range of them
Include such process, equipment, means, method or step.
Claims (7)
1. a kind of chip-scale packaging method, it is characterised in that including step：
Ubm layer is formed on the aluminium pad exposed from the passivation layer of wafer；
The ubm layer is etched, etching between the ubm layer and the passivation layer is formed gap；
Protection interface layer is formed in the gap, wherein
Formed it is described protection interface layer the step of be：
Protection interface layer material is applied between the gap；
Expose, develop and solidify the protection interface layer material, form the protection interface layer.
2. chip-scale packaging method according to claim 1, it is characterised in that
The ubm layer includes sputtering layer and electrodeposited coating；
First sputtering forms sputtering layer on the aluminium pad, after plating forms electrodeposited coating on the sputtering layer again.
3. chip-scale packaging method according to claim 2, it is characterised in that
The sputtering layer is titanium copper；
The electrodeposited coating be copper, nickel or tin silver in any one.
4. chip-scale packaging method according to claim 2, it is characterised in that
Before the electrodeposited coating is formed, photoetching agent pattern is formed in the sputtering layer resist coating, exposure imaging；
After the electrodeposited coating is formed, the photoresist is etched.
5. chip-scale packaging method according to claim 1, it is characterised in that
Protected interface layer material is polyimides or polyparaphenylene's benzo dioxazole.
6. chip-scale packaging method according to claim 1 and 2, it is characterised in that
Before the ubm layer is formed, the wafer is cleaned.
7. chip-scale packaging method according to claim 1 and 2, it is characterised in that
After the ubm layer is etched, before forming the protection interface layer, the wafer is cleaned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410426336.4A CN104332418B (en) | 2014-08-26 | 2014-08-26 | Chip-level packaging method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410426336.4A CN104332418B (en) | 2014-08-26 | 2014-08-26 | Chip-level packaging method |
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| Publication Number | Publication Date |
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| CN104332418A CN104332418A (en) | 2015-02-04 |
| CN104332418B true CN104332418B (en) | 2017-05-24 |
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| CN201410426336.4A Active CN104332418B (en) | 2014-08-26 | 2014-08-26 | Chip-level packaging method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101090099A (en) * | 2006-06-12 | 2007-12-19 | 中芯国际集成电路制造(上海)有限公司 | Solder lug and manufacturing method thereof |
| CN102543781A (en) * | 2012-01-17 | 2012-07-04 | 南通富士通微电子股份有限公司 | Optimizing process of wafer-level packaging |
| CN103811451A (en) * | 2014-01-23 | 2014-05-21 | 南通富士通微电子股份有限公司 | Chip scale package structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7294241B2 (en) * | 2003-01-03 | 2007-11-13 | Chartered Semiconductor Manufacturing Ltd. | Method to form alpha phase Ta and its application to IC manufacturing |
| JP5284125B2 (en) * | 2009-01-23 | 2013-09-11 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| US8003512B2 (en) * | 2009-02-03 | 2011-08-23 | International Business Machines Corporation | Structure of UBM and solder bumps and methods of fabrication |
-
2014
- 2014-08-26 CN CN201410426336.4A patent/CN104332418B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101090099A (en) * | 2006-06-12 | 2007-12-19 | 中芯国际集成电路制造(上海)有限公司 | Solder lug and manufacturing method thereof |
| CN102543781A (en) * | 2012-01-17 | 2012-07-04 | 南通富士通微电子股份有限公司 | Optimizing process of wafer-level packaging |
| CN103811451A (en) * | 2014-01-23 | 2014-05-21 | 南通富士通微电子股份有限公司 | Chip scale package structure |
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| CN104332418A (en) | 2015-02-04 |
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Inventor after: Ding Wanchun Inventor before: Wang Zitai |
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Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
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