TWM410659U - Bump structure - Google Patents

Bump structure Download PDF

Info

Publication number
TWM410659U
TWM410659U TW100209050U TW100209050U TWM410659U TW M410659 U TWM410659 U TW M410659U TW 100209050 U TW100209050 U TW 100209050U TW 100209050 U TW100209050 U TW 100209050U TW M410659 U TWM410659 U TW M410659U
Authority
TW
Taiwan
Prior art keywords
peripheral wall
outer peripheral
layer
wall
bump
Prior art date
Application number
TW100209050U
Other languages
Chinese (zh)
Inventor
Lung-Hua Ho
Chih-Ming Kuo
Kun-Shu Chuang
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Priority to TW100209050U priority Critical patent/TWM410659U/en
Publication of TWM410659U publication Critical patent/TWM410659U/en

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

100年07月01日核正替换亩. M410659 五、新型說明: 【新型所屬之技術領域】 [0001] 本創作係有關於一種凸塊結構,特別係有關於一種 可防止短路之凸塊結構。 【先前技術】 [0002] 如第1A至1H圖,習知凸塊製程係至少包含下列步驟On July 1, 100, the nuclear replacement is mu. M410659 V. New description: [New technical field] [0001] This creation is about a bump structure, especially for a bump structure that can prevent short circuit. [Prior Art] [0002] As shown in FIGS. 1A to 1H, the conventional bump process system includes at least the following steps.

:首先,請參閱第1A圖,提供一基板10,該基板10係具 有一表面11、複數個設置於該表面11之銲墊12及一形成 於該表面11之保護層13,該保護層13係顯露該些銲墊12 ;接著,請參閱第1B圖,形成一含銅金屬層20於該些銲 墊12及該保護層13 ;之後,請參閱第1C圖,形成一光阻 層30於該含銅金屬層20 ;接著,請參閱第1D圖,圖案化 該光阻層30以形成複數値開口 31 ;之後,請參閱·第1E圖 ,形成複數個銅凸塊40於該些開口 31内,各該銅凸塊40 係具有一第一外周壁41 ;接著,請參閱第1F圖,形成一 導接層50於該些銅凸塊40 ;之後,請參閱第1G圖,移除 該光阻層30,最後,請參閱第1H圖,利用蝕刻方法移除 未被該些銅凸塊40覆蓋之該含銅金屬層20以形成一凸塊 下金屬層21,各該凸塊下金屬層21係具有一第二外周壁 21a,然在進行移除未被該些銅凸塊40覆蓋之該含銅金屬 層20的步驟時,由於該些銅凸塊40之材質係包含有銅, 因此該些銅凸塊40會同時與該含銅金屬層20—起被蝕刻 而導致該些銅凸塊40之該些第一外周壁41產生凹陷之情 形,且該些凸塊下金屬層21之該些第二外周壁21a凹陷之 程度更大於該些銅凸塊40之該些第一外周壁41,此外, 表單编號A0101 第4頁/共18頁 M41Q659 100年07月01日修正替换百 由於該些第一外周壁41及該些第二外周壁21a凹陷且裸露 ,因此容易造成銅離子游離之現象而導致短路之情形發 生0 【新型内容】 [0003] 本創作之主要目的係在於提供一種凸塊結構,其包 含一基板、複數個凸塊下金屬層、複數個銅凸塊、一導 接層、一第一保護環以及一第二保護環,該基板係具有 一表面、複數個銲墊及一第一保護層,該些銲墊係設置 於該表面,該第一保護層係形成於該表面並顯露該些銲 墊,各該凸塊下金屬層係具有一第一外周壁,該些銅凸 塊係形成於該些凸塊下金屬層上,各該銅凸塊係具有一 第一頂面及一第二外周壁,該導接層係形成於該些銅凸 塊之該些第一頂面,該導接層係具有一第二頂面及一第 三外周壁,且該導接層係包含有一鎮層及一接合層,該 鎳層係位於該銅凸塊與該接合層之間,其中該第三外周 壁與該第二外周壁之間係具有一第一間距,該第三外周 壁與該第一外周壁之間係具有一第二間距且該導接層及 該第一保護層之間係具有一容置空間,該容置空間係環 繞該第一外周壁及該第二外周壁,且該容置空間係具有 一對應於該第一外周壁之第一容置部及一對應於該第二 外周壁之第二容置部,該第一保護環係形成於該第一容 置部,該第二保護環係形成於該第二容置部。由於環繞 該些凸塊下金屬層之該些第一容置部係形成有該些第一 保護環,環繞該些銅凸塊之該些第二容置部係形成有該 些第二保護環,因此可避免該些凸塊下金屬層之該些第 一外周壁及該些銅凸塊之該些第二外周壁裸露而造成銅 表單編號A0101 第5頁/共18頁 100年07月01日按正替換頁 M410659 離子游離導致短路之情形。 【實施方式】 [0004] 請參閱第2A至2J圖,其係本創作之一較佳實施例,First, referring to FIG. 1A, a substrate 10 is provided. The substrate 10 has a surface 11 , a plurality of pads 12 disposed on the surface 11 , and a protective layer 13 formed on the surface 11 . The protective layer 13 The pads 12 are exposed; then, referring to FIG. 1B, a copper-containing metal layer 20 is formed on the pads 12 and the protective layer 13; thereafter, refer to FIG. 1C to form a photoresist layer 30. The copper-containing metal layer 20; then, referring to FIG. 1D, the photoresist layer 30 is patterned to form a plurality of germanium openings 31; thereafter, referring to FIG. 1E, a plurality of copper bumps 40 are formed in the openings 31. Each of the copper bumps 40 has a first outer peripheral wall 41; then, referring to FIG. 1F, a conductive layer 50 is formed on the copper bumps 40; thereafter, refer to FIG. 1G to remove the The photoresist layer 30, and finally, referring to FIG. 1H, the copper-containing metal layer 20 not covered by the copper bumps 40 is removed by an etching method to form an under bump metal layer 21, and each of the under bump metal layers The layer 21 has a second outer peripheral wall 21a, but when the step of removing the copper-containing metal layer 20 not covered by the copper bumps 40 is performed, Since the copper bumps 40 are made of copper, the copper bumps 40 are simultaneously etched with the copper-containing metal layer 20 to cause the first outer peripheral walls 41 of the copper bumps 40. The second outer peripheral wall 21a of the under bump metal layer 21 is recessed to a greater extent than the first outer peripheral walls 41 of the copper bumps 40. Further, the form number A0101 is 4 Page 41 of 18 M41Q659 Correction of the replacement of the first outer peripheral wall 41 and the second outer peripheral wall 21a are recessed and exposed, so that copper ions are easily released and the short circuit occurs. [New content] [0003] The main purpose of the present invention is to provide a bump structure comprising a substrate, a plurality of under bump metal layers, a plurality of copper bumps, a conductive layer, a first guard ring, and a second protection ring, the substrate has a surface, a plurality of pads, and a first protective layer, wherein the pads are disposed on the surface, the first protective layer is formed on the surface and the pads are exposed Each of the under bump metal layers has a first outer a plurality of copper bumps formed on the underlying metal layers, each of the copper bumps having a first top surface and a second outer peripheral wall, the conductive layer being formed on the copper bumps The first top surface, the guiding layer has a second top surface and a third outer peripheral wall, and the guiding layer comprises a town layer and a bonding layer, and the nickel layer is located on the copper bump Between the third outer peripheral wall and the second outer peripheral wall, a first spacing is formed between the third outer peripheral wall and the first outer peripheral wall, and the second outer peripheral wall and the first outer peripheral wall have a second spacing and the guiding An accommodating space surrounds the first outer peripheral wall and the second outer peripheral wall, and the accommodating space has a corresponding one of the first outer peripheral walls. a first accommodating portion and a second accommodating portion corresponding to the second outer peripheral wall, the first guard ring is formed on the first accommodating portion, and the second guard ring is formed in the second accommodating portion unit. The second protection rings are formed around the second accommodating portions of the copper bumps by forming the first protection rings around the first accommodating portions of the underlying metal layers. Therefore, the first outer peripheral walls of the underlying metal layers of the bumps and the second outer peripheral walls of the copper bumps are prevented from being exposed to cause the copper form number A0101. Page 5 of 18 pages 100 July 01 The daily press replaces the page M410659. The ion is free to cause a short circuit. [Embodiment] [0004] Please refer to Figures 2A to 2J, which is a preferred embodiment of the present invention,

一種凸塊製程,其至少包含下列步驟:首先,請參閱第 2A圖,提供一基板110,該基板110係具有一表面111、 複數個銲墊112及一第一保護層113,該些銲墊11 2係設 置於該表面111,該第一保護層113係形成於該表面111 並顯露該些銲墊112,該基板110之材質矽可選自於鍺化 矽基板、砷化鎵基板或藍寶石基板其中之一,該第一保 護層113之材質係可選自於二氧化矽、氮化矽、氮氧化矽 或其混合體其中之一;接著,請參閱第2B圖,形成一含 銅金屬層120於些銲墊112及該第一保護層113,該含銅 金屬層120係具有複數個第一區121及複數個第二區122 ;之後,請參閱第2C圖,形成一光阻層130於該含銅金屬 層120 ;接著,請參閱第2D圖,圖案化該光阻層130以形 成複數個開口 131,該些開口 131係對應該些第一區121 ;之後,請參閱第2E圖,形成複數個銅凸塊140於該些開 口 131内,各該銅凸塊140係覆蓋該含銅金屬層120之各 該第一區121且各該銅凸塊140係具有一第一頂面141 ; 接著,請參閱第2F圖,形成一導接層150於該些銅凸塊 140之該些第一頂面141,該導接層150係具有一第二頂 面151且該導接層150係包含有一鎳層152及一接合層153 ,該鎳層152係位於該銅凸塊140與該接合層153之間, 該接合層153之材質係可選自於金、銀或鉛其中之一,在 本實施例中,該接合層153之材質係為金;之後,請參閱 第2G圖,移除該光阻層130 ;接著,請參閱第2H圖,移除 表單編號A0101 第6頁/共18頁 100年07月01日按正替換頁 該含銅金屬層120之該些第二區122以顯露出該第一保護 層113,並使該含銅金屬層120之各該第一區121形成一 凸塊下金屬層123,其中各該凸塊下金屬層123係具有一 第一外周壁123a,各該銅凸塊140係具有—第二外周壁 142,該導接層150係具有一第三外周壁154,該第一外 周壁123a係具有一第一外周長L1,該第二外周壁Η〗係 具有一第二外周長L2,該第三外周壁154係具有一第三外 周長L3 ’該第二外周長L3係大於該第二外周長^2,該第 一外周長L 2係不小於該第一外周長l 1,該第三外周壁15 4 與s亥第一外周壁14 2之間係具有一第一間距j) 1,該第三外 周壁154與該第一外周壁1233之間係具有一第二間距!)2 ,該第一間距D 2係不小於該第一間距d 1,該導接層15 〇及 該第一保護層11 3之間係具有一容置空間§,該容置空間$ 係環繞該第一外周壁123a及該第二外周壁142,且該容置 空間s係具有一對應於該第一外周壁123&之第一容置部S1 及一對應於該第二外周壁142之第二容置部S2 ;之後,請 參閱第21圖,形成一第二保護層160於該導接層15〇之該 第一頂面151、該些凸塊下金屬層123之該些第一外周壁 123a、該些銅凸塊140之該些第二外周壁142、該導接層 150之該第三外周壁154、該第一保護層113、該第一容 置部S1及該第一谷置部S2,該第二保護層160係可選自於 氧化物或氮化物其中之一,在本實施例中,該氮化物係 可為氮化矽,該氧化物係可為二氧化矽;最後,請參閱 第2J圖’移除位於該導接層15〇之該第二頂面151、該導 接層150之該第三外周壁154及該第一保護層113之該第 二保護層160,以使位於該第一容置部51之該第二保護層 表單編號A0101 第7頁/共丨8頁 M410659 100年ϋ7月01日梭正替換頁A bump process includes at least the following steps: First, referring to FIG. 2A, a substrate 110 is provided. The substrate 110 has a surface 111, a plurality of pads 112, and a first protective layer 113. The pads are provided. The first protective layer 113 is formed on the surface 111 and the pads 112 are exposed. The material of the substrate 110 can be selected from a germanium telluride substrate, a gallium arsenide substrate or a sapphire. One of the substrates, the material of the first protective layer 113 may be selected from one of cerium oxide, cerium nitride, cerium oxynitride or a mixture thereof; and then, refer to FIG. 2B to form a copper-containing metal. The layer 120 is formed on the solder pads 112 and the first protective layer 113. The copper-containing metal layer 120 has a plurality of first regions 121 and a plurality of second regions 122. Thereafter, refer to FIG. 2C to form a photoresist layer. 130 in the copper-containing metal layer 120; then, referring to FIG. 2D, the photoresist layer 130 is patterned to form a plurality of openings 131 corresponding to the first regions 121; then, refer to the second portion a plurality of copper bumps 140 are formed in the openings 131, each of the copper bumps The 140 series covers the first regions 121 of the copper-containing metal layer 120 and each of the copper bumps 140 has a first top surface 141. Next, please refer to FIG. 2F to form a conductive layer 150 on the copper. The first top surface 141 of the bump 140 has a second top surface 151 and the conductive layer 150 includes a nickel layer 152 and a bonding layer 153. Between the copper bumps 140 and the bonding layer 153, the material of the bonding layer 153 may be selected from one of gold, silver or lead. In the embodiment, the bonding layer 153 is made of gold; Please refer to FIG. 2G to remove the photoresist layer 130; then, refer to FIG. 2H, remove the form number A0101, page 6 / page 18, page 100, July 01, according to the replacement page, the copper-containing metal layer 120 The second regions 122 are formed to expose the first protective layer 113, and each of the first regions 121 of the copper-containing metal layer 120 is formed with an under bump metal layer 123, wherein each of the under bump metal layers 123 The first outer peripheral wall 123a has a first outer peripheral wall 142, and the conductive layer 150 has a third outer peripheral wall 154. The peripheral wall 123a has a first outer perimeter L1, the second outer perimeter wall has a second outer perimeter L2, and the third outer perimeter wall 154 has a third outer perimeter L3 'the second outer perimeter L3 is greater than The first outer circumference L2 is not less than the first outer circumference l1, and the first outer peripheral wall 15 4 has a first spacing between the first outer peripheral wall 14 4 and the first outer peripheral wall 14 2 j) 1, the third outer peripheral wall 154 and the first outer peripheral wall 1233 have a second spacing !) 2, the first spacing D 2 is not less than the first spacing d 1, the guiding layer 15 Between the first protective layer and the first protective layer 113, the accommodating space § is surrounded by the first outer peripheral wall 123a and the second outer peripheral wall 142, and the accommodating space s has a corresponding a first receiving portion S1 of the first outer peripheral wall 123 & and a second receiving portion S2 corresponding to the second outer peripheral wall 142; then, referring to FIG. 21, a second protective layer 160 is formed thereon. The first top surface 151 of the guiding layer 15 , the first outer peripheral walls 123 a of the under bump metal layers 123 , and the second outer peripheral walls 142 of the copper bumps 140 The third outer peripheral wall 154 of the layer 150, the first protective layer 113, the first receiving portion S1 and the first valley portion S2, the second protective layer 160 may be selected from an oxide or a nitride. In one embodiment, in the embodiment, the nitride system may be tantalum nitride, and the oxide may be tantalum dioxide; finally, please refer to FIG. 2J to remove the first layer located on the conductive layer 15 The second top surface 151, the third outer peripheral wall 154 of the guiding layer 150 and the second protective layer 160 of the first protective layer 113, so that the second protective layer form number located in the first receiving portion 51 A0101 Page 7 / A total of 8 pages M410659 100 years old July 01 shuttle replacement page

160形成一第一保護環161,及使位於該第二容置部S2之 該第二保護層160形成一第二保護環1 62以形成一凸塊結 構100,且該第一保護環161係連接該第二保護環162。 由於環繞該些凸塊下金屬層123之該些第一容置部S1係形 成有該些第一保護環161,環繞該些銅凸塊140之該些第 二容置部S2係形成有該些第二保護環162,因此該些凸塊 下金屬層123之該些第一外周壁123a及該些銅凸塊140之 該些第二外周壁142並無裸露,故可避免銅離子游離而造 成短路之情形。 較佳地,在本實施例中,該第一保護環161係具有一 第一環壁161a,該第二保護環162係具有一第二環壁 162a,該第一環壁161a、該第二環壁162a及該第三外周 壁154係為平齊。 本創作之保護範圍當視後附之申請專利範圍所界定 者為準,任何熟知此項技藝者,在不脫離本創作之精神 和範圍内所作之任何變化與修改,均屬於本創作之保護 範圍。 【圖式簡單說明】 [0005] 第1A至1H圖:習知凸塊製程之截面示意圖。 第2A至2J圖:依據本創作之一較佳實施例,一種凸塊製 程之截面示意圖。 【主要元件符號說明】 [0006] 10 基板 11 表面 12 銲墊 13 保護層 .20 含銅金屬層 21 凸塊下金屬層 表單編號A0101 第8頁/共18頁 M410659A first guard ring 161 is formed, and a second guard ring 160 is formed on the second protective layer 160 of the second receiving portion S2 to form a bump structure 100, and the first guard ring 161 is The second guard ring 162 is connected. The first receiving portions 161 are formed around the first accommodating portions S1 of the underlying metal layers 123, and the second accommodating portions S2 surrounding the copper bumps 140 are formed. The second protective ring 162 is such that the first outer peripheral wall 123a of the under bump metal layer 123 and the second outer peripheral walls 142 of the copper bumps 140 are not exposed, so that copper ions are prevented from being detached. Causes a short circuit. Preferably, in the embodiment, the first guard ring 161 has a first ring wall 161a, and the second guard ring 162 has a second ring wall 162a, the first ring wall 161a, the second The ring wall 162a and the third outer peripheral wall 154 are flush. The scope of protection of this creation is subject to the definition of the scope of the patent application, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of this creation are within the scope of protection of this creation. . BRIEF DESCRIPTION OF THE DRAWINGS [0005] FIGS. 1A to 1H are schematic cross-sectional views of a conventional bump process. 2A to 2J are schematic cross-sectional views showing a bump process in accordance with a preferred embodiment of the present invention. [Main component symbol description] [0006] 10 Substrate 11 Surface 12 Solder pad 13 Protective layer .20 Copper-containing metal layer 21 Under bump metal layer Form No. A0101 Page 8 of 18 M410659

100年07月01日按正替换頁 21a第二外周壁 30光阻層 31開口 40銅凸塊 41第一外周壁 50導接層 100凸塊結構 110基板 111表面 112銲墊 113第一保護層 120含銅金屬層 121第一區 122第二區 123凸塊下金屬層 123a第一外周壁 130光阻層 131 開口 140銅凸塊 141第一頂面 142第二外周壁 150導接層 151第二頂面 152鎳層 153接合層 154第三外周壁 160第二保護層 161第一保護環 161a第一環壁 162第二保護環 162a第二環壁 D1第一間距 D2第二間距 L1第一外周長 L2第二外周長 L3第三外周長 S容置空間 S1第一容置部 S2第二容置部 表單編號A0101 第9頁/共18頁July 01, 100, according to the replacement page 21a second outer peripheral wall 30 photoresist layer 31 opening 40 copper bump 41 first outer peripheral wall 50 conductive layer 100 bump structure 110 substrate 111 surface 112 pad 113 first protective layer 120 copper-containing metal layer 121 first region 122 second region 123 bump lower metal layer 123a first outer peripheral wall 130 photoresist layer 131 opening 140 copper bump 141 first top surface 142 second outer peripheral wall 150 conductive layer 151 Two top surface 152 nickel layer 153 bonding layer 154 third outer peripheral wall 160 second protective layer 161 first guard ring 161a first ring wall 162 second guard ring 162a second ring wall D1 first pitch D2 second pitch L1 first Outer circumference L2 Second outer circumference L3 Third outer circumference S accommodation space S1 First accommodation part S2 Second accommodation part Form number A0101 Page 9 of 18

Claims (1)

M410659 __ 100年07月01日修正替换k 六、申請專利範圍: 1 . 一種凸塊結構,其至少包含: 一基板,其係具有一表面、複數個銲墊及一第一保護層, 該些銲墊係設置於該表面,該第一保護層係形成於該表面 並顯露該些銲墊; 複數個凸塊下金屬層,各該凸塊下金屬層係具有一第一外 周壁; 複數個銅凸塊,其係形成於該些凸塊下金屬層上,各該銅 凸塊係具有一第一頂面及一第二外周壁; 一導接層,其係形成於該些銅凸塊之該些第一頂面,該導 接層係具有一第二頂面及一第三外周壁,且該導接層係包 含有一鎳層及一接合層,該鎳層係位於該銅凸塊與該接合 層之間,其中該第三外周壁與該第二外周壁之間係具有一 第一間距,該第三外周壁與該第一外周壁之間係具有一第 二間距且該導接層及該第一保護層之間係具有一容置空間 ,該容置空間係環繞該第一外周壁及該第二外周壁,且該 容置空間係具有一對應於該第一外周壁之第一容置部及一 對應於該第二外周壁之第二容置部; 一第一保護環,其係形成於該第一容置部;以及 一第二保護環,其係形成於該第二容置部。 2.如申請專利範圍第1項所述之凸塊結構,其中該第一保護 環係連接該第二保護環。 3 .如申請專利範圍第1項所述之凸塊結構,其中該第一保護 環係具有一第一環壁,該第二保護環係具有一第二環壁, 該第一環壁、該第二環壁及該第三外周壁係為平齊。 4 .如申請專利範圍第1項所述之凸塊結構,其中該第三外周 1003236470-0 100209050 表單編號A0101 第10頁/共18頁 M410659 100年07月01日修正替換頁 壁係具有一第三外周長,該第二外周壁係具有一第二外周 長,該第一外周壁係具有一第一外周長,該第三外周長係 大於該第二外周長,該第二外周長係不小於該第一外周長 〇 5 .如申請專利範圍第1項所述之凸塊結構,其中該第二間距 係不小於該第一間距。 6.如申請專利範圍第1項所述之凸塊結構,其中該第二保護 層係選自於氧化物或氮化物其中之一。 7 .如申請專利範圍第6項所述之凸塊結構,其中該氮化物係 可為氮化矽、氮氧化矽或其混合體其中之一。 8 .如申請專利範圍第6項所述之凸塊結構,其中該氧化物係 可為二氧化矽、氮氧化矽或其混合體其中之一。M410659 __ Revised and replaced by K1, July 1, 2016. Patent application scope: 1. A bump structure comprising at least: a substrate having a surface, a plurality of pads and a first protective layer, a pad is disposed on the surface, the first protective layer is formed on the surface and the pads are exposed; a plurality of under bump metal layers, each of the under bump metal layers having a first peripheral wall; a copper bump is formed on the underlying metal layer, each of the copper bumps has a first top surface and a second outer peripheral wall; and a conductive layer formed on the copper bumps The first top surface, the guiding layer has a second top surface and a third outer peripheral wall, and the guiding layer comprises a nickel layer and a bonding layer, wherein the nickel layer is located on the copper bump Between the third outer peripheral wall and the second outer peripheral wall, a first spacing is formed between the third outer peripheral wall and the first outer peripheral wall, and the second outer peripheral wall and the first outer peripheral wall have a second spacing and the guiding An accommodating space is formed between the connecting layer and the first protective layer, and the accommodating space surrounds the a first outer peripheral wall and the second outer peripheral wall, and the accommodating space has a first accommodating portion corresponding to the first outer peripheral wall and a second accommodating portion corresponding to the second outer peripheral wall; a guard ring formed on the first receiving portion; and a second guard ring formed in the second receiving portion. 2. The bump structure of claim 1, wherein the first guard ring is connected to the second guard ring. 3. The bump structure of claim 1, wherein the first guard ring has a first ring wall, the second guard ring has a second ring wall, the first ring wall, the first ring wall The second annular wall and the third peripheral wall are flush. 4. The bump structure according to claim 1, wherein the third outer circumference is 1003236470-0 100209050, the form number A0101, the 10th page, the total 18 pages, the M410659, the first of July, the revised replacement page wall has a first a third outer perimeter, the second outer peripheral wall has a second outer perimeter, the first outer peripheral wall having a first outer perimeter, the third outer perimeter being greater than the second outer perimeter, the second outer perimeter being The bump structure is less than the first outer circumference 〇5. The bump structure according to claim 1, wherein the second pitch is not less than the first pitch. 6. The bump structure of claim 1, wherein the second protective layer is selected from one of an oxide or a nitride. 7. The bump structure of claim 6, wherein the nitride system is one of tantalum nitride, hafnium oxynitride or a mixture thereof. 8. The bump structure of claim 6, wherein the oxide is one of cerium oxide, cerium oxynitride or a mixture thereof. 1003236470-0 100209050 表單編號A0101 第11頁/共18頁1003236470-0 100209050 Form No. A0101 Page 11 of 18
TW100209050U 2011-05-20 2011-05-20 Bump structure TWM410659U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW100209050U TWM410659U (en) 2011-05-20 2011-05-20 Bump structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100209050U TWM410659U (en) 2011-05-20 2011-05-20 Bump structure

Publications (1)

Publication Number Publication Date
TWM410659U true TWM410659U (en) 2011-09-01

Family

ID=46418003

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100209050U TWM410659U (en) 2011-05-20 2011-05-20 Bump structure

Country Status (1)

Country Link
TW (1) TWM410659U (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165481A (en) * 2011-12-13 2013-06-19 颀邦科技股份有限公司 Bump manufacture technology and structure thereof
TWI473184B (en) * 2011-12-22 2015-02-11 矽品精密工業股份有限公司 Conductive bump structure and method for fabricating the same
TWI485790B (en) * 2012-02-17 2015-05-21 Chipbond Technology Corp Method for manufacturing fine pitch bumps and structure thereof
TWI487443B (en) * 2014-04-30 2015-06-01 Wistron Neweb Corp Method of fabricating substrate structure and substrate structure fabricated by the same method
CN109979834A (en) * 2019-03-29 2019-07-05 颀中科技(苏州)有限公司 Bump manufacturing method for semiconductor packages

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165481A (en) * 2011-12-13 2013-06-19 颀邦科技股份有限公司 Bump manufacture technology and structure thereof
CN103165481B (en) * 2011-12-13 2015-07-15 颀邦科技股份有限公司 Bump manufacture technology and structure thereof
TWI473184B (en) * 2011-12-22 2015-02-11 矽品精密工業股份有限公司 Conductive bump structure and method for fabricating the same
TWI485790B (en) * 2012-02-17 2015-05-21 Chipbond Technology Corp Method for manufacturing fine pitch bumps and structure thereof
TWI487443B (en) * 2014-04-30 2015-06-01 Wistron Neweb Corp Method of fabricating substrate structure and substrate structure fabricated by the same method
CN109979834A (en) * 2019-03-29 2019-07-05 颀中科技(苏州)有限公司 Bump manufacturing method for semiconductor packages

Similar Documents

Publication Publication Date Title
TWI505433B (en) Chip package and fabrication method thereof
US8624392B2 (en) Electrical connection for chip scale packaging
TWI235439B (en) Wiring structure on semiconductor substrate and method of fabricating the same
US20080169559A1 (en) Bump structure with annular support and manufacturing method thereof
EP2229694B1 (en) Semiconductor chip under-bump metallization structure and manufacturing method thereof
US10068861B2 (en) Semiconductor device
US20170025370A1 (en) Chip scale sensing chip package and a manufacturing method thereof
CN106206505B (en) Semiconductor device and method for manufacturing semiconductor device
TWM410659U (en) Bump structure
JP6108698B2 (en) Method for manufacturing solid-state imaging device
US9768067B2 (en) Chip package and manufacturing method thereof
TW201630133A (en) Samiconductor packaging structure and manufactoring method for the same
CN106898589B (en) Integrated circuit with a plurality of transistors
US10256179B2 (en) Package structure and manufacturing method thereof
US20170271432A1 (en) Inductor structure and manufacturing method thereof
TW201241959A (en) Method for fabricating metal redistribution layer
US10424537B2 (en) Device with pillar-shaped components
CN107342261B (en) Semiconductor device and method for manufacturing the same
JP2005101144A (en) Semiconductor device and method for manufacturing semiconductor device
JP2008218494A (en) Semiconductor device and its manufacturing method
TWI440150B (en) Bumping process and structure thereof
US8048802B2 (en) Method for forming interlayer insulating film in semiconductor device
KR20090127742A (en) Wafer level chip scale package and fabricating method of the same
US11424204B2 (en) Semiconductor component and manufacturing method thereof
US9953894B2 (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
MM4K Annulment or lapse of a utility model due to non-payment of fees