CN109979834A - Bump manufacturing method for semiconductor packages - Google Patents
Bump manufacturing method for semiconductor packages Download PDFInfo
- Publication number
- CN109979834A CN109979834A CN201910249907.4A CN201910249907A CN109979834A CN 109979834 A CN109979834 A CN 109979834A CN 201910249907 A CN201910249907 A CN 201910249907A CN 109979834 A CN109979834 A CN 109979834A
- Authority
- CN
- China
- Prior art keywords
- metal layer
- bump
- gap
- semiconductor packages
- reaming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
- H01L2224/11825—Plating, e.g. electroplating, electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The present invention provides a kind of bump manufacturing methods for semiconductor packages, comprising the following steps: provides a substrate, the top of the substrate is equipped with the first metal layer and the second metal layer above the first metal layer；Photoresist layer is set in the second metal layer, patterns the photoresist layer and forms opening；Copper bump is set in the opening；By opening a window, reaming makes to generate gap between the copper bump and the photoresist layer；Further increase the gap until reaching required width by etching the copper bump；Top electronickelling matter metal layer and the filling gap in the copper bump；Golden metal layer is electroplated in the top of the nickel matter metal layer；Remove the photoresist layer and the second metal layer and the first metal layer below the photoresist layer.Bump manufacturing method of the present invention for semiconductor packages not only simplifies operation in technique, more significantly reduces production cost.
Description
Technical field
The present invention relates to a kind of bump manufacturing methods for semiconductor packages.
Background technique
Nickel plating is generallyd use to the protection of the side wall of copper bump in traditional encapsulation technology to realize, general manufacturing method
Are as follows: first to photoresist layer aperture, from bottom to top an electro-coppering, nickel and gold in aperture, secondly, photoresist layer is removed, finally, by convex
Block carries out electronickelling again with the side wall of coated copper, however, using secondary nickel plating, not only work in entire convex block manufacturing process
Skill is complicated, and cost is larger.
In view of this, it is necessary to the existing bump manufacturing method for semiconductor packages be improved, on solving
State problem.
Summary of the invention
It is simple to manufacture and the lower-cost convex block manufacture for semiconductor packages the purpose of the present invention is to provide a kind of
Method.
For achieving the above object, the present invention provides a kind of bump manufacturing methods for semiconductor packages, special
Sign is, comprising the following steps:
One substrate is provided, the top of the substrate be equipped with the first metal layer and above the first metal layer second
Metal layer；
Photoresist layer is set in the second metal layer, patterns the photoresist layer and forms opening；
Copper bump is set in the opening；
By opening a window, reaming makes to generate gap between the copper bump and the photoresist layer；
Further increase the gap until reaching required width by etching the copper bump；
Top electronickelling matter metal layer and the filling gap in the copper bump；
Golden metal layer is electroplated in the top of the nickel matter metal layer；
Remove the photoresist layer and the second metal layer and the first metal layer below the photoresist layer.
As a further improvement of the present invention, the windowing reaming includes primary windowing reaming and secondary windowing reaming, institute
It states primary windowing reaming to handle using baking, the secondary windowing reaming using plasma etching process.
As a further improvement of the present invention, the primary windowing reaming specifically includes: in the baking oven with inert gas
In and the baking oven temperature between 120~150 DEG C under conditions of toast 40~60min, make the photoresist layer and the copper
The gap is generated between convex block.
As a further improvement of the present invention, the inert gas is nitrogen.
As a further improvement of the present invention, the primary windowing reaming makes the gap reach the first width, and described
The range of one width is 3~5um, and the secondary windowing reaming makes the gap reach the second width, the model of second width
It encloses for 5~8um.
As a further improvement of the present invention, by etching the copper bump, to increase further to the gap required
Width specifically includes: copper bump described in chemical etching makes the gap further expansion to third width, the third width
Range is 8~12um.
As a further improvement of the present invention, described to be etched to chemical etching, the chemical etching uses hydrogen peroxide medicine
Liquid is filled the gap and is etched to the copper bump.
As a further improvement of the present invention, the time range of the chemical etching is 20~40min.
As a further improvement of the present invention, the chemical etching, which further etches the second metal layer, keeps the copper convex
Block and the side wall of the second metal layer are coplanar in above-below direction.
As a further improvement of the present invention, the top surface of the golden metal layer is lower than the photoresist in the up-down direction
Layer.
Beneficial effects of the present invention: side by open a window reaming of the present invention for the bump manufacturing method of semiconductor packages
Formula makes the left and right sidewall of the copper bump and the photoresist layer generates the gap, and passes through the practical hydrogen peroxide medicine of chemical etching
Liquid further etches the copper bump and the second metal layer to increase the gap to reach required width, then electric
The nickel matter metal layer is plated in the top of the copper bump and fills the full gap to coat the copper bump and described the
The left and right sidewall of two metal layers not only simplifies operation, more significantly reduces production cost in technique.
Detailed description of the invention
Fig. 1 is the schematic diagram that photoresist layer of the present invention forms opening.
Fig. 2 is the schematic diagram that the present invention forms copper bump in opening.
Fig. 3 is schematic diagram of the present invention to photoresist layer windowing reaming.
Fig. 4 is schematic diagram of the present invention to copper bump and second metal layer chemical etching.
Fig. 5 is the schematic diagram of present invention electroless nickel layer and layer gold on copper bump.
Fig. 6 is that the present invention removes the schematic diagram after photoresist layer, second metal layer and the first metal layer.
Specific embodiment
Below with reference to embodiment shown in the drawings, the present invention will be described in detail.But the embodiment is not intended to limit
The present invention, structure that those skilled in the art are made according to the embodiment, method or transformation functionally are wrapped
Containing within the scope of the present invention.
It please join Fig. 1 to Fig. 6 and show the bump manufacturing method that the present invention is used for semiconductor packages, define X-axis first as a left side
Right direction, Z axis are up and down direction.Bump manufacturing method of the invention is applied to the encapsulation technology field in integrated circuit, system
The method of making comprises the steps of
Step 1: please join shown in Fig. 1, a substrate 1 is provided, the first metal layer 2 is set in the top of the substrate 1, in institute
The top setting second metal layer 3 of the first metal layer 2 is stated, the first metal layer 2 is titanium-tungsten layer, the second metal layer
3 be layers of copper.
Step 2: photoresist layer 4 is arranged in the second metal layer 3, patterns the photoresist layer 4 and form a rectangular aperture
5, the second metal layer 3 is revealed in the opening 5.
Step 3: please join shown in Fig. 2, copper bump 6 is set in the opening 5, the copper bump 6 is set to described second
On metal layer 3, the left and right sidewall of the copper bump 6 is close to the top of the photoresist layer 4 and the copper bump 6 in the up-down direction
Lower than the photoresist layer 4.
Step 4: please join shown in Fig. 3, by the reaming that opens a window make the copper bump 6 left and right sidewall and the photoresist layer 4 it
Between generate gap 7, the windowing reaming includes primary windowing reaming and secondary windowing reaming, and the primary windowing reaming uses baking
Roasting processing, the primary windowing reaming specifically include: in the baking oven with inert gas and the temperature of the baking oven 120~
40~60min is toasted under conditions of between 150 DEG C, in the present embodiment, the inert gas is nitrogen, preferred baking time
For 50min, in this way, the photoresist layer 4 gradually generates the gap 7 between shrinkage and the left and right sidewall of the copper bump 6, it is described
Primary windowing reaming makes the gap 7 reach the first width, and the range of first width is 3~5um, and the secondary windowing is expanded
Hole using plasma etching process, it is described it is secondary windowing reaming process are as follows: by plasma etching apparatus emit radio frequency and
It is passed through nitrogen and oxygen is etched, can also be passed through carbon tetrafluoride gas, the nitrogen, the oxygen and the tetrafluoro when necessary
The ratio for changing carbon is 1:10:2, in this way, 7 further expansion of the gap, the secondary windowing reaming makes the gap 7 reach the
Two width, the range of second width are 5~8um.
Step 5: please join shown in Fig. 4, further increase the gap 7 until reaching institute by etching the copper bump 6
The width needed specifically includes: described to be etched to chemical etching, the chemical etching fills the gap 7 using hydrogen peroxide medical fluid
The copper bump 6 is etched, makes the copper convex by etching period of the hydrogen peroxide medical fluid to the copper bump 6
The width in the lateral direction of block 6 reduces to increase the gap 7 to third width, and the range of the third width is 8~
The range of 12um, the etching period are 20~40min, can be controlled according to required size is etched to the copper bump 6
Etching period, the chemical etching also further etch the second metal layer 3 make the first metal layer 2 be revealed in it is described between
In gap 7, also, the side wall of the second metal layer 3 is total with the photoresist layer 4 and the copper bump 6 respectively in the up-down direction
Face.
Step 6: please join shown in Fig. 5, top electronickelling matter metal layer 8 and the filling gap 7 in the copper bump 6,
The i.e. described nickel matter metal layer 8 coats the top surface and side of the copper bump 6 completely, while coating the second metal layer 3 completely
Side wall.
Step 7: golden metal layer 9 is electroplated in the top of the nickel matter metal layer 8, the top surface of the golden metal layer 9 exists
It is lower than the photoresist layer 4 in up and down direction.
Step 8: please join shown in Fig. 6, the photoresist layer 4 and second metal positioned at 4 lower section of photoresist layer are removed
Layer 3 and the first metal layer 2 below the second metal layer 3 form complete projection cube structure.
In conclusion the bump manufacturing method for semiconductor packages of the invention, makes institute by way of the reaming that opens a window
The left and right sidewall and the photoresist layer 4 for stating copper bump 6 generate the gap 7, and pass through the practical hydrogen peroxide medical fluid of chemical etching
The copper bump 6 and the second metal layer 3 are further etched to increase the gap 7 to reach required width, then
Be electroplated the nickel matter metal layer 8 in the top of the copper bump 6 and fill the full gap 7 to coat the copper bump 6 and
The left and right sidewall of the second metal layer 3 reduces the oxidation of the left and right sidewall of the copper bump 6 and the second metal layer 3, phase
Compared with traditional secondary nickel plating, opens a window reaming and chemical etching can replace a nickel plating therein, and open a window reaming and chemistry
Etching not only simplifies operation, more significantly reduces production cost compared to nickel plating technology in technique.
The above examples are only used to illustrate the technical scheme of the present invention and are not limiting, although referring to preferred embodiment to this hair
It is bright to be described in detail, those skilled in the art should understand that, it can modify to technical solution of the present invention
Or equivalent replacement, without departing from the spirit and scope of the technical solution of the present invention.
Claims (10)
1. a kind of bump manufacturing method for semiconductor packages, which comprises the following steps:
A substrate is provided, the top of the substrate is equipped with the first metal layer and the second metal above the first metal layer
Layer；
Photoresist layer is set in the second metal layer, patterns the photoresist layer and forms opening；
Copper bump is set in the opening；
By opening a window, reaming makes to generate gap between the copper bump and the photoresist layer；
Further increase the gap until reaching required width by etching the copper bump；
Top electronickelling matter metal layer and the filling gap in the copper bump；
Golden metal layer is electroplated in the top of the nickel matter metal layer；
Remove the photoresist layer and the second metal layer and the first metal layer below the photoresist layer.
2. being used for the bump manufacturing method of semiconductor packages as described in claim 1, it is characterised in that: the windowing reaming packet
Primary windowing reaming and secondary windowing reaming are included, the primary windowing reaming is handled using baking, and the secondary windowing reaming is adopted
Use plasma etch process.
3. being used for the bump manufacturing method of semiconductor packages as claimed in claim 2, it is characterised in that: the primary windowing is expanded
Hole specifically includes: toasting in the baking oven with inert gas and under conditions of the temperature of the baking oven is between 120~150 DEG C
40~60min makes to generate the gap between the photoresist layer and the copper bump.
4. being used for the bump manufacturing method of semiconductor packages as claimed in claim 2, it is characterised in that: the inert gas is
Nitrogen.
5. being used for the bump manufacturing method of semiconductor packages as claimed in claim 2, it is characterised in that: the primary windowing is expanded
Hole makes the gap reach the first width, and the range of first width is 3~5um, the secondary windowing reaming make described between
Gap reaches the second width, and the range of second width is 5~8um.
6. being used for the bump manufacturing method of semiconductor packages as described in claim 1, it is characterised in that: by etching the copper
Convex block makes the gap increase further to that required width specifically includes: copper bump described in chemical etching makes the gap into one
Step is extended to third width, and the range of the third width is 8~12um.
7. being used for the bump manufacturing method of semiconductor packages as described in claim 1, it is characterised in that: described to be etched to chemistry
Etching, the chemical etching are filled the gap using hydrogen peroxide medical fluid and are etched to the copper bump.
8. being used for the bump manufacturing method of semiconductor packages as described in claim 1, it is characterised in that: the chemical etching
Time range is 20~40min.
9. as described in claim 1 be used for semiconductor packages bump manufacturing method, it is characterised in that: the chemical etching into
Second metal layer described in one step etching keeps the copper bump and the side wall of the second metal layer coplanar in above-below direction.
10. being used for the bump manufacturing method of semiconductor packages as described in claim 1, it is characterised in that: the golden metal
The top surface of layer is lower than the photoresist layer in the up-down direction.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910249907.4A CN109979834A (en) | 2019-03-29 | 2019-03-29 | Bump manufacturing method for semiconductor packages |
| PCT/CN2019/119956 WO2020199608A1 (en) | 2019-03-29 | 2019-11-21 | Bump manufacturing method for semiconductor packaging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910249907.4A CN109979834A (en) | 2019-03-29 | 2019-03-29 | Bump manufacturing method for semiconductor packages |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109979834A true CN109979834A (en) | 2019-07-05 |
Family
ID=67081680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910249907.4A Pending CN109979834A (en) | 2019-03-29 | 2019-03-29 | Bump manufacturing method for semiconductor packages |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109979834A (en) |
| WO (1) | WO2020199608A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110517960A (en) * | 2019-08-23 | 2019-11-29 | 江苏上达电子有限公司 | A kind of manufacturing method of COF substrate high intensity convex block |
| WO2020199608A1 (en) * | 2019-03-29 | 2020-10-08 | 颀中科技（苏州）有限公司 | Bump manufacturing method for semiconductor packaging |
| CN112687647A (en) * | 2020-12-28 | 2021-04-20 | 颀中科技（苏州）有限公司 | Flip chip structure and preparation method thereof |
| CN113725283A (en) * | 2021-11-04 | 2021-11-30 | 深圳市时代速信科技有限公司 | Semiconductor device and method for manufacturing the same |
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| TWM410659U (en) * | 2011-05-20 | 2011-09-01 | Chipbond Technology Corp | Bump structure |
| CN102931159A (en) * | 2012-11-08 | 2013-02-13 | 南通富士通微电子股份有限公司 | Semiconductor packaging structure |
| CN103165481A (en) * | 2011-12-13 | 2013-06-19 | 颀邦科技股份有限公司 | Bump manufacture technology and structure thereof |
| CN103165482A (en) * | 2011-12-13 | 2013-06-19 | 颀邦科技股份有限公司 | Bump technology |
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|---|---|---|---|---|
| TW531873B (en) * | 2001-06-12 | 2003-05-11 | Advanced Interconnect Tech Ltd | Barrier cap for under bump metal |
| US8492891B2 (en) * | 2010-04-22 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with electrolytic metal sidewall protection |
| CN202651096U (en) * | 2012-02-22 | 2013-01-02 | 颀邦科技股份有限公司 | Fine pitch projection structure |
| US9520375B2 (en) * | 2015-04-30 | 2016-12-13 | International Business Machines Corporation | Method of forming a solder bump on a substrate |
| CN109979834A (en) * | 2019-03-29 | 2019-07-05 | 颀中科技（苏州）有限公司 | Bump manufacturing method for semiconductor packages |
-
2019
- 2019-03-29 CN CN201910249907.4A patent/CN109979834A/en active Pending
- 2019-11-21 WO PCT/CN2019/119956 patent/WO2020199608A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWM410659U (en) * | 2011-05-20 | 2011-09-01 | Chipbond Technology Corp | Bump structure |
| CN103165481A (en) * | 2011-12-13 | 2013-06-19 | 颀邦科技股份有限公司 | Bump manufacture technology and structure thereof |
| CN103165482A (en) * | 2011-12-13 | 2013-06-19 | 颀邦科技股份有限公司 | Bump technology |
| CN102931159A (en) * | 2012-11-08 | 2013-02-13 | 南通富士通微电子股份有限公司 | Semiconductor packaging structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020199608A1 (en) * | 2019-03-29 | 2020-10-08 | 颀中科技（苏州）有限公司 | Bump manufacturing method for semiconductor packaging |
| CN110517960A (en) * | 2019-08-23 | 2019-11-29 | 江苏上达电子有限公司 | A kind of manufacturing method of COF substrate high intensity convex block |
| CN112687647A (en) * | 2020-12-28 | 2021-04-20 | 颀中科技（苏州）有限公司 | Flip chip structure and preparation method thereof |
| CN113725283A (en) * | 2021-11-04 | 2021-11-30 | 深圳市时代速信科技有限公司 | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020199608A1 (en) | 2020-10-08 |
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Application publication date: 20190705 |
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