CN113725283A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113725283A CN113725283A CN202111297050.7A CN202111297050A CN113725283A CN 113725283 A CN113725283 A CN 113725283A CN 202111297050 A CN202111297050 A CN 202111297050A CN 113725283 A CN113725283 A CN 113725283A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
Abstract
A semiconductor device and a preparation method thereof relate to the technical field of semiconductors. The preparation method comprises the following steps: forming a semiconductor stack on a substrate; forming a source ohmic metal and a drain ohmic metal on the semiconductor stack; forming a seed metal layer covering the source ohmic metal and the drain ohmic metal on the semiconductor stack; forming a photoresist layer on the seed metal layer, and forming a first window on the photoresist layer; depositing an Au layer in the first window; baking the photoresist layer to shrink the photoresist layer so as to form a gap between the Au layer and the photoresist layer; forming a metal barrier layer on the gap and the Au layer; removing the photoresist layer and the exposed seed metal layer; forming source electrode interconnection metal and drain electrode interconnection metal on the source electrode ohmic metal and the drain electrode ohmic metal respectively and forming a source field plate on the metal barrier layer; a dielectric layer is formed between the source field plate and the metal barrier layer. The preparation method can avoid the diffusion of Au to the inside of the dielectric layer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
The GaN-based HEMT device is used as a third-generation semiconductor device, has higher frequency, higher working temperature, higher breakdown voltage and higher power, and has wide application prospect in the military and civil fields of high-frequency, high-voltage, high-temperature and high-power devices.
For a GaN-based HEMT device, the gate metal is formed by electron beam evaporation, lift-off process, which is in schottky contact with the semiconductor layer. The composition of the gate metal is a stack of a Ni layer and an Au layer. Since the dielectric layer between the gate metal and the source field plate is thin (usually, the thickness of the dielectric layer is between 100nm and 400 nm), a strong electric field exists between the gate metal and the source field plate, and Au in the gate metal migrates into the dielectric layer in the strong electric field, which causes the increase of gate-source leakage and even gate-source breakdown in severe cases. Therefore, how to effectively avoid the diffusion of Au into the dielectric layer becomes a technical problem to be solved at present.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, which can effectively avoid the diffusion of Au to the inside of a dielectric layer and improve the stability of the device.
The embodiment of the invention is realized by the following steps:
in one aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a semiconductor stack on a substrate; forming spaced source and drain ohmic metals on the semiconductor stack; forming a seed metal layer covering the source ohmic metal and the drain ohmic metal on the semiconductor stack; forming a photoresist layer on the seed metal layer, and forming a first window on the photoresist layer, wherein the first window is positioned between the source electrode ohmic metal and the drain electrode ohmic metal; depositing an Au layer in the first window; baking the photoresist layer to shrink the photoresist layer to form a gap between the Au layer and the photoresist layer; forming a metal barrier layer on the gap and the Au layer; respectively removing the photoresist layer and the exposed seed metal layer; forming a source interconnection metal on the source ohmic metal, a drain interconnection metal on the drain ohmic metal, and a source field plate on the metal barrier layer; and a dielectric layer is formed between the source field plate and the metal barrier layer. The preparation method of the semiconductor device can effectively avoid the diffusion of Au to the inside of the dielectric layer and improve the stability of the device.
Optionally, forming a seed metal layer overlying the source ohmic metal and the drain ohmic metal on the semiconductor stack, comprising: forming a passivation layer covering the source ohmic metal and the drain ohmic metal on the semiconductor stack; etching the passivation layer to form a gate trench exposing the semiconductor stack on the passivation layer; and depositing a seed metal layer covering the gate groove on the passivation layer.
Optionally, baking the photoresist layer to shrink the photoresist layer to form a gap between the Au layer and the photoresist layer, comprising: baking the photoresist layer to shrink the photoresist layer under the conditions that the baking temperature is between 120 ℃ and 150 ℃ and the baking time is between 5min and 10min, so as to form a gap between the Au layer and the photoresist layer.
Optionally, the width of the gap is greater than or equal to the thickness of the metal barrier layer.
Optionally, forming a source interconnect metal on the source ohmic metal, a drain interconnect metal on the drain ohmic metal, and a source field plate on the metal barrier layer; wherein, be formed with the dielectric layer between source field board and the metal barrier layer, include: forming a dielectric layer on the exposed passivation layer, wherein the dielectric layer covers the metal barrier layer; sequentially etching the dielectric layer and the passivation layer to form a second window exposing the ohmic metal of the source electrode and a third window exposing the ohmic metal of the drain electrode; and respectively forming source electrode interconnection metal in the second window, forming drain electrode interconnection metal in the third window, and forming a source field plate at the position of the dielectric layer corresponding to the metal barrier layer.
Optionally, the dielectric layer and the passivation layer are both made of SiN.
Optionally, the source interconnection metal, the drain interconnection metal and the source field plate are all laminated metals, and the laminated metals include a Ti layer and an Au layer formed in sequence.
Optionally, forming a metal barrier layer on the slot and the Au layer, including: and forming a metal barrier layer on the gap and the Au layer by adopting a pulse plating process.
Optionally, the material of the metal barrier layer is any one of Pd, W, or TiW.
In another aspect of the present invention, a semiconductor device is provided, which includes a substrate, a semiconductor stack formed on the substrate, a source ohmic metal and a drain ohmic metal spaced apart from each other on the semiconductor stack, a source interconnection metal on the source ohmic metal, a drain interconnection metal on the drain ohmic metal, and a gate metal between the source interconnection metal and the drain interconnection metal; the grid metal comprises a seed metal layer which is in contact with the semiconductor laminated layer and an Au layer which is positioned on the seed metal layer, the semiconductor device further comprises a metal blocking layer which coats the outer peripheral wall of the Au layer, a dielectric layer which is positioned on the metal blocking layer, and a source field plate which is positioned on the dielectric layer.
The beneficial effects of the invention include:
the preparation method of the semiconductor device comprises the steps of forming a semiconductor laminated layer on a substrate; forming spaced source and drain ohmic metals on the semiconductor stack; forming a seed metal layer covering the source ohmic metal and the drain ohmic metal on the semiconductor stack; forming a photoresist layer on the seed metal layer, and forming a first window on the photoresist layer, wherein the first window is positioned between the source electrode ohmic metal and the drain electrode ohmic metal; depositing an Au layer in the first window; baking the photoresist layer to shrink the photoresist layer to form a gap between the Au layer and the photoresist layer; forming a metal barrier layer on the gap and the Au layer; respectively removing the photoresist layer and the exposed seed metal layer; forming a source interconnection metal on the source ohmic metal, a drain interconnection metal on the drain ohmic metal, and a source field plate on the metal barrier layer; and a dielectric layer is formed between the source field plate and the metal barrier layer. This application is through toasting the photoresist layer to make the photoresist layer shrink with and form the gap between the Au layer of grid metal, and form the metal barrier layer at the upper surface of this gap and Au, thereby carry out all-round protection to the Au layer through the metal barrier layer, in order to avoid Au to the inside diffusion of dielectric layer, and then improve the stability of device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is one of flow diagrams illustrating a method for fabricating a semiconductor device according to some embodiments of the present invention;
fig. 2 is a second schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present invention;
fig. 3 is a third schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present invention;
fig. 4 is a schematic view of a semiconductor device according to some embodiments of the present invention;
fig. 5 is a second schematic view illustrating a manufacturing process of a semiconductor device according to some embodiments of the present invention;
fig. 6 is a third schematic view illustrating a manufacturing process of a semiconductor device according to some embodiments of the present invention;
fig. 7 is a fourth schematic view illustrating a process for manufacturing a semiconductor device according to some embodiments of the present invention;
fig. 8 is a fifth schematic view illustrating a fabrication process of a semiconductor device according to some embodiments of the present invention;
fig. 9 is a sixth schematic view of a semiconductor device according to some embodiments of the present invention;
fig. 10 is a seventh schematic view illustrating a process for manufacturing a semiconductor device according to some embodiments of the present invention;
fig. 11 is an eighth schematic view illustrating a process for manufacturing a semiconductor device according to some embodiments of the present invention;
fig. 12 is a ninth schematic view illustrating a process for manufacturing a semiconductor device according to some embodiments of the present invention;
fig. 13 is a tenth schematic diagram illustrating a process for fabricating a semiconductor device according to some embodiments of the present invention;
fig. 14 is an eleventh schematic view of a semiconductor device according to some embodiments of the present invention.
Icon: 10-a substrate; 20-a semiconductor stack; 31-source ohmic metal; 32-drain ohmic metal; 40-gate metal; 41-seed metal layer; a 42-Au layer; 50-a photoresist layer; 51-a first window; 60-a gap; b-the width of the gap; 70-a metal barrier layer; 81-source interconnect metal; 82-drain interconnect metal; 90-a source field plate; 91-a dielectric layer; 92-a passivation layer; 921-grid groove.
Detailed Description
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the invention and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending" onto "another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending over" another element, it can be directly on or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Relative terms such as "below …" or "above …" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to fig. 1, the present embodiment provides a method for manufacturing a semiconductor device, including:
s100, a semiconductor stack 20 is formed on the substrate 10.
Referring to fig. 4, a semiconductor stack 20 is formed on a substrate 10. Illustratively, the semiconductor stack 20 may be deposited by metal organic chemical vapor deposition on the substrate 10. The semiconductor stack 20 may include a nucleation layer, a buffer layer, a channel layer, and a barrier layer, which are sequentially formed on the substrate 10. Specifically, the materials of the substrate 10 and the semiconductor stacked layer 20 may be selected by those skilled in the art, and the present application is not limited thereto.
S200, forming a source ohmic metal 31 and a drain ohmic metal 32 on the stacked semiconductor layer 20 at intervals, as shown in fig. 5.
Step S200 may be performed by performing electron beam evaporation to entirely evaporate metal on the semiconductor stacked layer 20, and then removing metal in the remaining region by peeling, and leaving the source ohmic metal 31 in the source region and the drain ohmic metal 32 in the drain region; then, the source ohmic metal 31 and the drain ohmic metal 32 are alloyed by performing a high temperature heat treatment (typically, a temperature greater than 500 ℃) to form ohmic contacts with the underlying semiconductor stack 20.
Illustratively, the source ohmic metal 31 and the drain ohmic metal 32 may be stacked materials, for example, Ti layer/Al layer/Ni layer/Au layer 42 may be sequentially stacked.
And S300, forming a seed metal layer 41 covering the source ohmic metal 31 and the drain ohmic metal 32 on the semiconductor stacked layer 20.
The seed metal layer 41 is a bottom metal layer of the gate metal 40. Typically, the gate metal 40 includes a seed metal layer 41 and an Au layer 42 on the seed metal layer 41.
For example, in the present embodiment, referring to fig. 2, the step S300 of forming the seed metal layer 41 covering the source ohmic metal 31 and the drain ohmic metal 32 on the semiconductor stacked layer 20 specifically includes the following steps:
and S310, forming a passivation layer 92 covering the source ohmic metal 31 and the drain ohmic metal 32 on the semiconductor stacked layer 20.
In this step, the passivation layer 92 is formed on the semiconductor stack 20 in a whole layer, and the passivation layer 92 covers the source ohmic metal 31 and the drain ohmic metal 32. The passivation layer 92 may be formed by plasma vapor deposition.
S320, the passivation layer 92 is etched to form a gate trench 921 exposing the semiconductor stacked layer 20 on the passivation layer 92, as shown in fig. 6.
The passivation layer 92 is etched to form the gate groove 921, which may be implemented by a dry etching process.
And S330, depositing a seed metal layer 41 covering the gate groove 921 on the passivation layer 92, as shown in FIG. 7.
At this time, the seed metal layer 41 will cover the passivation layer 92 and the exposed semiconductor stack 20 (i.e., the region where the gate groove 921 is located). The seed metal layer 41 will serve as the underlying metal for the gate metal 40. Illustratively, the seed metal layer 41 may be a Ni layer.
S400, forming a photoresist layer 50 on the seed metal layer 41, and forming a first window 51 on the photoresist layer 50, wherein the first window 51 is located between the source ohmic metal 31 and the drain ohmic metal 32, as shown in fig. 8.
The first window 51 may be formed by exposing and developing the photoresist layer 50, and the technical means is well known to those skilled in the art, so that the detailed description thereof is omitted.
S500, depositing the Au layer 42 in the first window 51, as shown in fig. 9.
The deposition of the Au layer 42 may be formed by depositing an Au material by electrodeposition in the first window 51. In this embodiment, it should be noted that the seed metal layer 41 and the Au layer 42 together form the gate metal 40 of the semiconductor device.
S600, baking the photoresist layer 50 to shrink the photoresist layer 50 to form a gap 60 between the Au layer 42 and the photoresist layer 50, as shown in fig. 10.
Since the photoresist layer 50 can be shrunk by baking the photoresist layer 50 at a suitable temperature and time according to the characteristics of the photoresist layer 50, the gap 60 is formed between the Au layer 42 and the photoresist layer 50 in step S600, so as to facilitate the subsequent preparation of the metal barrier layer 70 in the gap 60.
The temperature and time for baking the photoresist layer 50 should be reasonably selected, and too high baking temperature and too long baking time can cause the photoresist layer 50 to be denatured and cannot be removed cleanly; too low a baking temperature and too short a baking time will result in insufficient shrinkage of the photoresist layer 50 and too small a gap 60 between the Au layer 42 and the photoresist layer 50. In this embodiment, optionally, the step S600 of baking the photoresist layer 50 to shrink the photoresist layer 50 so as to form the gap 60 between the Au layer 42 and the photoresist layer 50 may be implemented by:
the photoresist layer 50 is baked under conditions of a baking temperature between 120 ℃ and 150 ℃ and a baking time between 5min and 10min to shrink the photoresist layer 50 to form a gap 60 between the Au layer 42 and the photoresist layer 50.
Illustratively, the baking temperature may be 120 ℃, 130 ℃, 140 ℃, 150 ℃, or the like. The baking time can be 5min, 6min, 8min, 10min and the like, which are not listed in the application.
S700, a metal barrier layer 70 is formed on the slit 60 and the Au layer 42, as shown in fig. 11.
That is, as shown in fig. 11, the metal barrier layer 70 is attached to the gap 60 between the Au layer 42 and the photoresist layer 50 and the upper surface of the Au layer 42, so that the metal barrier layer 70 completely covers the Au layer 42, thereby preventing Au in the Au layer 42 from migrating toward the source field plates 90. The material of the metal barrier layer 70 is a material capable of blocking Au migration, and the material of the metal barrier layer 70 is, for example, any one of Pd, W, and TiW.
In this embodiment, the width B of the gap formed in step S600 is greater than or equal to the thickness of the metal barrier layer 70. That is, the metal barrier layer 70 may fill the entire gap 60 or may fill a portion of the gap 60. For ease of fabrication, in this embodiment, the width B of the gap may be selected to be equal to the thickness of the metallic barrier layer 70.
Also, in the present embodiment, the thickness of the portion of the metal barrier layer 70 located on the sidewall of the Au layer 42 and the portion located on the upper surface of the Au layer 42 should be uniform, so that the metal barrier layer 70 is uniform.
In addition, optionally, the step S700 of forming the metal barrier layer 70 on the slit 60 and the Au layer 42 includes:
a metal barrier layer 70 is formed on the slit 60 and the Au layer 42 using a pulse plating process.
The pulse plating method can improve the thickness uniformity of the metal barrier layer 70 on the surface of the gate metal 40. Alternatively, the duty cycle of the pulse current used for pulse plating may be between 0.1% and 20%.
And S800, respectively removing the photoresist layer 50 and the exposed seed metal layer 41, as shown in FIG. 12.
The specific manner of removing the photoresist layer 50 and the exposed seed metal layer 41 is not limited in this application, and dry etching or wet etching may be used, and those skilled in the art may select the method according to actual requirements.
S900, forming a source interconnect metal 81 on the source ohmic metal 31, a drain interconnect metal 82 on the drain ohmic metal 32, and a source field plate 90 on the metal barrier layer 70; wherein a dielectric layer 91 is formed between the source field plate 90 and the metal barrier layer 70.
Referring to fig. 14, a dielectric layer 91 is disposed between the source field plate 90 and the metal barrier layer 70. Alternatively, the dielectric layer 91 and the passivation layer 92 may be both made of SiN.
Also, the source interconnection metal 81, the drain interconnection metal 82, and the source field plate 90 may be all stacked metals, and the stacked metals include the Ti layer and the Au layer 42 formed in this order.
In the present embodiment, please refer to fig. 3, which illustrates that, in the step S900, the source interconnection metal 81 is formed on the source ohmic metal 31, the drain interconnection metal 82 is formed on the drain ohmic metal 32, and the source field plate 90 is formed on the metal barrier layer 70; wherein, a dielectric layer 91 is formed between the source field plate 90 and the metal barrier layer 70, which specifically comprises the following steps:
and S910, forming a dielectric layer 91 on the exposed passivation layer 92, wherein the dielectric layer 91 covers the metal barrier layer 70.
That is, on the basis of fig. 12, a dielectric layer 91 is formed entirely on the device upper surface, and at this time, the dielectric layer 91 covers the exposed passivation layer 92 and the exposed gate metal 40 (including the sidewalls of the metal barrier layer 70 and the exposed seed metal layer 41). The process for forming the dielectric layer 91 may be a plasma vapor deposition process.
S920, the dielectric layer 91 and the passivation layer 92 are sequentially etched to form a second window exposing the source ohmic metal 31 and a third window exposing the drain ohmic metal 32, as shown in fig. 13.
The sizes of the second window and the third window are determined according to the sizes of the source interconnection metal 81 and the drain interconnection metal 82 which need to be formed subsequently, and the application is not limited.
S930, forming a source interconnection metal 81 in the second window, a drain interconnection metal 82 in the third window, and forming a source field plate 90 on the dielectric layer 91 corresponding to the metal barrier layer 70, respectively.
It should be noted that the source interconnection metal 81 and the drain interconnection metal 82 may be prepared together with the source field plate 90, or may be prepared separately (i.e., the source interconnection metal 81 and the drain interconnection metal 82 are prepared at one time, and the source field plate 90 is prepared at another time), which is not limited in this application.
In summary, the present application provides a method for manufacturing a semiconductor device, which includes forming a semiconductor stack 20 on a substrate 10; forming spaced source ohmic metal 31 and drain ohmic metal 32 on the semiconductor stack 20; forming a seed metal layer 41 covering the source ohmic metal 31 and the drain ohmic metal 32 on the semiconductor stack 20; forming a photoresist layer 50 on the seed metal layer 41, and forming a first window 51 on the photoresist layer 50, the first window 51 being located between the source ohmic metal 31 and the drain ohmic metal 32; depositing a Au layer 42 within the first window 51; baking the photoresist layer 50 to shrink the photoresist layer 50 to form a gap 60 between the Au layer 42 and the photoresist layer 50; forming a metal barrier layer 70 on the slit 60 and the Au layer 42; respectively removing the photoresist layer 50 and the exposed seed metal layer 41; forming a source interconnect metal 81 on the source ohmic metal 31, a drain interconnect metal 82 on the drain ohmic metal 32, and a source field plate 90 on the metal barrier layer 70; wherein a dielectric layer 91 is formed between the source field plate 90 and the metal barrier layer 70. This application is through toasting photoresist layer 50 to make photoresist layer 50 shrink with the Au layer 42 of grid metal 40 between form gap 60, and form metal barrier layer 70 at the upper surface of this gap 60 and Au, thereby carry out all-round protection to Au layer 42 through metal barrier layer 70, in order to avoid Au to the inside diffusion of dielectric layer 91, and then improve the stability of device.
In another aspect of the present invention, a semiconductor device is provided, which includes a substrate 10, a semiconductor stack 20 formed on the substrate 10, a source ohmic metal 31 and a drain ohmic metal 32 disposed on the semiconductor stack 20 at an interval, a source interconnection metal 81 disposed on the source ohmic metal 31, a drain interconnection metal 82 disposed on the drain ohmic metal 32, and a gate metal 40 disposed between the source interconnection metal 81 and the drain interconnection metal 82; the gate metal 40 includes a seed metal layer 41 in contact with the semiconductor stack 20 and an Au layer 42 on the seed metal layer 41, the semiconductor device further includes a metal barrier layer 70 covering a peripheral wall of the Au layer 42, a dielectric layer 91 on the metal barrier layer 70, and a source field plate 90 on the dielectric layer 91.
The material or thickness of the metal barrier layer 70 and other layers is the same as that provided in the above embodiments of the semiconductor device, and the material of the metal barrier layer 70 is any one of Pd, W, or TiW.
Also, the semiconductor device further includes a passivation layer 92, as shown in fig. 14, the passivation layer 92 is located on the semiconductor stacked layer 20, the source interconnection metal 81 and the source ohmic metal 31 are in contact with the semiconductor stacked layer 20 through the passivation layer 92, the drain interconnection metal 82 and the drain ohmic metal 32 are also in contact with the semiconductor stacked layer 20 through the passivation layer 92 in sequence, and the seed metal layer 41 is also in contact with the semiconductor stacked layer 20 through the passivation layer 92.
It should be noted that the semiconductor device has the same structure as the semiconductor device manufactured by the method for manufacturing a semiconductor device provided above. Since the specific structure of the manufactured semiconductor device can be derived without any doubt by the above manufacturing method of the semiconductor device, the description of the present application is not repeated.
The above description is only an alternative embodiment of the present invention and is not intended to limit the present invention, and various modifications and variations of the present invention may occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
forming a semiconductor stack on a substrate;
forming spaced source and drain ohmic metals on the semiconductor stack;
forming a seed metal layer covering the source ohmic metal and the drain ohmic metal on the semiconductor stack;
forming a photoresist layer on the seed metal layer, and forming a first window on the photoresist layer, wherein the first window is positioned between the source ohmic metal and the drain ohmic metal;
depositing an Au layer in the first window;
baking the photoresist layer to shrink the photoresist layer to form a gap between the Au layer and the photoresist layer;
forming a metal barrier layer on the gap and the Au layer;
respectively removing the photoresist layer and the exposed seed metal layer;
forming a source interconnect metal on the source ohmic metal, a drain interconnect metal on the drain ohmic metal, and a source field plate on the metal barrier layer; and a dielectric layer is formed between the source field plate and the metal barrier layer.
2. The method of manufacturing a semiconductor device according to claim 1, wherein forming a seed metal layer covering the source ohmic metal and the drain ohmic metal on the semiconductor stack comprises:
forming a passivation layer covering the source ohmic metal and the drain ohmic metal on the semiconductor stacked layer;
etching the passivation layer to form a gate groove exposing the semiconductor lamination layer on the passivation layer;
and depositing a seed metal layer covering the gate groove on the passivation layer.
3. The method of manufacturing a semiconductor device according to claim 1, wherein baking the photoresist layer to shrink the photoresist layer to form a gap between the Au layer and the photoresist layer comprises:
baking the photoresist layer to shrink the photoresist layer under the conditions that the baking temperature is between 120 ℃ and 150 ℃ and the baking time is between 5min and 10min, so as to form a gap between the Au layer and the photoresist layer.
4. The method according to claim 1, wherein a width of the gap is greater than or equal to a thickness of the metal barrier layer.
5. The method of manufacturing a semiconductor device according to claim 2, wherein a source interconnect metal is formed on the source ohmic metal, a drain interconnect metal is formed on the drain ohmic metal, and a source field plate is formed on the metal barrier layer; wherein, a dielectric layer is formed between the source field plate and the metal barrier layer, and the dielectric layer comprises:
forming a dielectric layer on the exposed passivation layer, wherein the dielectric layer covers the metal barrier layer;
sequentially etching the dielectric layer and the passivation layer to form a second window exposing the ohmic metal of the source electrode and a third window exposing the ohmic metal of the drain electrode;
and respectively forming source electrode interconnection metal in the second window, forming drain electrode interconnection metal in the third window, and forming a source field plate at the position of the dielectric layer corresponding to the metal barrier layer.
6. The method of claim 5, wherein the dielectric layer and the passivation layer are both made of SiN.
7. The method according to claim 5, wherein the source interconnection metal, the drain interconnection metal, and the source field plate are laminated metals, and the laminated metals include a Ti layer and an Au layer formed in this order.
8. The method of manufacturing a semiconductor device according to claim 1, wherein the forming a metal barrier layer on the slit and the Au layer comprises:
and forming a metal barrier layer on the gap and the Au layer by adopting a pulse plating process.
9. The method of any one of claims 1 to 8, wherein the metal barrier layer is made of any one of Pd, W and TiW.
10. A semiconductor device is characterized by comprising a substrate, a semiconductor lamination layer formed on the substrate, a source ohmic metal and a drain ohmic metal which are arranged on the semiconductor lamination layer at intervals, a source interconnection metal positioned on the source ohmic metal, a drain interconnection metal positioned on the drain ohmic metal, and a gate metal positioned between the source interconnection metal and the drain interconnection metal; the grid metal comprises a seed metal layer in contact with the semiconductor laminated layer and an Au layer positioned on the seed metal layer, the semiconductor device further comprises a metal blocking layer wrapping the outer peripheral wall of the Au layer, a dielectric layer positioned on the metal blocking layer, and a source field plate positioned on the dielectric layer.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101894767A (en) * | 2009-05-20 | 2010-11-24 | 日月光半导体制造股份有限公司 | Manufacturing method of bump bottom metal layer |
| US20130256755A1 (en) * | 2012-03-28 | 2013-10-03 | Sumitomo Electric Device Innovations, Inc. | Semiconductor device and method for manufacturing the same |
| US20140001640A1 (en) * | 2012-06-29 | 2014-01-02 | Sumitomo Electric Device Innovations, Inc. | Method for fabricating semiconductor device and semiconductor device |
| CN109979834A (en) * | 2019-03-29 | 2019-07-05 | 颀中科技（苏州）有限公司 | Bump manufacturing method for semiconductor packages |
-
2021
- 2021-11-04 CN CN202111297050.7A patent/CN113725283A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101894767A (en) * | 2009-05-20 | 2010-11-24 | 日月光半导体制造股份有限公司 | Manufacturing method of bump bottom metal layer |
| US20130256755A1 (en) * | 2012-03-28 | 2013-10-03 | Sumitomo Electric Device Innovations, Inc. | Semiconductor device and method for manufacturing the same |
| US20140001640A1 (en) * | 2012-06-29 | 2014-01-02 | Sumitomo Electric Device Innovations, Inc. | Method for fabricating semiconductor device and semiconductor device |
| CN109979834A (en) * | 2019-03-29 | 2019-07-05 | 颀中科技（苏州）有限公司 | Bump manufacturing method for semiconductor packages |
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