CN107342273B - Filling method for through silicon via of wafer - Google Patents
Filling method for through silicon via of wafer Download PDFInfo
- Publication number
- CN107342273B CN107342273B CN201710495773.5A CN201710495773A CN107342273B CN 107342273 B CN107342273 B CN 107342273B CN 201710495773 A CN201710495773 A CN 201710495773A CN 107342273 B CN107342273 B CN 107342273B
- Authority
- CN
- China
- Prior art keywords
- wafer
- silicon via
- current value
- silicon
- electroplating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The invention discloses a filling method of a wafer silicon through hole, which comprises the following steps: carrying out first electroplating treatment on the wafer through silicon via according to first parameters to fill the wafer through silicon via, wherein the first parameters comprise at least one first current value; and carrying out first electroplating treatment on the wafer through silicon via according to a second parameter so as to supplement and fill the wafer through silicon via, wherein the second parameter comprises at least one second current value, and at least one part of the second current value is larger than the first current value. The method realizes the final complete filling of the TSV which is not completely filled, reduces the material loss and reduces the process cost.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a filling method of a wafer silicon through hole.
Background
With the continuous progress of microelectronic technology, the feature size of integrated circuits is continuously reduced, and the interconnection density is continuously improved; meanwhile, the requirements of users on high performance and low power consumption are continuously improved. The Through Silicon Via (TSV) process has the advantages of large stacking density in the three-dimensional direction, small outline size after packaging, low power consumption and the like, is widely considered as a fourth generation packaging technology after bonding, tape carrier bonding and flip chip, and gradually becomes a mainstream technology in the field of high-density packaging, and the TSV electro-coppering filling technology is an important part in the TSV process.
The process menu of the electroplating current in the electroplating complete filling process is adjusted in the early stage as shown in table 1:
TABLE 1 electroplating Current Process Menu when electroplating is completely filled
| Current value/A | Plating time/min |
| 0.245 | 6 |
| 0.309 | 6 |
| 0.376 | 6 |
| 0.504 | 6 |
| 0.636 | 6 |
| 0.768 | 6 |
| 0.896 | 6 |
| 1.027 | 6 |
| 1.158 | 6 |
| 1.287 | 6 |
| 1.419 | 6 |
| 1.549 | 6 |
And respectively detecting the center, the middle and the edge of the wafer by X-Ray, wherein the detection results are shown in fig. 2A, 2B and 2C, the TSV at the center, the middle and the edge of the wafer has no hole, the filling is completed, and the TSV wafer is filled with the electroplated copper. The optical profilometer measures the copper protrusion at the top of the TSV to obtain detection results as shown in figures 3A, 3B and 3C, wherein the X axis represents the coordinate along a certain direction of the plane of the TSV, the Y axis is the coordinate perpendicular to the direction of the X axis, the protrusion at the top of the TSV is 0.8-0.9um at the center of the wafer, the protrusion at the top of the TSV is 0.8-1.0um at the middle of the wafer, and the protrusion at the top of the TSV is 0.9-1.1um at the edge of the wafer. From the above, the TSV has been completely filled from the bottom up. Meanwhile, four-point probe measurement is carried out on the copper thickness of the surface of the wafer, the measurement chart is shown in figure 4, the average value of the thickness of the electroplated copper on the surface of the wafer is 3.44um, and the uniformity is 1.98%.
In the TSV copper electroplating filling process step, due to the fact that process debugging is required in the early stage for TSV copper electroplating filling with different opening rates and sizes, an optimal process menu is determined, and before the optimal effect is achieved, TSV which is not completely filled in the debugging process is often generated; meanwhile, in the automatic running process of the TSV copper electroplating process, only a part of Down machines are electroplated during TSV electroplating possibly caused by external or artificial factors, and the TSV wafer under the condition needs to be processed.
In the prior art, the treatment mode of incomplete filling TSV is direct scrapping treatment or a process menu which is not completely plated is used for supplementing plating, the soaking time in electroplating solution is prolonged, the electroplating solution is subjected to acid etching on a copper oxide layer, and then electroplating is carried out, but the effect is poor. Because the TSV aiming at the situation does not have a better treatment mode, the TSV is always treated as a scrap piece finally, and the process cost is increased.
Disclosure of Invention
The invention aims to solve the technical problem of realizing complete filling of incompletely filled through silicon vias.
Therefore, the embodiment of the invention provides a wafer through silicon via filling method, which comprises the following steps: carrying out first electroplating treatment on the wafer through silicon via according to first parameters to fill the wafer through silicon via, wherein the first parameters comprise at least one first current value; and carrying out secondary electroplating treatment on the wafer through silicon via according to a second parameter so as to supplement and fill the wafer through silicon via, wherein the second parameter comprises at least one second current value, and at least one part of the second current value is larger than the first current value.
Preferably, the first current value and the second current value are each plural, have a predetermined order, and gradually increase in order, wherein a minimum value of the second current values is equal to a minimum value of the first current values.
Preferably, the second smallest value of the second current values is equal to the largest value of the first current values.
Preferably, the first parameter further includes a first plating duration corresponding to the first current value, and the second parameter further includes a second plating duration corresponding to the second current value.
Preferably, after the first electroplating process is performed on the through-silicon-via according to the first parameter, and before the second electroplating process is performed on the through-silicon-via according to the second parameter, the method further includes: and processing the through silicon via of the wafer by using etching liquid.
Preferably, the processing the wafer through-silicon-via using a copper oxide etching liquid comprises: and etching the through silicon via for a preset time by using a mixed solution of hydrogen peroxide and sulfuric acid at a preset rotating speed.
Preferably, the predetermined rotation speed is 30RPM and the predetermined time is 20 s.
Preferably, the etch thickness is in the range of 10nm to 100 nm.
According to the filling method of the wafer through silicon via, the wafer through silicon via is firstly subjected to primary electroplating treatment by using a small current value, and the through silicon via is not completely filled at the moment.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flowchart illustrating an exemplary method for filling through-silicon-vias in a wafer according to an embodiment of the present invention;
fig. 2A is a result diagram of X-Ray filling detecting of the center of the wafer after filling according to the debugged process flow in the background art.
Fig. 2B is a result diagram of X-Ray filling of the middle of the wafer after filling according to the debugged process flow in the background art.
Fig. 2C is a result diagram of X-Ray filling detecting of the wafer edge after filling according to the debugged process flow in the background art.
FIG. 3A is a diagram of the results of an optical profiler detecting the center of a wafer after filling according to a debugged process flow in the background art;
FIG. 3B is a diagram of the results of the optical profiler detecting the middle of a wafer after filling according to a debugged process flow in the background art;
FIG. 3C is a diagram of the results of the optical profiler detecting the edge of the wafer after filling according to the debugged process flow in the background art;
FIG. 4 is a diagram showing the results of four-point probe detection in the background art;
FIG. 5A is a diagram illustrating the results of an X-Ray detection of the center of a wafer for abort in an embodiment of the present invention;
FIG. 5B is a diagram illustrating the results of an abort X-Ray inspection of a wafer in accordance with an embodiment of the present invention;
FIG. 5C is a graph of the results of an X-Ray detection of wafer edges for abort in an embodiment of the present invention;
FIG. 6A is a diagram illustrating the results of detecting the wafer center by X-Ray after the post-plating process in accordance with an embodiment of the present invention;
FIG. 6B is a graph showing the middle result of the X-Ray detection of the wafer after the post-plating in the embodiment of the present invention;
FIG. 6C is a graph showing the results of detecting the edge of the wafer by X-Ray after the deposition process in the embodiment of the present invention;
FIG. 7A is a diagram illustrating the result of detecting the center of the wafer by the optical profiler after the post plating process in the embodiment of the present invention;
FIG. 7B is a diagram illustrating the middle result of the optical profiler after the post-plating inspection of the wafer in the embodiment of the present invention;
FIG. 7C is a graph of the result of detecting the edge of the wafer by the optical profiler after the post plating in the embodiment of the present invention;
FIG. 8 is a diagram showing the results of four-point probe detection after the replating in the embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The present embodiment provides a method for filling through silicon vias in a wafer, which may be performed by an electroplating apparatus, as shown in fig. 1, and includes the following steps:
s10: and carrying out first electroplating treatment on the wafer through silicon via according to a first parameter to fill the wafer through silicon via, wherein the first parameter comprises at least one first current value.
In the through silicon via electroplating filling process step, because the through silicon vias with different opening rates and sizes need to be subjected to process debugging in the early stage, the electroplating parameters, namely the electroplating current menu, are determined, and the electroplating current menu comprises one or more current values. The metal to be filled by electroplating is copper, gold, tungsten and other metals, and the filling is generally carried out by electroplating copper.
In this embodiment, 10x100um TSV with a diameter of 10um and a depth of 100um is selected and platedThe aperture ratio is about 0.19%, and the manufacturing flow of the electroplated TSV wafer is as follows: providing a wafer, and cleaning and drying the surface of the wafer by using an SC1 solution; coating photoresist AZ4620, exposing and developing; etching 10x100um TSV; removing the photoresist and cleaning; plasma Enhanced Chemical Vapor Deposition (PECVD) method for preparing SiO2A surface thickness of about 2 um; PVD (physical Vapor deposition) physical Vapor deposition produces Ti/Cu (adhesion layer/seed layer), the surface thickness of which is about 500nm/1500nm, and an electroplating copper filling process is adopted.
In this embodiment, the electroplating process is shown in table 2, which is equivalent to that the electroplating apparatus performs the first electroplating according to the process menu shown in table 2, and the sequence of rows in table 2 is the sequence of parameters adopted by the electroplating apparatus for the TSV.
TABLE 2 electroplating Current Process Menu when electroplating is not completely filled
After the processing of step S10, the results shown in fig. 5A, 5B, and 5C are obtained by X-Ray detection, as shown in the figure, the TSVs in the center of the wafer, the middle of the wafer, and the edge of the wafer are not completely filled, and the filling degree is about half from the bottom to the top.
There are various reasons for incomplete filling, for example, before the prior debugging fails to achieve the better effect, through silicon vias which are not completely filled in the debugging process are often generated; meanwhile, in the automatic running process of the through silicon via copper electroplating process, only a part of through silicon via electroplating may be electroplated due to external factors or human factors, and at this time, supplementary filling needs to be performed on the through silicon via wafer in such a situation, that is, step S20 is executed.
S20: and carrying out secondary electroplating treatment on the wafer through silicon via according to a second parameter so as to supplement and fill the wafer through silicon via, wherein the second parameter comprises at least one second current value, and at least one part of the second current value is larger than the first current value. And then, the incompletely filled through silicon vias need to be subjected to plating compensation, and the established electroplating compensation plating process menu is based on the process menu used in the previous complete electroplating on an electroplating current compiling program: adding one or more steps of current smaller than the initial value of the current part which is not electroplated and is remained in the electroplating process, and then adding the current part which is not electroplated to form a plating supplement current program, so as to perform the plating supplement process by the process menu. The menu of the plating process is shown in table 3:
TABLE 3 Menu of plating process when incomplete filling
After the step S20, the X-Ray detects that the TSVs at the center, middle and edge of the wafer have been completely filled as shown in fig. 6A, 6B and 6C. Further through the optical profiler, measure TSV top and show in fig. 7A, 7B, 7C, TSV has accomplished the complete filling from bottom to top, and is more unanimous with the TSV copper protruding height that once only fills completely, and wafer center department, TSV top is protruding about 0.8-0.9um, the wafer middle department, TSV top is protruding 1.2-1.4um, wafer edge, TSV top is protruding 1.1-1.2 um. Meanwhile, four-point probe measurement is performed on the copper thickness of the wafer surface, the measurement result is shown in fig. 8, the average value of the copper thickness of the TSV wafer surface is 3.53um, the uniformity is 2.02%, and the uniformity is also better consistent with the copper thickness and uniformity of the TSV wafer surface which is completely filled at one time.
According to the filling method of the wafer through silicon via provided by the embodiment of the invention, the wafer through silicon via is firstly subjected to primary electroplating treatment by using a small current value, and the through silicon via is possibly not completely filled at the moment, and on the basis, the wafer through silicon via is subjected to secondary supplementary electroplating treatment by using a large current value so as to realize final complete filling of the wafer through silicon via which is not completely filled, so that the material loss can be reduced, and the process cost can be reduced.
Preferably, the first current value and the second current value are each plural, have a predetermined order, and gradually increase in order, wherein a minimum value of the second current values is equal to a minimum value of the first current values.
The plating current menu filled twice comprises a plurality of current values, the current gradually increases according to the time sequence, and the initial current value during the plating supplement is equal to the current value during the first plating. As can be seen from the above plating tables, the current values were all sequentially increased, and the initial currents in Table 3 were equal to those in Table 2.
Preferably, the second smallest value of the second current values is equal to the largest value of the first current values.
As an alternative embodiment, the second current value of the menu of the plating-on current can select any current value in the abnormal stopping menu, but the current value at the time of abnormal stopping in the menu is preferably selected for better connection with the plating-on menu.
Preferably, the first parameter further comprises a first plating duration corresponding to a first current value, and the second parameter further comprises a second plating duration corresponding to said second current value.
The electroplating menu also comprises electroplating time corresponding to each current value, wherein the time value is related to the current value condition of each step according to the opening rate and the depth of the TSV of the product. The time shown in tables 2 and 3 is obtained from the through-silicon via opening ratio and size test in the present embodiment, and does not mean that all the time values corresponding to the current values in each step are equal.
Preferably, before the step S20, the method further includes a step S11, after the first electroplating process is performed on the through-silicon-via wafer according to the first parameter, and before the second electroplating process is performed on the through-silicon-via wafer according to the second parameter, the method further includes: and processing the through silicon via of the wafer by using the etching solution.
Preferably, the processing of the wafer through-silicon-via with the etching liquid includes: and etching the through silicon via for a preset time by using a mixed solution of hydrogen peroxide and sulfuric acid at a preset rotating speed.
Preferably, the predetermined rotation speed is 30RPM and the predetermined time is 20 s.
Preferably, the etch thickness is in the range of 10nm to 100 nm.
Performing a complementary plating process on the TSV, treating the TSV by using a copper oxide etching solution before a complementary plating electroplating process, selecting a mixed solution of hydrogen peroxide and sulfuric acid to etch the TSV wafer for 20s under the condition of a rotating speed of 30RPM, and performing micro-etching treatment, wherein the preferable copper etching thickness range can be 10-100nm in consideration of process cost; and after the etching is finished, performing a complementary plating process.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (7)
1. A method for filling a through silicon via of a wafer is characterized by comprising the following steps:
carrying out first electroplating treatment on the wafer through silicon via according to first parameters to fill the wafer through silicon via, wherein the first parameters comprise at least one first current value;
performing second electroplating treatment on the wafer through silicon via according to a second parameter to supplement and fill the wafer through silicon via, wherein the second parameter comprises at least one second current value, and at least one part of the second current value is larger than the first current value;
the first current value and the second current value are multiple, have a preset sequence and are gradually increased in sequence, wherein the minimum value of the second current values is equal to the minimum value of the first current values.
2. The wafer through silicon via filling method of claim 1, wherein the second smallest value of the second current values is equal to the largest value of the first current values.
3. The wafer through silicon via filling method of claim 1, wherein the first parameter further comprises a first plating duration corresponding to the first current value, and the second parameter further comprises a second plating duration corresponding to the second current value.
4. The method as claimed in claim 1, wherein after the first electroplating process is performed on the through-silicon-via according to the first parameter and before the second electroplating process is performed on the through-silicon-via according to the second parameter, the method further comprises: and processing the through silicon via of the wafer by using etching liquid.
5. The wafer through silicon via filling method of claim 4, wherein the processing the wafer through silicon via by using the etching solution comprises: and etching the through silicon via for a preset time by using a mixed solution of hydrogen peroxide and sulfuric acid at a preset rotating speed.
6. The wafer through silicon via filling method of claim 5, wherein the predetermined rotation speed is 30RPM and the predetermined time is 20 s.
7. The wafer through silicon via filling method of claim 4, wherein the etching thickness is in the range of 10nm to 100 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710495773.5A CN107342273B (en) | 2017-06-26 | 2017-06-26 | Filling method for through silicon via of wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710495773.5A CN107342273B (en) | 2017-06-26 | 2017-06-26 | Filling method for through silicon via of wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107342273A CN107342273A (en) | 2017-11-10 |
| CN107342273B true CN107342273B (en) | 2020-01-10 |
Family
ID=60220909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710495773.5A Active CN107342273B (en) | 2017-06-26 | 2017-06-26 | Filling method for through silicon via of wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107342273B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113363152A (en) * | 2020-03-06 | 2021-09-07 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364542A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | Copper plating method in semiconductor device |
| CN103094187A (en) * | 2011-10-31 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Forming method for silicon through hole |
| CN104465495A (en) * | 2013-09-24 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming through silicon via |
-
2017
- 2017-06-26 CN CN201710495773.5A patent/CN107342273B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364542A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | Copper plating method in semiconductor device |
| CN103094187A (en) * | 2011-10-31 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Forming method for silicon through hole |
| CN104465495A (en) * | 2013-09-24 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming through silicon via |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107342273A (en) | 2017-11-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9484293B2 (en) | Semiconductor devices with close-packed via structures having in-plane routing and method of making same | |
| JP5893914B2 (en) | Copper plating solution and copper plating method using the same | |
| US9190325B2 (en) | TSV formation | |
| US20160013135A1 (en) | Semiconductor structures and fabrication method thereof | |
| TW201428912A (en) | Buried TSV used for decaps | |
| TW201546329A (en) | Wet etching methods for copper removal and planarization in semiconductor processing | |
| US9966347B2 (en) | Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods | |
| CN208738213U (en) | Semiconductor interconnection structure | |
| US20140308764A1 (en) | Adjusting Sizes of Connectors of Package Components | |
| TW201426963A (en) | Wafer stacking structure and method of manufacturing the same | |
| Yu et al. | Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps | |
| US11742309B2 (en) | Bump coplanarity for semiconductor device assembly and methods of manufacturing the same | |
| CN107342273B (en) | Filling method for through silicon via of wafer | |
| Zervas et al. | Fabrication and characterization of wafer-level deep TSV arrays | |
| WO2013142863A1 (en) | Through-silicon via filling | |
| JP6217465B2 (en) | Wiring structure manufacturing method, wiring structure, and electronic device using the same | |
| KR102061026B1 (en) | Plating method | |
| TWI730521B (en) | System and method of electrochemical plating and forming semiocnductor structure | |
| TW200535987A (en) | Reverse-tone mask method for post-cmp elimination of copper overburden humps | |
| CN107452632B (en) | System and method for achieving uniformity across redistribution layers | |
| Sakuma et al. | Simplified 20‐µm pitch vertical interconnection process for 3D chip stacking | |
| WO2021253513A1 (en) | Silicon through-hole structure for three-dimensional integrated circuit packaging and fabrication method therefor | |
| JP2018012885A5 (en) | ||
| Koh et al. | Process development for high-current electrochemical deposition of copper pillar bumps | |
| Buckalew et al. | Within-feature-shape (WiF) control of mega pillars for high density fan-out (HDFO) technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |