CN104900543A - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN104900543A CN104900543A CN201410081136.XA CN201410081136A CN104900543A CN 104900543 A CN104900543 A CN 104900543A CN 201410081136 A CN201410081136 A CN 201410081136A CN 104900543 A CN104900543 A CN 104900543A
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- bond pad
- dielectric layer
- interlayer dielectric
- clearance wall
- groove
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Abstract
The invention relates to a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a substrate; forming an interlayer dielectric layer on the substrate; patterning the interlayer dielectric layer to form a bonding pad groove in the interlayer dielectric layer; forming a spacer in the side wall of the bonding pad groove; selecting a bonding pad material to fill the bonding pad groove to form a bonding pad; etching the spacer to partially remove the spacer; and forming a groove between the interlayer dielectric layer and the bonding pad. According to the semiconductor device and the preparation method thereof, in order to solve the problems existing in the prior art, in the current technological process, and under the condition of not influencing pattern density and not improving bonding aligning precision, process windows of the bonding process are increased.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of semiconductor device and preparation method thereof.
Background technology
At consumer electronics field, multifunctional equipment is more and more subject to liking of consumer, compared to the simple equipment of function, multifunctional equipment manufacturing process will be more complicated, such as need the chip of integrated multiple difference in functionality in circuit version, thus there is 3D integrated circuit (integrated circuit, IC) technology, 3D integrated circuit (integrated circuit, IC) a kind of system-level integrated morphology is defined as, multiple chip is stacking in vertical plane direction, thus saving space, multiple pin can be drawn as required in the marginal portion of each chip, utilize these pins as required, by need be connected to each other chip interconnected by metal wire, but still there is a lot of deficiency in aforesaid way, such as stacked chips quantity is more, and the annexation more complicated between chip, so will need to utilize many metal line, final wire laying mode is more chaotic, and volume can be caused to increase.
Therefore, at present at described 3D integrated circuit (integrated circuit, IC) mostly adopt silicon through hole (Through Silicon Via, TSV) in technology and be positioned at the metal interconnect structure formation electrical connection above silicon through hole, then realize the bonding between wafer further.
At the three-dimensional composite technology of 3D IC, under the assistance of the key technologies such as silicon through hole (TSV), intermediate plate (Interposer), encapsulation spare part, in limited areal, carry out the superposition of maximum wafer and integrate, further reduction SoC chip area, encapsulation volume promote wafer and link up efficiency.
Therefore, Cu-Cu in wafer level engages (Wafer level Cu-Cu bonding) and, as the key technology of in 3DIC, is also in development at present, and the high-end products such as 3D CIS have important application trend.
Cu-Cu in prior art in wafer level engages the method for (Wafer level Cu-Cu bonding), as shown in Figure 3, first first wafer 10 and the second wafer 20 be provided, by engaging between the copper pad 102 on the first wafer 10 and the copper pad on the second wafer 10, realize wafer face opposite stacking (F2F Stacking).Its preparation technology's flow process as shown in Figure 2, first wafer and the second wafer are provided, first interlayer dielectric layer is formed in described first wafer and described second wafer, then on described interlayer dielectric layer, light shield is formed, and interlayer dielectric layer described in patterning, in described interlayer dielectric layer, form metal pad groove, then in described groove, barrier layer and Seed Layer is formed, then in described groove, form metallic copper by Cu ECP, then perform planarisation step, to form copper pad; Then clean described wafer, is then integrated described first wafer and the second wafer joint by low-temperature thermocompression bonding mode, finally performs annealing steps.
In 3D IC encapsulation technology, wafer face opposite stacking (F2F Stacking), 2.5D silicon intermediary layer (Interposer) etc., capital relates to the bonding techniques of silicon chip and silicon chip, and at present conventional be the low-temperature thermocompression bonding mode of copper-copper.In this technical development process, because the density of Cu pad (pad) is more and more higher, so design rule is more and more less, the distance between Cu pad (pad) and Cu pad (pad) is also more and more less.In the process engaged, because Cu is in hot pressing, Cu has certain ductility, when bonding, bonding force control is not very even, easily see that adjacent bond pad (Bonding pad) causes connection due to the extension of Cu when hot pressing, cause the situation of short circuit (short), as Fig. 1 b.Meanwhile, when bond quality is fine, if as shown in 1a, due to the existence of finedraw after joint, can cause stability (reliability) problem, the engaging force of joint interface (bonding interface) is also not too enough.
Therefore need to do further improvement to joint method between wafer of the prior art, to eliminate the various drawbacks existed in prior art.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of preparation method of semiconductor device, comprising:
Substrate is provided, described substrate is formed with interlayer dielectric layer;
Interlayer dielectric layer described in patterning, to form bond pad groove in described interlayer dielectric layer;
The sidewall of described bond pad groove forms clearance wall;
Bond pad material is selected to fill described bond pad groove, to form bond pad;
Etch described clearance wall, to remove the described clearance wall of part, between described interlayer dielectric layer and described bond pad, form groove.
As preferably, the formation method of described clearance wall comprises:
At described interlayer dielectric layer, described bond pad recess sidewall and bottom deposit spacer material layer;
The described spacer material layer of described interlayer dielectric layer, described bond pad bottom portion of groove is removed in etching, to form clearance wall on the sidewall of described bond pad groove.
As preferably, the method forming described bond pad comprises:
Copper diffusion barrier layer is formed in described bond pad groove;
The Seed Layer of plated metal Cu, and form Ni metal, to fill described bond pad groove by the method for Cu electroplating;
Perform planarisation step, to obtain highly homogeneous bond pad.
As preferably, the height of described bond pad is greater than the height of described clearance wall and described interlayer dielectric layer, so that the joint between pad.
As preferably, select there is with described interlayer dielectric layer high etching selectivity method etch-back described in clearance wall, with by below described spacer etch to described interlayer dielectric layer top, form described groove.
As preferably, described clearance wall selects Si
3n
4, TiN, low-K material or carbon-based material.
As preferably, described carbon-based material comprises oxide, SiN and SiON.
As preferably, described interlayer dielectric layer selects SiO
2;
When described clearance wall selects Si
3n
4time, lower powered dry etching is selected in described etching;
When described clearance wall selects low-K material, DHF is selected in described etching;
When described clearance wall selects low TiN material, H is selected in described etching
2o
2;
When described clearance wall selects carbon-based material, oxygen base dry etching is selected in described etching.
As preferably, the width of described clearance wall is 5% ~ 25% of described bond-pad width.
As preferably, described method also comprises further:
There is provided the first wafer and the second wafer, the bond pad of wherein said first wafer and/or described second wafer comprises described groove;
Described first wafer and described second wafer are cleaned, removes the oxide that surface is formed;
Then the bond pad in the bond pad in described first wafer and described second wafer is carried out low temperature and pressure joint;
Perform annealing steps.
As preferably, the temperature that described low temperature and pressure engages is 300-400 DEG C, and engaging time is 30-90 minute, and activating pressure is 30-60KN.
As preferably, described in be annealed into process annealing, annealing temperature is 300-400 DEG C, and the time is 30-90 minute.
Present invention also offers a kind of semiconductor device, comprising:
Substrate;
Interlayer dielectric layer, is positioned in described substrate;
Bond pad, is embedded in described interlayer dielectric layer, and its height is higher than the height of described interlayer dielectric layer;
Groove, between described interlayer dielectric layer and described bond pad.
As preferably, described semiconductor device also comprises clearance wall, between described bond pad and described interlayer dielectric layer, is positioned at the below of described groove.
As preferably, described semiconductor device also comprises diffusion impervious layer, is positioned on the sidewall of described bond pad, between described pad and described clearance wall.
The present invention is in order to solve problems of the prior art, in current technological process, in not effect diagram patterning density (pattern density) situation, when not increasing joint (Bonding) alignment precision, increase the process window engaging (bonding) technique.
In the present invention after metal valley etching (Cu trench etch) completes, increase clearance wall (spacer) technique; After Cu CMP, then part (partial) etches clearance wall (spacer), forms groove; By increasing the clearance wall (recessed spacer) of depression, make in Cu-Cu engaging process, in the groove that the clearance wall that the Cu squeezed out can flow into depression is formed, avoid and engage in (Bonding) process at Cu-Cu at present, due in heat pressing process process, the extension of Cu causes the connection of adjacent C u pad, ensures when existing Cu pad density, when ensureing to aim at enough and to spare (overlay margin) at present, increase the process window of joint technology.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-1b is the SEM figure that in prior art, Cu-Cu engages, and wherein Fig. 1 a closes the good situation of quality for engaging, and Fig. 1 b is that bond quality is bad, situation about being easily short-circuited;
Fig. 2 is the process chart that in prior art, in two wafers, Cu-Cu engages;
Fig. 3 is the partial structurtes schematic diagram that in prior art, two wafer Cu-Cu engage;
Fig. 4 a-4d be the present invention one particularly in execution mode Cu-Cu engage in the preparation process schematic diagram of copper pad;
Fig. 5 is the present invention one partial structurtes schematic diagram that two wafer Cu-Cu engage in execution mode particularly;
Fig. 6 is the present invention one process chart that two wafer Cu-Cu engage in execution mode particularly.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed description is proposed, so that the preparation method of semiconductor device of the present invention to be described.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
Embodiment 1
The present invention is in order to solve Problems existing in wafer current engaging process, provide a kind of new bond pad and preparation method thereof, be further described described method below in conjunction with accompanying drawing 4a-4d and Fig. 6, wherein Fig. 6 is the schematic flow sheet of the embodiment of the invention.
First, perform step 201, substrate 201 is provided, described substrate 201 is formed with components and parts and interconnect architecture.
Particularly, with reference to Fig. 4 a, in this step, described substrate 201 can at least one in following mentioned material: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
At least containing Semiconductor substrate in described substrate, in described Semiconductor substrate, active device and interconnect architecture can be formed with.Particularly, through-silicon via structure (not shown) is formed in described Semiconductor substrate, the formation method of described through-silicon via structure is for form mask layer first on the semiconductor substrate, be preferably hard mask layer, then hard mask layer described in patterning, to form the shape of described silicon through hole groove, then with described hard mask layer for Semiconductor substrate described in mask etch, to form described silicon through hole groove in described Semiconductor substrate.Described engraving method can select dry etching or wet etching, is not limited to a certain method.
Then form separator in described silicon through hole groove, particularly, in of the present invention one particularly execution mode, form described separator by the method for thermal oxidation, described separator is SiO
2layer, its thickness is 8-50 dust, but is not limited to this thickness.Described step of thermal oxidation can select conventional rapid thermal oxidation process to carry out, in an embodiment of the present invention, select O
2or containing O
2atmosphere described device is heat-treated, described heat treatment temperature at 800-1500 DEG C, be preferably 1100-1200 DEG C, processing time is 2-30min, form through described process the oxide skin(coating) that thickness is 2-8 dust over the substrate, as preferably, the thickness of described thermal oxide layer 105 is 5 dusts.
Filled conductive material in described silicon through hole groove, to form through-silicon via structure.Select metallic copper to fill described silicon through hole groove, described silicon through hole groove can be filled by the method for physical vapor deposition (PVD) method or Cu electroplating (ECP) in the present invention.
Then carry out chemico-mechanical polishing (CMP) technique, electric conducting material described in planarization, flattening method conventional in field of semiconductor manufacture can be used to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing flattening method.Chemico-mechanical polishing flattening method is more conventional.
Then on described components and parts, form interconnect architecture, such as, on described through-silicon via structure, form described interconnection structure, described interconnection structure is positioned at through hole, interlayer metal layer and top through hole above described components and parts.
The formation method of described through hole, interlayer metal layer and top through hole can realize by the following method, but is not limited to following methods.
For described through hole, interlevel dielectric deposition on the semiconductor substrate, and interlayer dielectric layer described in patterning, form opening, to expose described active device, then opening described in filled with conductive material is selected, and planarization, to form electrical connection with the active device in described semiconductor device.
Then form described interlayer metal layer and top through hole, formation method can with reference to the formation method of described through hole, or the additive method selecting this area conventional, does not repeat them here.
Perform step 202, form interlayer dielectric layer 202 on the substrate, and interlayer dielectric layer 202 described in patterning, to form bond pad groove in described interlayer dielectric layer 202.
Particularly, as shown in fig. 4 a, interlevel dielectric deposition 202 on the substrate, wherein said interlayer dielectric layer 202 can select conventional dielectric material, in of the present invention one particularly execution mode, be preferably SiO
2.
One in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG) that the deposition process of described interlayer dielectric layer 202 can select chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc. to be formed.Preferred chemical vapor deposition (CVD) method in the present invention.
Then interlayer dielectric layer 202 described in patterning, to form bond pad groove in described interlayer dielectric layer 202.
Particularly, as shown in fig. 4 a, first on described interlayer dielectric layer 202, form photoresist layer or organic distribution layer (Organic distribution layer of patterning, ODL), siliceous bottom antireflective coating (Si-BARC) and be positioned at the photoresist layer (not shown) of patterning at top, pattern definition on the wherein said photoresist pattern of described bond pad groove, then with described photoresist layer for mask layer etching described organic distribution layer, bottom antireflective coating forms the pattern of bond pad groove, then with described organic distribution layer, bottom antireflective coating is mask, etch described interlayer metal dielectric layer, to form described bond pad groove.
Further, described bond pad groove can select common shape, the generic grooves that the critical size of such as upper and lower opening is the same, or can also select groove wide at the top and narrow at the bottom, is not limited to a certain shape, can arranges as required.The number of described bond pad groove, is also not limited to a certain number range.
Particularly, select dry etching or wet etching in this step, preferably C-F etchant etches described Semiconductor substrate 201 in the present invention, and described C-F etchant is CF
4, CHF
3, C
4f
8and C
5f
8in one or more.In this embodiment, described dry etching can select CF
4, CHF
3, add N in addition
2, CO
2in one as etching atmosphere, wherein gas flow is CF
410-200sccm, CHF
310-200sccm, N
2or CO
2or O
210-400sccm, described etching pressure is 30-150mTorr, and etching period is 5-120s, is preferably 5-60s, is more preferably 5-30s.
Perform step 203, the sidewall of described bond pad groove forms clearance wall 203.
Particularly, as shown in Fig. 4 a-4b, first at described interlayer dielectric layer 202, described bond pad recess sidewall and bottom deposit spacer material layer, to cover described substrate completely, wherein said clearance wall 203 selects Si
3n
4, TiN, low-K material or carbon-based material (carbon based materials), such as SiN, SiON or oxide etc.
Wherein said spacer material layer should have larger etching selectivity with described interlayer dielectric layer 202, can be more prone in subsequent steps form described groove.
Then the described deposition spacer material layer of described interlayer dielectric layer 202, described bond pad bottom portion of groove is removed in etching, to form clearance wall 203 on the sidewall of described bond pad groove, the method of overall etch (Blank etch) is selected to etch described spacer material layer in this step, only retain the spacer material layer on the sidewall of described bond pad groove, form clearance wall 203, as shown in Figure 4 b.The width of described clearance wall 203 is 5% ~ 25% of described bond-pad width.
Select dry method overall etch (Blank dry etch) in this step, select which kind of dry etching particularly, need to select according to described selecting of spacer material layer, be not limited to a certain method, those skilled in the art can select as the case may be.
Perform step 204, select bond pad material to fill described bond pad groove, to form bond pad.
As illustrated in fig. 4 c, first in described bond pad groove, copper diffusion barrier layer is formed; Then the Seed Layer of plated metal Cu, and form Ni metal, to fill described bond pad groove by the method for Cu electroplating; Then planarisation step is performed, to obtain highly homogeneous bond pad.
Particularly, first in described bond pad groove, diffusion impervious layer 205(barrier is formed in this step), be preferably formed copper diffusion barrier layer, the formation method of described copper diffusion barrier layer can for mainly to select physical vaporous deposition and chemical vapour deposition technique, particularly, can select evaporation, electron beam evaporation, plasma spray deposition and sputtering, preferably plasma spray deposition and sputtering method form described copper diffusion barrier layer in the present invention.The thickness of described copper diffusion barrier layer is not limited in a certain numerical value or scope, can adjust as required.
As preferably, described diffusion barrier material can one or more for being selected from TaN, Ta, TiN, Ti, reduce the RC delay time because dead resistance and parasitic capacitance cause.As preferably, in of the present invention one particularly execution mode, be preferably TaN and/or Ta.
Then in the first Seed Layer of plated metal copper on described diffusion impervious layer, the deposition process of described Seed Layer can select chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc.
Then select the method for Cu electroplating (ECP) to form described metallic copper 204, as preferably, can also use additive when electroplating, described additive is smooth dose (LEVELER), accelerator (ACCELERATORE) and inhibitor (SUPPRESSOR).
As preferably, forming the step that can also comprise annealing after described metallic copper 204 is formed further, annealing can carry out 2-4 hour at 80-160 DEG C, to impel copper crystallization again, crystal grain of growing up, reduces resistance and improves stability.
Then metallic copper 204 material described in planarization, metal level 204 described in planarization and described diffusion impervious layer 205 are to the top at described interlayer dielectric layer 202 top, and it is highly greater than the height of described interlayer dielectric layer.
Perform step 205, clearance wall 203 described in etch-back, to remove the described clearance wall 203 of part, forms groove between described interlayer dielectric layer 202 and described bond pad.
Particularly, as shown in figure 4d, select clearance wall 203 described in dry etching or wet etching etch-back in this step, further, select there is with described interlayer dielectric layer 202 high etching selectivity engraving method etch-back described in clearance wall 203, so that described clearance wall 203 is etched to below described interlayer dielectric layer 202 top, to form groove between described interlayer dielectric layer 202 and described bond pad, make in Cu-Cu engaging process, in the groove that the clearance wall that the Cu squeezed out can flow into depression is formed, avoid and engage in (Bonding) process at Cu-Cu at present, due in heat pressing process process, the extension of Cu causes the connection of adjacent C u pad.
Further, when described spacer material layer selects different materials, select different engraving methods, described interlayer dielectric layer selects SiO
2; When described clearance wall selects Si
3n
4time, described etch-back selects lower powered dry etching; When described clearance wall selects low-K material, described etch-back selects DHF; When described clearance wall selects low TiN material, described etch-back selects H
2o
2, when described clearance wall selects carbon-based material, described etch-back selects oxygen base dry etching.
Perform step 206, engaged by two wafers comprising described bond pad, described joint comprises the joint between bond pad.
Particularly, as shown in Figure 5, two wafers are respectively the first wafer and the second wafer, described in wherein said first wafer and the second wafer, bond pad is all prepared by said method, or only the first wafer or the bond pad only in the second wafer are formed by said method, groove is formed between the described bond pad formed by the method and described interlayer dielectric layer, and the bond pad in other wafer is formed by conventional method, do not comprise the step forming clearance wall and etch-back.
As preferably, before the first wafer and the second wafer engage, also comprise the step that described first wafer and described second wafer are cleaned, remove the oxide that surface is formed, such as, remove the Cu oxide that surface is formed.
Then the bond pad in the bond pad in described first wafer and described second wafer is carried out low temperature and pressure joint; The temperature that described low temperature and pressure engages is 300-400 DEG C, and engaging time is 30-90 minute, and activating pressure is 30-60KN.
Finally perform annealing steps, described in be annealed into process annealing, annealing temperature is 300-400 DEG C, and the time is 30-90 minute.Rapid thermal annealing can be selected in the present invention, particularly, the one in following several mode can be selected: pulse laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser short annealing and non-coherent broad band light source (as halogen lamp, arc lamp, graphite heating) short annealing etc.Those skilled in the art can select as required, are also not limited to examples cited.
Embodiment 2
Present invention also offers a kind of high density bond pad, comprising:
Substrate 201;
Interlayer dielectric layer 202, is positioned in described substrate 201;
Bond pad, is embedded in described interlayer dielectric layer 202, and its height is higher than the height of described interlayer dielectric layer 202;
Groove, between described interlayer dielectric layer 202 and described bond pad.
Described semiconductor device also comprises clearance wall 203, between described bond pad and described interlayer dielectric layer 202, is positioned at the below of described groove.
Described semiconductor device also comprises diffusion impervious layer, is positioned on the sidewall of described bond pad, between described pad and described clearance wall 203.
Described clearance wall 203 is between described bond pad and described interlayer dielectric layer 202, it is highly less than the height of described interlayer dielectric layer 202, to form groove between the described interlayer dielectric layer 202 above described clearance wall 203 and described bond pad, make in Cu-Cu engaging process, in the groove that the clearance wall that the Cu squeezed out can flow into depression is formed, avoid and engage in (Bonding) process at Cu-Cu at present, due in heat pressing process process, the extension of Cu causes the connection of adjacent C u pad.
As preferably, described bond pad also comprises and is positioned at diffusion impervious layer, is positioned on the sidewall of described pad, between described pad and described clearance wall.
The present invention is in order to solve problems of the prior art, in current technological process, in not effect diagram patterning density (pattern density) situation, when not increasing joint (Bonding) alignment precision, increase the process window engaging (bonding) technique.
In the present invention after metal valley etching (Cu trench etch) completes, increase clearance wall (spacer) technique; After Cu CMP, then part (partial) etches clearance wall (spacer), forms groove; By increasing the clearance wall (recessed spacer) of depression, make in Cu-Cu engaging process, in the groove that the clearance wall that the Cu squeezed out can flow into depression is formed, avoid and engage in (Bonding) process at Cu-Cu at present, due in heat pressing process process, the extension of Cu causes the connection of adjacent C u pad, ensures when existing Cu pad density, when ensureing to aim at enough and to spare (overlay margin) at present, increase the process window of joint technology.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (15)
1. a preparation method for semiconductor device, comprising:
Substrate is provided, described substrate is formed with interlayer dielectric layer;
Interlayer dielectric layer described in patterning, to form bond pad groove in described interlayer dielectric layer;
The sidewall of described bond pad groove forms clearance wall;
Bond pad material is selected to fill described bond pad groove, to form bond pad;
Etch described clearance wall, to remove the described clearance wall of part, between described interlayer dielectric layer and described bond pad, form groove.
2. method according to claim 1, is characterized in that, the formation method of described clearance wall comprises:
At described interlayer dielectric layer, described bond pad recess sidewall and bottom deposit spacer material layer;
The described spacer material layer of described interlayer dielectric layer, described bond pad bottom portion of groove is removed in etching, to form clearance wall on the sidewall of described bond pad groove.
3. method according to claim 1, is characterized in that, the method forming described bond pad comprises:
Copper diffusion barrier layer is formed in described bond pad groove;
The Seed Layer of plated metal Cu, and form Ni metal, to fill described bond pad groove by the method for Cu electroplating;
Perform planarisation step, to obtain highly homogeneous bond pad.
4. the method according to claim 1 or 3, is characterized in that, the height of described bond pad is greater than the height of described clearance wall and described interlayer dielectric layer, so that the joint between pad.
5. method according to claim 1, is characterized in that, select there is with described interlayer dielectric layer high etching selectivity method etch-back described in clearance wall, with by described spacer etch to below described interlayer dielectric layer top, form described groove.
6. method according to claim 1, is characterized in that, described clearance wall selects Si
3n
4, TiN, low-K material or carbon-based material.
7. method according to claim 6, is characterized in that, described carbon-based material comprises oxide, SiN and SiON.
8. the method according to claim 1 or 6, is characterized in that, described interlayer dielectric layer selects SiO
2;
When described clearance wall selects Si
3n
4time, lower powered dry etching is selected in described etching;
When described clearance wall selects low-K material, DHF is selected in described etching;
When described clearance wall selects low TiN material, H is selected in described etching
2o
2;
When described clearance wall selects carbon-based material, oxygen base dry etching is selected in described etching.
9. method according to claim 1, is characterized in that, the width of described clearance wall is 5% ~ 25% of described bond-pad width.
10. method according to claim 1, is characterized in that, described method also comprises further:
There is provided the first wafer and the second wafer, the bond pad of wherein said first wafer and/or described second wafer comprises described groove;
Described first wafer and described second wafer are cleaned, removes the oxide that surface is formed;
Then the bond pad in the bond pad in described first wafer and described second wafer is carried out low temperature and pressure joint;
Perform annealing steps.
11. methods according to claim 10, is characterized in that, the temperature that described low temperature and pressure engages is 300-400 DEG C, and engaging time is 30-90 minute, and activating pressure is 30-60KN.
12. methods according to claim 10, is characterized in that, described in be annealed into process annealing, annealing temperature is 300-400 DEG C, and the time is 30-90 minute.
13. 1 kinds of semiconductor device, comprising:
Substrate;
Interlayer dielectric layer, is positioned in described substrate;
Bond pad, is embedded in described interlayer dielectric layer, and its height is higher than the height of described interlayer dielectric layer;
Groove, between described interlayer dielectric layer and described bond pad.
14. semiconductor device according to claim 13, is characterized in that, described semiconductor device also comprises clearance wall, between described bond pad and described interlayer dielectric layer, are positioned at the below of described groove.
15. semiconductor device according to claim 14, is characterized in that, described semiconductor device also comprises diffusion impervious layer, are positioned on the sidewall of described bond pad, between described pad and described clearance wall.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410081136.XA CN104900543B (en) | 2014-03-06 | 2014-03-06 | A kind of semiconductor devices and preparation method thereof |
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|---|---|---|---|
| CN201410081136.XA CN104900543B (en) | 2014-03-06 | 2014-03-06 | A kind of semiconductor devices and preparation method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN104900543A true CN104900543A (en) | 2015-09-09 |
| CN104900543B CN104900543B (en) | 2018-02-06 |
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| CN108431947A (en) * | 2015-11-23 | 2018-08-21 | 美敦力公司 | Embedded metal structure in glass |
| CN109786348A (en) * | 2017-11-15 | 2019-05-21 | 台湾积体电路制造股份有限公司 | It is formed and has reeded metal joined article |
| CN110092348A (en) * | 2018-01-30 | 2019-08-06 | 上海新微技术研发中心有限公司 | Eutectic bonding structure and eutectic bonding method |
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| CN108431947A (en) * | 2015-11-23 | 2018-08-21 | 美敦力公司 | Embedded metal structure in glass |
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| US10854574B2 (en) | 2017-11-15 | 2020-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming metal bonds with recesses |
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