CN104900543B - A kind of semiconductor devices and preparation method thereof - Google Patents
A kind of semiconductor devices and preparation method thereof Download PDFInfo
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- CN104900543B CN104900543B CN201410081136.XA CN201410081136A CN104900543B CN 104900543 B CN104900543 B CN 104900543B CN 201410081136 A CN201410081136 A CN 201410081136A CN 104900543 B CN104900543 B CN 104900543B
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- bond pad
- dielectric layer
- interlayer dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof, there is provided substrate, formed with interlayer dielectric layer in the substrate；The interlayer dielectric layer is patterned, to form bond pad groove in the interlayer dielectric layer；Clearance wall is formed in the side wall of the bond pad groove；The bond pad groove is filled from bond pad material, to form bond pad；The clearance wall is etched, to remove the part clearance wall, groove is formed between the interlayer dielectric layer and the bond pad.The present invention is in order to solve problems of the prior art, in current technological process, is not influenceing to pattern density（pattern density）In the case of, do not increasing engagement（Bonding）In the case of alignment precision, increase engagement（bonding）The process window of technique.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor devices and preparation method thereof.
Background technology
In consumer electronics field, multifunctional equipment is increasingly liked by consumer, compared to the simple equipment of function,
Multifunctional equipment manufacturing process will be more complicated, than the chip if desired for integrated multiple difference in functionalitys in circuit version, thus go out
3D integrated circuits are showed（Integrated circuit, IC）Technology, 3D integrated circuits（Integrated circuit, IC）Quilt
A kind of system-level integrated morphology is defined as, multiple chips are stacked in vertical plane direction, so as to save space, each chip
Marginal portion can draw multiple pins as needed, utilize these pins as needed, it would be desirable to the chip of interconnection
Interconnected by metal wire, but aforesaid way still has many deficiencies, for example stacked chips quantity is more, and between chip
Annexation it is more complicated, then just may require that using more metal lines, final wire laying mode is more chaotic, Er Qiehui
Volume is caused to increase.
Therefore, at present in the 3D integrated circuits（Integrated circuit, IC）Silicon hole is mostly used in technology
（Through Silicon Via, TSV）And the metal interconnection structure above silicon hole forms electrical connection, then enters one
Step realizes the bonding between wafer.
In 3D IC solid composite technologies, the key technology such as silicon hole (TSV), intermediate plate (Interposer), zero group of encapsulation
Under the assistance of part, maximum chip superposition is carried out in limited areal and is integrated, further reduces SoC chip areas, envelope
Dress volume simultaneously lifts chip communication efficiency.
Therefore, the Cu-Cu engagements in wafer level（Wafer level Cu-Cu bonding）As one in 3DIC
Key technology, development is also at present, have important application trend on the high-end products such as 3D CIS.
Cu-Cu engagements in wafer level in the prior art（Wafer level Cu-Cu bonding）Method, such as scheme
Shown in 3, the first wafer 10 and the second wafer 20 are provided first, pass through the wafer 10 of copper pad 102 and second on the first wafer 10
On copper pad between engage, realize that chip stacks (F2F Stacking) face-to-face.Its preparation technology flow as shown in Fig. 2
First wafer and the second wafer are provided, are initially formed interlayer dielectric layer in first wafer and second wafer, then
Light shield is formed on the interlayer dielectric layer, and patterns the interlayer dielectric layer, metal is formed in the interlayer dielectric layer
Pad recess, barrier layer and Seed Layer are then formed in the groove, is then formed in the groove by Cu ECP
Metallic copper, planarisation step is then performed, to form copper pad；Then the wafer is cleaned, then passes through low-temperature thermocompression bonding
First wafer and the second wafer are combined into one by mode, finally perform annealing steps.
In 3D IC package technologies, chip stacks (F2F Stacking), 2.5D silicon intermediary layer (Interposer) face-to-face
Deng, can all be related to the bonding techniques of silicon chip and silicon chip, and it is currently used be copper-copper low-temperature thermocompression bonding mode.At this
In individual technology evolution, due to Cu pads（pad）Density more and more higher, so design rule is less and less, Cu pads
（pad）With Cu pads（pad）The distance between it is also less and less.During engagement, because Cu is in hot pressing, Cu tools
There is certain ductility, bonding force control is not very uniformly, it is readily seen that adjacent bond pad when bonding（Bonding
pad）Because extensions of the Cu in hot pressing causes to connect, short circuit is caused（short）Situation, such as Fig. 1 b.Meanwhile bond quality is very
When good, if as shown in 1a, due to the presence of fine crack after engagement, stability can be caused（reliability）Problem, engage boundary
Face（bonding interface）Engaging force it is also less enough.
Therefore need to be improved joint method is further between wafer of the prior art, to eliminate in the prior art
Existing various drawbacks.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
The present invention is in order to overcome the problem of presently, there are, there is provided a kind of preparation method of semiconductor devices, including：
Substrate is provided, formed with interlayer dielectric layer in the substrate；
The interlayer dielectric layer is patterned, to form bond pad groove in the interlayer dielectric layer；
Clearance wall is formed in the side wall of the bond pad groove；
The bond pad groove is filled from bond pad material, to form bond pad；
Etch the clearance wall, to remove the part clearance wall, the interlayer dielectric layer and the bond pad it
Between form groove.
Preferably, the forming method of the clearance wall includes：
In the interlayer dielectric layer, the bond pad recess sidewall and bottom deposit spacer material layer；
Etching removes the interlayer dielectric layer, the spacer material layer of the bond pad bottom portion of groove, with institute
State and form clearance wall in the side wall of bond pad groove.
Preferably, forming the method for the bond pad includes：
Copper diffusion barrier layer is formed in the bond pad groove；
Deposited metal Cu Seed Layer, and Ni metal is formed by the method for Cu electroplating, to fill the seam welding
Disk groove；
Planarisation step is performed, to obtain highly homogeneous bond pad.
Preferably, the height of the bond pad is more than the height of the clearance wall and the interlayer dielectric layer, so as to
Engagement between pad.
Preferably, there is clearance wall described in the method etch-back of high etching selectivity from the interlayer dielectric layer,
With will the spacer etch to following at the top of the interlayer dielectric layer, form the groove.
Preferably, the clearance wall selects Si3N4, TiN, low-K material or carbon-based material.
Preferably, the carbon-based material includes oxide, SiN and SiON.
Preferably, the interlayer dielectric layer selects SiO2；
When the clearance wall selects Si3N4When, dry etching of the etching from low-power；
When the clearance wall selects low-K material, DHF is selected in the etching；
When the clearance wall selects low TiN materials, H is selected in the etching2O2；
When the clearance wall selects carbon-based material, epoxide dry etching is selected in the etching.
Preferably, the width of the clearance wall is the 5%~25% of the bond-pad width.
Preferably, methods described still further comprises：
The first wafer and the second wafer are provided, wherein the bond pad bag of first wafer and/or second wafer
Containing the groove；
First wafer and second wafer are cleaned, remove the oxide that surface is formed；
Then the bond pad in the bond pad in first wafer and second wafer is subjected to low temperature and pressure
Engagement；
Perform annealing steps.
Preferably, the temperature of the low temperature and pressure engagement is 300-400 DEG C, engaging time is 30-90 minutes, engagement pressure
Power is 30-60KN.
Preferably, described be annealed into process annealing, annealing temperature is 300-400 DEG C, and the time is 30-90 minutes.
Present invention also offers a kind of semiconductor devices, including：
Substrate；
Interlayer dielectric layer, in the substrate；
Bond pad, in the interlayer dielectric layer, its height is higher than the height of the interlayer dielectric layer；
Groove, between the interlayer dielectric layer and the bond pad.
Preferably, the semiconductor devices also includes clearance wall, positioned at the bond pad and the interlayer dielectric layer
Between, positioned at the lower section of the groove.
Preferably, the semiconductor devices also includes diffusion impervious layer, in the side wall of the bond pad, it is located at
Between the pad and the clearance wall.
The present invention in current technological process, is not influenceing to pattern to solve problems of the prior art
Density（pattern density）In the case of, do not increasing engagement（Bonding）In the case of alignment precision, increase engagement
（bonding）The process window of technique.
Etched in the present invention in metal valley（Cu trench etch）After completion, increase clearance wall（spacer）Work
Skill；In Cu CMP and then part（partial）Etch clearance wall（spacer）, form groove；By the gap for increasing depression
Wall（recessed spacer）So that in Cu-Cu engaging processes, the Cu squeezed out can be flowed into the clearance wall shape of depression
Into groove in, avoid at present Cu-Cu engage（Bonding）During, during heat pressing process, Cu extension is made
Into the connection of adjacent C u pads, ensure in the case of existing Cu pad densities, ensure alignment enough and to spare at present（overlay
margin）In the case of, increase the process window of joint technology.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-1b are the SEM figures of Cu-Cu engagements in the prior art, and wherein Fig. 1 a close the preferable situation of quality, figure for engagement
1b is that bond quality is bad, and the situation of short circuit easily occurs；
The process chart that Fig. 2 engages for Cu-Cu in two wafers in the prior art；
Fig. 3 is the partial structural diagram of two wafer Cu-Cu engagements in the prior art；
The preparation process schematic diagram of copper pad during Fig. 4 a-4d engage for Cu-Cu in the present invention one specifically embodiment；
The partial structural diagram that Fig. 5 engages for two wafer Cu-Cu in the present invention one specifically embodiment；
The process chart that Fig. 6 engages for two wafer Cu-Cu in the present invention one specifically embodiment.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate of the present invention half
The preparation method of conductor device.Obviously, execution of the invention be not limited to semiconductor applications technical staff be familiar with it is special
Details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have it
His embodiment.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in this manual
When, it, which is indicated, has the feature, entirety, step, operation, element and/or component, but does not preclude the presence or addition of one or more
Individual other features, entirety, step, operation, element, component and/or combinations thereof.
Now, the exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
Understand be to provide these embodiments be in order that disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness in layer and region is exaggerated
Degree, and make identical element is presented with like reference characters, thus description of them will be omitted.
Embodiment 1
The present invention is in order to solve problem present in wafer current engaging process, there is provided a kind of new bond pad and its
Preparation method, below in conjunction with the accompanying drawings 4a-4d and Fig. 6 methods described is further described, wherein Fig. 6 for the present invention one have
The schematic flow sheet of body embodiment.
First, step 201 is performed, there is provided substrate 201, formed with component and interconnection architecture in the substrate 201.
Specifically, reference picture 4a, in this step, the substrate 201 can be the following material being previously mentioned at least
It is a kind of：Silicon, silicon-on-insulator（SOI）, be laminated silicon on insulator（SSOI）, be laminated SiGe on insulator（S-SiGeOI）And
Germanium on insulator SiClx（SiGeOI）Deng.
At least contain Semiconductor substrate in the substrate, could be formed with the Semiconductor substrate active device and mutually
It is coupled structure.Specifically, through-silicon via structure is formed in the Semiconductor substrate（Not shown in figure）, the shape of the through-silicon via structure
Into method to form mask layer, preferably hard mask layer on the semiconductor substrate first, the hard mask is then patterned
Layer, to form the shape of the silicon hole groove, then using the hard mask layer as Semiconductor substrate described in mask etch, with
The silicon hole groove is formed in the Semiconductor substrate.The engraving method can select dry etching or wet etching,
It is not limited to a certain method.
Then separation layer is formed in the silicon hole groove, specifically, in of the invention one specifically embodiment, led to
The method of thermal oxide is crossed to form the separation layer, the separation layer is SiO2Layer, its thickness is 8-50 angstroms, but is not limited to
The thickness.The step of thermal oxidation can select conventional rapid thermal oxidation process to carry out, in the specific embodiment party of the present invention
O is selected in formula2Or contain O2Atmosphere the device is heat-treated, the heat treatment temperature is at 800-1500 DEG C, preferably
For 1100-1200 DEG C, processing time 2-30min, the oxidation that thickness is 2-8 angstroms is formed over the substrate by the processing
Nitride layer, preferably, the thickness of the thermal oxide layer 105 is 5 angstroms.
Conductive material is filled in the silicon hole groove, to form through-silicon via structure.The silicon is filled from metallic copper
Through hole groove, physical vapour deposition (PVD) can be passed through in the present invention（PVD）Method or Cu electroplating（ECP）Method filling institute
State silicon hole groove.
Then (CMP) technique is chemically-mechanicapolish polished, planarizes the conductive material, can be led using semiconductor manufacturing
Conventional flattening method realizes the planarization on surface in domain.The non-limiting examples of the flattening method include mechanical planarization
Change method and chemically mechanical polishing flattening method.Chemically mechanical polishing flattening method is more often used.
Then interconnection architecture is formed on the component, such as the mutually link is formed on the through-silicon via structure
Structure, the interconnection structure are located at through hole, interlayer metal layer and top through hole above the component.
The forming method of the through hole, interlayer metal layer and top through hole can be realized by the following method, still
It is not limited to following methods.
By taking the through hole as an example, interlevel dielectric deposition, and pattern the interlayer and be situated between on the semiconductor substrate
Electric layer, form opening, to expose the active device, then fill the opening from conductive material, and planarize, with
Active device in the semiconductor devices forms electrical connection.
Then the interlayer metal layer and top through hole are formed, forming method is referred to the formation side of the through hole
Method, or other method commonly used in the art is selected, it will not be repeated here.
Step 202 is performed, forms interlayer dielectric layer 202 on the substrate, and patterns the interlayer dielectric layer 202,
To form bond pad groove in the interlayer dielectric layer 202.
Specifically, as shown in fig. 4 a, interlevel dielectric deposition 202 on the substrate, wherein the interlayer dielectric layer 202
Conventional dielectric material can be selected, is preferably SiO in of the invention one specifically embodiment2。
The deposition process of the interlayer dielectric layer 202 can select chemical vapor deposition（CVD）Method, physical vapour deposition (PVD)
（PVD）Method or ald（ALD）The low-pressure chemical vapor depositions (LPCVD) of the formation such as method, laser ablation deposition (LAD) with
And one kind in selective epitaxy growth (SEG).Preferred chemical vapor deposition in the present invention（CVD）Method.
Then the interlayer dielectric layer 202 is patterned, to form bond pad groove in the interlayer dielectric layer 202.
Specifically, as shown in fig. 4 a, form the photoresist layer of patterning on the interlayer dielectric layer 202 first or have
Machine distribution layer（Organic distribution layer,ODL）, siliceous bottom antireflective coating（Si-BARC）And position
In the photoresist layer of the patterning at top（Not shown in figure）, wherein pattern definition on the photoresist seam welding
The pattern of disk groove, then etch organic distribution layer using the photoresist layer as mask layer, bottom antireflective coating is formed
The pattern of bond pad groove, then using organic distribution layer, bottom antireflective coating as mask, etch the interlayer metal
Dielectric layer, to form the bond pad groove.
Further, the bond pad groove can select common shape, such as the critical size of upper and lower opening is the same
Generic grooves, or groove wide at the top and narrow at the bottom can also be selected, it is not limited to a certain shape, can be set as needed
Put.The number of the bond pad groove, is also not limited to a certain number range.
Specifically, in this step from dry etching or wet etching, preferred C-F etchants lose in the present invention
The Semiconductor substrate 201 is carved, the C-F etchants are CF4、CHF3、C4F8And C5F8In one or more.In the embodiment party
In formula, the dry etching can select CF4、CHF3, in addition plus N2、CO2In it is a kind of as etching atmosphere, wherein gas
Flow is CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure are 30-
150mTorr, more preferably etching period 5-120s, preferably 5-60s, 5-30s.
Step 203 is performed, clearance wall 203 is formed in the side wall of the bond pad groove.
Specifically, as shown in Fig. 4 a-4b, first the interlayer dielectric layer 202, the bond pad recess sidewall and
Bottom deposit spacer material layer, so that the substrate is completely covered, wherein the clearance wall 203 selects Si3N4, TiN, low-K material
Or carbon-based material（carbon based materials）, such as SiN, SiON or oxide etc..
Wherein described spacer material layer should have larger etching selectivity with the interlayer dielectric layer 202, so as to
It can be more prone to form the groove in subsequent steps.
Then etching removes the interlayer dielectric layer 202, the deposition gap wall material of the bond pad bottom portion of groove
The bed of material, to form clearance wall 203 in the side wall of the bond pad groove, in this step from overall etch（Blank
etch）Method etch the spacer material layer, only retain the spacer material layer in the side wall of the bond pad groove,
Clearance wall 203 is formed, as shown in Figure 4 b.The width of the clearance wall 203 is the 5%~25% of the bond-pad width.
Dry method overall etch is selected in this step（Blank dry etch）, specifically from which kind of dry etching, need
To be selected according to the selection of the spacer material layer, it is not limited to which a certain method, those skilled in the art can be with
Selected as the case may be.
Step 204 is performed, the bond pad groove is filled from bond pad material, to form bond pad.
As illustrated in fig. 4 c, copper diffusion barrier layer is formed in the bond pad groove first；Then deposited metal Cu
Seed Layer, and Ni metal is formed by the method for Cu electroplating, to fill the bond pad groove；Then planarization is performed
Step, to obtain highly homogeneous bond pad.
Specifically, diffusion impervious layer 205 is formed first in the bond pad groove in this step（barrier）,
Be preferably formed as copper diffusion barrier layer, the forming method of the copper diffusion barrier layer can be mainly from physical vaporous deposition and
Chemical vapour deposition technique, specifically, evaporation, electron beam evaporation, plasma spray deposition and sputtering can be selected, in this hair
Preferred plasma spray deposition and sputtering method form the copper diffusion barrier layer in bright.The thickness of the copper diffusion barrier layer
It is not limited in a certain numerical value or scope, can be adjusted as needed.
Preferably, the diffusion barrier material can be the one or more in TaN, Ta, TiN, Ti, to subtract
The small RC delay times caused by dead resistance and parasitic capacitance.Preferably, in of the invention one specifically embodiment
Preferably TaN and/or Ta.
Then in the Seed Layer of the deposited metal copper first on the diffusion impervious layer, the deposition process of the Seed Layer can
With from chemical vapor deposition（CVD）Method, physical vapour deposition (PVD)（PVD）Method or ald（ALD）Method etc..
Then Cu electroplating is selected（ECP）Method form the metallic copper 204, preferably, plating when may be used also
So that using additive, the additive is flat dose（LEVELER）, accelerator（ACCELERATORE）And inhibitor
（SUPPRESSOR）.
Preferably, after forming the metallic copper 204 and being formed can also further comprising annealing the step of, annealing can be with
2-4 hours are carried out at 80-160 DEG C, to promote copper to recrystallize, long big crystal grain, resistance is reduced and improves stability.
Then the material of metallic copper 204 is planarized, planarizes the metal level 204 and the diffusion impervious layer 205
To the top at the top of interlayer dielectric layer 202, its height is more than the height of the interlayer dielectric layer.
Step 205 is performed, clearance wall 203 described in etch-back, to remove the part clearance wall 203, is situated between in the interlayer
Groove is formed between electric layer 202 and the bond pad.
Specifically, as shown in figure 4d, in this step from clearance wall described in dry etching or wet etching etch-back
203, further, from clearance wall described in the engraving method etch-back with the interlayer dielectric layer 202 with high etching selectivity
203, the clearance wall 203 is etched to below the top of interlayer dielectric layer 202, with the He of interlayer dielectric layer 202
Groove is formed between the bond pad so that in Cu-Cu engaging processes, the Cu squeezed out can be flowed into the gap of depression
In the groove that wall is formed, avoid and engaged at present in Cu-Cu（Bonding）During, during heat pressing process, Cu's prolongs
Exhibition causes the connection of adjacent C u pads.
Further, when the spacer material layer choosing is with different materials, from different engraving methods, the interlayer
Dielectric layer selects SiO2；When the clearance wall selects Si3N4When, the etch-back selects the dry etching of low-power；Between described
When gap wall selects low-K material, the etch-back selects DHF；When the clearance wall selects low TiN materials, the etch-back choosing
Use H2O2, when the clearance wall selects carbon-based material, the etch-back selects epoxide dry etching.
Step 206 is performed, two wafers comprising the bond pad are engaged, the engagement is included between bond pad
Engagement.
Specifically, as shown in figure 5, two wafers are respectively the first wafer and the second wafer, wherein first wafer and
Bond pad is prepared by the above method described in second wafer, either the engagement in only the first wafer or only the second wafer
Pad is formed by the above method, formed with recessed between the bond pad and the interlayer dielectric layer that are formed by this method
Groove, and the bond pad in wafer is formed by conventional method in addition, and not comprising the step of forming clearance wall and etch-back.
Preferably, before the first wafer and the engagement of the second wafer, in addition to first wafer and described second
The step of wafer is cleaned, the oxide that surface is formed is removed, such as remove the Cu oxide that surface is formed.
Then the bond pad in the bond pad in first wafer and second wafer is subjected to low temperature and pressure
Engagement；The temperature of low temperature and pressure engagement is 300-400 DEG C, and engaging time is 30-90 minutes, activating pressure 30-60KN.
Annealing steps are finally performed, described to be annealed into process annealing, annealing temperature is 300-400 DEG C, and the time is 30-90 points
Clock.Rapid thermal annealing can be selected in the present invention, specifically, the one kind that can be selected in following several ways：Pulse laser
Short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser short annealing and non-coherent broad band light
Source（Such as halogen lamp, arc lamp, graphite heating）Short annealing etc..Those skilled in the art can be selected as needed, also simultaneously
It is not limited to examples cited.
Embodiment 2
Present invention also offers a kind of high density bond pad, including：
Substrate 201；
Interlayer dielectric layer 202, in the substrate 201；
Bond pad, in the interlayer dielectric layer 202, its height is higher than the height of the interlayer dielectric layer 202；
Groove, between the interlayer dielectric layer 202 and the bond pad.
The semiconductor devices also includes clearance wall 203, positioned at the bond pad and the interlayer dielectric layer 202 it
Between, positioned at the lower section of the groove.
The semiconductor devices also includes diffusion impervious layer, in the side wall of the bond pad, positioned at the pad
Between the clearance wall 203.
For the clearance wall 203 between the bond pad and the interlayer dielectric layer 202, its height is less than the layer
Between dielectric layer 202 height, between the interlayer dielectric layer 202 above the clearance wall 203 and the bond pad
Forming groove so that in Cu-Cu engaging processes, the Cu squeezed out can be flowed into the groove of clearance wall formation of depression,
Avoid and engaged at present in Cu-Cu（Bonding）During, during heat pressing process, Cu extension causes adjacent C u to weld
The connection of disk.
Preferably, the bond pad also includes being located at diffusion impervious layer, in the side wall of the pad, positioned at institute
State between pad and the clearance wall.
The present invention in current technological process, is not influenceing to pattern to solve problems of the prior art
Density（pattern density）In the case of, do not increasing engagement（Bonding）In the case of alignment precision, increase engagement
（bonding）The process window of technique.
Etched in the present invention in metal valley（Cu trench etch）After completion, increase clearance wall（spacer）Work
Skill；In Cu CMP and then part（partial）Etch clearance wall（spacer）, form groove；By the gap for increasing depression
Wall（recessed spacer）So that in Cu-Cu engaging processes, the Cu squeezed out can be flowed into the clearance wall shape of depression
Into groove in, avoid at present Cu-Cu engage（Bonding）During, during heat pressing process, Cu extension is made
Into the connection of adjacent C u pads, ensure in the case of existing Cu pad densities, ensure alignment enough and to spare at present（overlay
margin）In the case of, increase the process window of joint technology.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (15)
1. a kind of preparation method of semiconductor devices, including：
Substrate is provided, formed with interlayer dielectric layer in the substrate；
The interlayer dielectric layer is patterned, to form bond pad groove in the interlayer dielectric layer；
Clearance wall is formed in the side wall of the bond pad groove；
The bond pad groove is filled from bond pad material, to form bond pad；
The clearance wall is etched, to remove the part clearance wall, the shape between the interlayer dielectric layer and the bond pad
Into groove.
2. according to the method for claim 1, it is characterised in that the forming method of the clearance wall includes：
In the interlayer dielectric layer, the bond pad recess sidewall and bottom deposit spacer material layer；
Etching removes the interlayer dielectric layer, the spacer material layer of the bond pad bottom portion of groove, to be connect described
Close and form clearance wall in the side wall of pad recess.
3. according to the method for claim 1, it is characterised in that forming the method for the bond pad includes：
Copper diffusion barrier layer is formed in the bond pad groove；
Deposited metal Cu Seed Layer, and Ni metal is formed by the method for Cu electroplating, it is recessed to fill the bond pad
Groove；
Planarisation step is performed, to obtain highly homogeneous bond pad.
4. the method according to claim 1 or 3, it is characterised in that the height of the bond pad is more than the clearance wall
With the height of the interlayer dielectric layer, in order to the engagement between pad.
5. according to the method for claim 1, it is characterised in that there is high etching selectivity from the interlayer dielectric layer
Method etch-back described in clearance wall, will the spacer etch to following at the top of the interlayer dielectric layer, formed described recessed
Groove.
6. according to the method for claim 1, it is characterised in that the clearance wall selects Si3N4, TiN, low-K material or carbon
Sill.
7. according to the method for claim 6, it is characterised in that the carbon-based material includes oxide or SiN.
8. according to the method for claim 6, it is characterised in that the carbon-based material includes SiON.
9. the method according to claim 1 or 6, it is characterised in that the interlayer dielectric layer selects SiO2；
When the clearance wall selects Si3N4When, dry etching of the etching from low-power；
When the clearance wall selects low-K material, DHF is selected in the etching；
When the clearance wall selects TiN materials, H is selected in the etching2O2；
When the clearance wall selects carbon-based material, epoxide dry etching is selected in the etching.
10. according to the method for claim 1, it is characterised in that the width of the clearance wall is the bond-pad width
5%~25%.
11. according to the method for claim 1, it is characterised in that methods described still further comprises：
The first wafer and the second wafer are provided, wherein the bond pad of first wafer and/or second wafer includes institute
State groove；
First wafer and second wafer are cleaned, remove the oxide that surface is formed；
Then the bond pad in the bond pad in first wafer and second wafer is subjected to low temperature and pressure engagement；
Perform annealing steps.
12. according to the method for claim 11, it is characterised in that the temperature of the low temperature and pressure engagement is 300-400 DEG C,
Engaging time is 30-90 minutes, activating pressure 30-60KN.
13. according to the method for claim 11, it is characterised in that described to be annealed into process annealing, annealing temperature 300-
400 DEG C, the time is 30-90 minutes.
14. a kind of semiconductor devices, including：
Substrate；
Interlayer dielectric layer, in the substrate；
Bond pad, in the interlayer dielectric layer, its height is higher than the height of the interlayer dielectric layer；
Groove, between the interlayer dielectric layer and the bond pad；
The semiconductor devices also includes clearance wall, between the bond pad and the interlayer dielectric layer, positioned at described
The lower section of groove.
15. semiconductor devices according to claim 14, it is characterised in that the semiconductor devices also includes diffusion barrier
Layer, in the side wall of the bond pad, between the pad and the clearance wall.
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