CN113948456A - Semiconductor substrate filling method, chip, device and material filling equipment - Google Patents

Semiconductor substrate filling method, chip, device and material filling equipment Download PDF

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Publication number
CN113948456A
CN113948456A CN202111105551.0A CN202111105551A CN113948456A CN 113948456 A CN113948456 A CN 113948456A CN 202111105551 A CN202111105551 A CN 202111105551A CN 113948456 A CN113948456 A CN 113948456A
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China
Prior art keywords
groove
filling
substrate
substrate layer
layer
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CN202111105551.0A
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Chinese (zh)
Inventor
王俊杰
陈建勋
蔡旻錞
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202111105551.0A priority Critical patent/CN113948456A/en
Publication of CN113948456A publication Critical patent/CN113948456A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a semiconductor substrate filling method, a chip, a device and material filling equipment adopting the method, which are suitable for integrated circuit wire interconnection operation and related application scenes. The invention overcomes the technical prejudice, adopts the closed-loop filling process and the heat treatment process, and repeatedly carries out the filling operation, so that the material filling quality of the workpiece is improved.

Description

Semiconductor substrate filling method, chip, device and material filling equipment
Technical Field
The invention belongs to the technical field of microelectronic circuits, and particularly relates to a semiconductor substrate filling method, a chip and a device adopting the method, and material filling equipment.
Background
As the physical dimensions of microelectronic circuitry are approaching the limits of moore's law, filling process trenches after etching becomes increasingly difficult.
The inventor researches and discovers that: on one hand, the filling process has the phenomenon of poor step coverage due to the size of the groove; on the other hand, the oxidized surface of the process groove is not beneficial to ensuring the uniformity of the plating layer in the subsequent electroplating process.
Disclosure of Invention
The invention discloses a semiconductor substrate filling method, a chip, a device and material filling equipment adopting the method, which are suitable for integrated circuit wire interconnection operation and related application scenes.
It should be noted that the terms "first", "second", and the like used in the present invention are only used for describing each constituent element in the technical solution, and do not constitute a limitation on the technical solution, and cannot be understood as an indication or suggestion of the importance of the corresponding element; an element in the similar language "first", "second", etc. means that in the corresponding embodiment, the element includes at least one.
The invention discloses a semiconductor substrate filling method, which comprises the steps of obtaining a first substrate through an etching process, and using the substrate for constructing a preset semiconductor structure; the process may include any desired process flow in a semiconductor manufacturing process.
Further, a first trench with a barrier layer is obtained on the first substrate through a first filling process, and the first trench is filled with a first base layer, namely a seed layer, for post-process operation.
The first substrate layer is attached to the surface of the first groove, and the distance from the opening surface of the bottom of the first substrate layer to the notch plane of the first groove is the first groove depth; when the depth is zero, it indicates that the first trench is filled.
Further, annealing and refluxing the first groove to enable the first substrate layer to generate reflux and enable the side wall of the first groove to be perpendicular to the notch plane of the first groove; in general, in order to save the energy consumption of the process, the prior art directly enters the electroplating process without performing the subsequent filling.
However, the inventor finds that the single filling process has difficulty in ensuring the filling quality because the size of the workpiece is reduced continuously and the order of 10 nanometers is solved. The filling amount of single filling is reduced, and multiple filling is performed to the contrary, so that the related technical bias is overcome, and unexpected technical effects are achieved: if the open surface of the bottom of the first substrate layer is lower than the second groove depth preset by the notch plane of the first groove, filling the first groove depth by the first filling process again and performing annealing reflux treatment again; and if the open surface of the bottom of the first substrate layer and the notch plane of the first groove accord with the preset second groove depth, ending the filling process.
Further, when the first substrate takes a semiconductor material as a first base material, etching a first groove on the first base material, and enabling a first end of the first groove to be open and a second end to be closed; wherein the second end is filled with a conductor material; for substrates obtained with a process not greater than 28 nm, the method is more advantageously applicable.
Further, the method is naturally applicable to the use of silicon and germanium materials. Additionally, the method is only effective when the value of the first groove depth is larger than the thickness value of each filling in the first filling process. The method is also suitable for the technological process adopting different filling materials, wherein the filling material can adopt at least one of gold, silver, copper and aluminum.
Meanwhile, the first filling process can adopt a chemical vapor deposition and/or physical vapor deposition method, as long as the method can accurately control the growth amount of the filler.
Further, the depth of the second trench may be zero or negative, which respectively represents different process states, and when the depth of the second trench is negative, it represents that the first trench is filled to generate a protrusion.
Still further, as a necessary process indicator, the annealing temperature must be sufficient to reflow the conductor; the aim is to eliminate the disadvantageous structural state of the surface of the part after filling. Particularly, the annealing temperature is 220-550 ℃, and the specific material is improved.
Further, in order to improve the electroplating effect, the first substrate layer may be subjected to a reduction treatment to remove the surface oxide layer. Thereafter, the first base layer may be subjected to an electroplating operation.
Wherein the first substrate layer is subjected to an electroplating operation until the plating thickness of the first substrate layer is increased to a predetermined process value. In order to further improve the quality of the workpiece after the electroplating operation, a chemical mechanical polishing process can be adopted for surface treatment.
On the basis of this, it is natural that the chip adopting the above method falls into the protection scope of the present invention in the manufacturing process. It is also within the scope of the present invention for the corresponding production apparatus to employ any of the above-described methods.
Still further, if the material filling equipment is operated based on the above-mentioned process, it will also fall into the protection scope of the present invention. The preprocessing unit is used for detecting a first substrate obtained by an etching process and using the first substrate to construct a preset semiconductor structure; the material filling unit is used for detecting a first groove with a barrier layer obtained on a first substrate through a first filling process, and filling the first groove with a first substrate layer used for a subsequent process.
The first substrate layer is attached to the surface of the first groove, and the distance from the opening surface of the bottom of the first substrate layer to the notch plane of the first groove is the first groove depth; the detection and heat treatment unit carries out annealing reflux treatment on the first groove, so that the first substrate layer generates reflux, and the side wall of the first groove is perpendicular to the notch plane of the first groove.
The process control unit controls the execution process of the detection and heat treatment unit according to the process requirement, and if the open surface of the bottom of the first substrate layer is lower than a second groove depth preset by the notch plane of the first groove, the first filling process is used for filling again, and annealing reflux treatment is carried out again; and if the open surface of the bottom of the first substrate layer and the notch plane of the first groove accord with the preset second groove depth, ending the filling process.
The invention discloses a semiconductor substrate filling method, a chip, a device and material filling equipment adopting the method, which are suitable for integrated circuit wire interconnection operation and related application scenes; by overcoming the technical prejudice, the filling operation is repeatedly carried out by adopting a closed-loop filling process and a heat treatment process, so that the material filling quality of the workpiece is improved.
Drawings
To more clearly illustrate the technical solutions of the present invention and to facilitate further understanding of the technical effects, technical features and objects of the present invention, the present invention will be described in detail with reference to the accompanying drawings, which form an essential part of the specification, and which are used together with the embodiments of the present invention to illustrate the technical solutions of the present invention, but do not limit the present invention.
The same reference numerals in the drawings denote the same elements, and in particular:
FIG. 1 is a schematic structural view before a filling operation in example 1 of the present invention;
FIG. 2 is a schematic structural diagram of an intermediate state after a certain filling operation in embodiment 1 of the present invention;
FIG. 3 is a schematic structural diagram of an intermediate state after annealing and reflowing after a certain filling operation in example 1 of the present invention;
FIG. 4 is a schematic structural view after completion of the filling operation in example 1 of the present invention;
FIG. 5 is a process flow diagram of example 2 of the material filling apparatus of the present invention.
Wherein:
100 — a first substrate; 200 — a first substrate layer;
300-a first groove; 400- -a barrier layer; 500- - -a second substrate;
1000- -Process initialization; 2000- -first fill process;
3000- -detection and heat treatment process; 4000-repeated check fill process.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. Of course, the following specific examples are provided only for explaining the technical solutions of the present invention, and are not intended to limit the present invention.
In addition, the portions shown in the embodiments or the drawings are only illustrations of the relevant portions of the present invention, and are not all of the present invention.
As shown in fig. 1, a schematic structural view before filling operation in embodiment 1 of the present invention; to avoid the penetration of the filler material into the workpiece, a barrier layer 400 is added; where the second substrate 500 is other structural or semiconductor material, the second substrate 500 provides physical support for the relevant structures or components of the present embodiment.
As shown in fig. 2, a first substrate 100 obtained through an etching process is used to construct a predetermined semiconductor structure; the first trenches 300 with the barrier layer 400 are filled with the first substrate layer 200, i.e., the seed layer, for post-process operations.
Wherein, the first substrate layer 200 is attached to the surface of the first trench 300, and the distance from the open surface of the bottom of the first substrate layer 200 to the notch plane of the first trench 300 is the first groove depth; the depth is used for judging whether the filling operation has reached the process requirement, and when the depth is zero or negative, the workpiece completes the filling operation.
If the filling operation is not satisfactory, the first substrate layer 200 is reflowed by performing an annealing reflow process on the first trench 300, and the sidewall of the first trench 300 is perpendicular to the notch plane of the first trench 300.
If the open surface of the bottom of the first substrate layer 200 is lower than the second groove depth preset in the notch plane of the first trench 300, the first filling process is performed again to fill the first substrate layer and the annealing reflow process is performed again.
If the open surface of the bottom of the first substrate layer 200 and the notch plane of the first trench 300 conform to the predetermined second trench depth, the filling process is ended.
As shown, the first substrate 100 has a semiconductor material as a first base material, and a first trench 300 is etched on the base material; the first trench 300 is open at a first end and closed at a second end, which is filled with a conductor material. The method is particularly useful for high density workpieces of the first substrate 100, and is typically obtained using processes not greater than 28 nm, and is applicable to both silicon and germanium materials.
As described above, the value of the first groove depth is larger than the thickness value of each filling of the first filling process, that is, by controlling the filling depth, the filling process is not completed once, that is, by controlling the filling amount, the improvement of the quality of the workpiece in the filling process is achieved.
Furthermore, the invention is also applicable to filling materials such as gold, silver, copper and aluminum, and is particularly beneficial to improving copper materials with higher expansion rate.
Further, the first filling process of the present invention adopts a chemical vapor deposition and/or physical vapor deposition method, which is beneficial to the precise control of the filling process.
As described above, the depth of the second groove is zero or negative, and when the depth of the second groove is negative, the first groove is filled to generate a protrusion.
To achieve process results, the annealing temperature should be sufficient to reflow the conductor so that the workpiece characteristics, structure, shape, etc. are improved.
The data show that when the annealing temperature is 220-550 ℃, a better heat treatment effect can be generated on the copper metal.
Further, in order to improve the electroplating effect, the first substrate layer 200 may be subjected to a reduction process to remove a surface oxide layer.
Further, the electroplating operation is performed on the first substrate layer 200 until the plating thickness of the first substrate layer 200 is increased by a predetermined process value, further improving the conductive performance of the conductor.
Furthermore, the surface treatment is carried out by adopting a chemical mechanical polishing process after the electroplating operation, so that the structure and the electrical property of the workpiece are further improved.
As shown in fig. 1 to 5; fig. 5 shows a material filling apparatus using the method of the present invention, wherein a preprocessing unit 1000 is used for inspecting the first substrate 100 obtained by the etching process and using it for building a predetermined semiconductor structure.
The material filling unit 2000 is used for detecting that the first trench 300 with the barrier layer is obtained on the first substrate 100 through the first filling process, and filling the first trench 300 with the first base layer 200 for a subsequent process.
The first substrate layer 200 is attached to the surface of the first groove 300, and the distance from the open surface of the bottom of the first substrate layer 200 to the notch plane of the first groove 300 is the first groove depth.
The inspection and heat treatment unit 3000 performs an annealing reflow process on the first trench 300 to reflow the first substrate layer 200 and make the sidewall of the first trench 300 perpendicular to the notch plane of the first trench 300.
The process control unit 4000 controls the execution process of the detection and thermal treatment unit 3000 according to the process requirements, and if the open surface of the bottom of the first substrate layer 200 is lower than the second groove depth preset in the notch plane of the first trench 300, the first filling process is performed again to fill the open surface and the annealing reflow process is performed again.
If the open surface of the bottom of the first substrate layer 200 and the notch plane of the first trench 300 conform to the predetermined second trench depth, the filling process is ended. .
It should be noted that the above examples are only for clearly illustrating the technical solutions of the present invention, and those skilled in the art will understand that the embodiments of the present invention are not limited to the above contents, and obvious changes, substitutions or replacements can be made based on the above contents without departing from the scope covered by the technical solutions of the present invention; other embodiments will fall within the scope of the invention without departing from the inventive concept.

Claims (16)

1. A method of filling a semiconductor substrate, comprising:
obtaining a first substrate (100) through an etching process; the first substrate (100) is used for building a predetermined semiconductor structure;
obtaining a first trench (300) with a barrier layer (400) on the first substrate (100) through a first filling process, wherein the first trench (300) is filled with a first base layer (200) for post-process operation, and the first base layer (200) is defined as a seed layer; wherein the content of the first and second substances,
the first substrate layer (200) is attached to the surface of the first groove (300), and the distance from the opening surface of the bottom of the first substrate layer (200) to the notch plane of the first groove (300) is a first groove depth;
performing annealing reflow treatment on the first groove (300), so that the first substrate layer (200) generates reflow, and the side wall of the first groove (300) is perpendicular to the notch plane of the first groove (300);
if the open surface of the bottom of the first substrate layer (200) is lower than a second groove depth preset by the notch plane of the first groove (300), filling by the first filling process again and performing annealing reflux treatment again;
ending the filling process if the open face of the bottom of the first substrate layer (200) and the notch plane of the first trench (300) conform to a predetermined second trench depth.
2. The method of claim 1, wherein:
the first substrate (100) takes a semiconductor material as a first base material, and the first groove (300) is etched on the first base material;
a first end of the first trench (300) is open;
the first trench (300) is closed at a second end, which is filled with a conductor material.
3. The method of claim 1 or 2, wherein:
the first substrate (100) is obtained by a process not greater than 28 nm.
4. The method of claim 1 or 2, wherein:
the semiconductor material is at least one of the following materials: silicon, germanium.
5. The method of claim 1 or 2, wherein:
the value of the first groove depth is larger than the thickness value of each filling of the first filling process.
6. The method of claim 2, wherein:
the conductor is made of at least one of the following materials: gold, silver, copper, aluminum.
7. The method of claim 1 or 6, wherein:
the first filling process adopts a chemical vapor deposition and/or physical vapor deposition method.
8. The method of claim 7, wherein:
the depth of the second groove depth is zero or negative, and when the second groove depth is negative, a bulge is generated after the first groove is filled.
9. The method of claim 4, wherein:
the annealing temperature is sufficient to cause reflow of the conductor.
10. The method of claim 9, wherein:
the annealing temperature is 220-550 ℃.
11. The method of claim 9 or 10, further comprising:
and carrying out reduction treatment on the first substrate layer (200) to eliminate a surface oxidation layer.
12. The method of claim 11, wherein:
-performing an electroplating operation on the first base layer (200); wherein the first substrate layer (200) is subjected to an electroplating operation until the plating thickness of the first substrate layer (200) increases by a predetermined process value.
13. The method of claim 9,
and carrying out surface treatment by adopting a chemical mechanical polishing process after the electroplating operation.
14. A chip, characterized in that:
the method according to any one of claims 1 to 13 is used during the manufacture of the chip.
15. A semiconductor manufacturing apparatus, characterized in that:
the production device employs the method of any one of claims 1 to 13.
16. A material filling apparatus, comprising: the device comprises a pretreatment unit (1000), a material filling unit (2000), a detection and heat treatment unit (3000) and a process control unit (4000); wherein the content of the first and second substances,
pretreatment unit (1000): for inspecting the first substrate obtained by the etching process and using it for building a predetermined semiconductor structure;
material filling unit (2000): the method comprises the steps of detecting a first groove with a barrier layer obtained on a first substrate through a first filling process, and filling the first groove with a first substrate layer for a subsequent process; the first substrate layer is attached to the surface of the first groove, and the distance from the opening surface of the bottom of the first substrate layer to the notch plane of the first groove is a first groove depth;
detection and thermal treatment unit (3000): carrying out annealing reflow treatment on the first groove to enable the first substrate layer to generate reflow, and enabling the side wall of the first groove to be perpendicular to the notch plane of the first groove;
process control unit (4000): controlling the execution process of the detection and heat treatment unit (3000) according to the process requirements, and if the open surface of the bottom of the first substrate layer is lower than a second groove depth preset by the notch plane of the first groove, filling the first substrate layer by a first filling process again and performing the annealing reflux treatment again; and if the open surface of the bottom of the first substrate layer and the notch plane of the first groove accord with a preset second groove depth, ending the filling process.
CN202111105551.0A 2021-09-22 2021-09-22 Semiconductor substrate filling method, chip, device and material filling equipment Pending CN113948456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111105551.0A CN113948456A (en) 2021-09-22 2021-09-22 Semiconductor substrate filling method, chip, device and material filling equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111105551.0A CN113948456A (en) 2021-09-22 2021-09-22 Semiconductor substrate filling method, chip, device and material filling equipment

Publications (1)

Publication Number Publication Date
CN113948456A true CN113948456A (en) 2022-01-18

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