CN110504211A - Improve the process of the mound shape bump defects of top copper interconnection layer - Google Patents
Improve the process of the mound shape bump defects of top copper interconnection layer Download PDFInfo
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- CN110504211A CN110504211A CN201910810022.7A CN201910810022A CN110504211A CN 110504211 A CN110504211 A CN 110504211A CN 201910810022 A CN201910810022 A CN 201910810022A CN 110504211 A CN110504211 A CN 110504211A
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- layer
- copper
- interconnection layer
- copper interconnection
- improving
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
Abstract
The invention discloses a kind of processes of mound shape bump defects for improving top copper interconnection layer, comprising: Step 1: forming top copper interconnection layer on a semiconductor substrate；Step 2: forming copper overflows neutralizing layer, the growth temperature that copper overflows neutralizing layer is lower than the growth temperature on subsequent etching barrier layer, so that copper is overflowed copper spill-out in neutralizing layer growth course and reduces or eliminates；While it is compact medium layer that copper, which overflows neutralizing layer, makes to be formed no longer generation copper when copper spilling neutralizing layer carries out the growth technique of subsequent etching barrier layer again later and overflows；Step 3: forming etching barrier layer.The mound shape bump defects of the mound shape bump defects of copper interconnection layer, especially top copper interconnection layer can be effectively reduced in the present invention.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, in particular to a kind of mound shape for improving copper interconnection layer is convex
Play the process of (hillock) defect.
Background technique
With the development of integrated circuit fabrication process and the diminution of critical size, many new methods are applied to device
In manufacturing process, to improve device performance, silicon nitride because its have good Etch selectivity, good copper adhesiveness and
It is good to stop the properties such as diffusion of the copper between interface and be widely used.
In report so far, researchers think that only increase silicon nitride could preferably to the adhesiveness on copper surface
Diffusion of the copper between interface is suppressed, is used to increase pre-treatment step after being mostly conceived to chemomechanical copper grinding (CMP)
Remove as copper it is exposed caused by copper oxide, to contact resistance between reducing interface and prevent diffusion of the copper between interface
Phenomenon, existing 65 nanometers, all can deposited silicon nitride after top layer copper CMP in the process nodes such as 55nm, 40nm, 28nm and 22nm
Film a large amount of hillock defects inevitably can all occur after silicon nitride film deposition as etching barrier layer.
Gradually downward with process node, more seriously reach 250000 or more to 40nm node copper hillock defect,
And copper hillock defect always exists the weaker copper penetration phenomenon of corner region, and copper penetration phenomenon process node by
Become shorter and shorter at a distance from copper wire due to copper wire when gradually downward, so that the risk for causing electric current to puncture shown can be got over
Come bigger.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of works of mound shape bump defects for improving top copper interconnection layer
The mound shape bump defects of top copper interconnection layer can be effectively reduced in process.
In order to solve the above technical problems, the technique side of the mound shape bump defects provided by the invention for improving top copper interconnection layer
Method includes the following steps:
Step 1: forming top copper interconnection layer on a semiconductor substrate, the top copper interconnection layer includes multiple copper lines
Figure is isolated between the copper lines figure by interlayer film, formed after the top copper interconnection layer copper lines figure and
Expose on the surface of the interlayer film.
Step 2: forming copper on the semiconductor substrate overflows neutralizing layer, the copper overflows the growth temperature of neutralizing layer
Lower than the growth temperature on subsequent etching barrier layer, so that the copper is overflowed copper spill-out in neutralizing layer growth course and reduce or eliminate；
It is compact medium layer that the copper, which overflows neutralizing layer, simultaneously, makes to carry out again the subsequent quarter after forming the copper spilling neutralizing layer
Copper is no longer generated when losing the growth technique on barrier layer to overflow.
The etching barrier layer is formed in compacting layer surface Step 3: overflowing in the copper.
A further improvement is that the semiconductor substrate is silicon substrate.
A further improvement is that the top copper interconnection layer bottom also has one layer or more of bottom copper interconnection layer, it is described
The corresponding interlayer film of top copper interconnection layer is top layer interlayer film.
A further improvement is that top copper interconnection layer described in step 1 is formed using Damascus technics.
A further improvement is that step 1 include it is following step by step:
Form top layer interlayer film.
The corresponding through-hole of the copper lines figure or groove are formed in the top layer interlayer film.
Plating forms the top copper interconnection layer, and the top copper interconnection layer fills the through-hole or groove and extends to institute
It states in the top layer interlayer film surface outside through-hole or groove.
Chemical mechanical grinding is carried out to the top copper interconnection layer, after the chemical mechanical grinding outside the through-hole or groove
The top layer interlayer film surface on the top copper interconnection layer be removed, the top layer copper in the through-hole or groove is mutual
Even layer is equal with the surface of the top layer interlayer film, is made of the top copper interconnection layer being filled in the through-hole or groove
The graph line figure.
A further improvement is that further include after the completion of step 1 and before step 2 to pretreated step, it is described
Pre-process the copper oxide formed for removing the exposed copper interconnection layer surface.
A further improvement is that the pretreatment removes the copper oxide using ammonia plasmas.
A further improvement is that the interlayer film is lower than the low dielectric of silica using silicon dioxide layer or dielectric constant
Dielectric layer.
A further improvement is that it is carbon dope silicon nitride (NDC) that copper described in step 2, which overflows neutralizing layer,.
A further improvement is that growing the compact medium layer using pecvd process in step 2.
A further improvement is that the compact medium layer with a thickness of
A further improvement is that the temperature for forming the compact medium layer in step 2 is 350 DEG C.
A further improvement is that etching barrier layer described in step 3 is silicon nitride, the growth temperature of the etching barrier layer
Degree is 400 DEG C or more.
A further improvement is that being formed with semiconductor devices, semiconductor devices on the semiconductor substrate in step 1
Process node be 65nm or less.
A further improvement is that the process node of the semiconductor devices includes 65nm, 55nm, 40nm, 28nm and 22nm.
Since the block structure of the copper lines figure of top copper interconnection layer is larger, if after forming top copper interconnection layer
Etching barrier layer such as silicon nitride is directly formed, then biggish bulk under the action of such as 400 DEG C of the growth temperature of etching barrier layer
The top copper interconnection layer of structure is easy to produce copper and overflows and formed mound shape bump defects, and for these technical problems, the present invention exists
It is formed after top copper interconnection layer in semiconductor substrate, does not directly adopt instead of and generate etching barrier layer compared with Seedling height temperature,
The copper that growth temperature is initially formed lower than etching barrier layer overflows neutralizing layer, so that copper is overflowed neutralizing layer using reduced growth temperature raw
Copper spill-out reduces or eliminates in growth process；It is compact medium layer that copper, which overflows neutralizing layer, simultaneously, make to be formed copper overflow neutralizing layer it
It no longer generates copper when carrying out the growth technique of the subsequent etching barrier layer again afterwards to overflow, so the present invention can substantially reduce top
The copper of layer copper interconnection layer, which is overflowed and reduced, overflows generated mound shape bump defects by copper, can finally improve product yield.
It can be realized in addition, the present invention need to only form copper spilling neutralizing layer before etching barrier layer formation, simple process
It is and at low cost, it is easy to accomplish.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the structure chart for forming etching barrier layer in existing copper interconnection process method after the formation of top layer copper；
Fig. 2 is the flow chart of the process for the mound shape bump defects that the embodiment of the present invention improves top copper interconnection layer；
Fig. 3 is the device architecture schematic diagram in present invention method.
Specific embodiment
First, applicant carries out for example following analysis to the prior art, is described below:
As shown in Figure 1, being the structure for forming etching barrier layer in existing copper interconnection process method after the formation of top layer copper
Figure is formed with etching barrier layer 102 on the surface of top layer copper 101, and etching barrier layer 102 generallys use silicon nitride film composition,
Etching barrier layer 102 can also be covered on the surface of the interlayer film (not shown) outside top layer copper 101.Substantially, hillock defect
Caused by mechanism be and to use Jie of the low-k of package copper as in order to meet capacitive reactance caused by lower dielectric layer
Electric layer, and the dielectric layer of low-k often has more loose characteristic, loose dielectric layer bring side effect is
It is difficult to suppress the spilling of copper wire and cause hillock defect under high temperature or other external factor.
Present invention method:
As shown in Fig. 2, being the stream of the process for the mound shape bump defects that the embodiment of the present invention improves top copper interconnection layer
Cheng Tu；As shown in figure 3, being the device architecture schematic diagram in present invention method；In order to solve the above technical problems, of the invention
The process of the mound shape bump defects of the improvement top copper interconnection layer of offer includes the following steps:
Step 1: forming top copper interconnection layer 1 on a semiconductor substrate, the top copper interconnection layer 1 includes multiple copper wire
Figure is isolated between the copper lines figure by interlayer film, forms the copper lines figure after the top copper interconnection layer 1
Expose with the surface of the interlayer film.
In present invention method, the semiconductor substrate is silicon substrate.It is formed with half on the semiconductor substrate
Conductor device, the process node of semiconductor devices are 65nm hereinafter, for example: the process node of semiconductor devices include 65nm,
55nm, 40nm, 28nm and 22nm.
1 bottom of top copper interconnection layer also has one layer or more of bottom copper interconnection layer, and the top copper interconnection layer 1 is right
The interlayer film answered is top layer interlayer film.
Top copper interconnection layer 1 described in step 1 is formed using Damascus technics.
A further improvement is that step 1 include it is following step by step:
Form top layer interlayer film.
The corresponding through-hole of the copper lines figure or groove are formed in the top layer interlayer film.
Plating forms the top copper interconnection layer 1, and the top copper interconnection layer 1 is filled the through-hole or groove and extended to
In the top layer interlayer film surface outside the through-hole or groove.
Chemical mechanical grinding, the through-hole or groove after the chemical mechanical grinding are carried out to the top copper interconnection layer 1
The top copper interconnection layer 1 in the outer top layer interlayer film surface is removed, the top layer in the through-hole or groove
Copper interconnection layer 1 is equal with the surface of the top layer interlayer film, by the top layer copper-connection being filled in the through-hole or groove
The 1 composition graph line figure of layer.
It further include to pretreated step after the completion of step 1 and before step 2, the pretreatment is sudden and violent for removing
The copper oxide that 1 surface of the copper interconnection layer of dew is formed.Such as: the pretreatment is removed described using ammonia plasmas
Copper oxide.
The interlayer film is lower than the low dielectric layer of silica using silicon dioxide layer or dielectric constant, and low dielectric is situated between
Matter layer may include fluorine-doped silica (FSG), carbon doped silicon oxide (SiOC) and black diamond (black diamond) etc..
Step 2: forming copper on the semiconductor substrate overflows neutralizing layer 2, the copper overflows the growth temperature of neutralizing layer 2
Degree is lower than the growth temperature on subsequent etching barrier layer 3, so that the copper is overflowed copper spill-out in 2 growth course of neutralizing layer and reduces or disappear
It removes；It is compact medium layer that the copper, which overflows neutralizing layer 2, simultaneously, makes to carry out again after forming the copper spilling neutralizing layer 2 subsequent
Copper is no longer generated when the growth technique of the etching barrier layer 3 to overflow.
It is preferably selected as, the copper overflows the silicon nitride (NDC) that neutralizing layer 2 is carbon dope.Described in being grown using pecvd process
Copper overflows neutralizing layer 2, carries out the pecvd process growth copper spilling pressure for example, by using the Express board of general woods (Lam) company
Preparative layer 2.It is passed through corresponding nitrogen source, carbon source and silicon source progress PECVD in pecvd process cavity to react to form NDC, such as uses four
Methyl-monosilane (TMS) and ammonia, which carry out PECVD reaction, can form NDC.
The copper overflow neutralizing layer 2 with a thickness ofForming the copper to overflow the temperature of neutralizing layer 2 is 350 DEG C.
The etching barrier layer 3 is formed on 2 surface of neutralizing layer Step 3: overflowing in the copper.The etching barrier layer 3 is
Silicon nitride, the growth temperature of the etching barrier layer 3 are 400 DEG C or more.In general, the top of the top copper interconnection layer 1 also
It will form aluminium through-hole and corresponding interlayer film, the etching barrier layer 3 is as the logical of the top for forming the top copper interconnection layer 1
The barrier layer when etching in hole.
Since the block structure of the copper lines figure of top copper interconnection layer 1 is larger, if formed top copper interconnection layer 1 it
Directly form such as silicon nitride of etching barrier layer 3 afterwards, then it is biggish under the action of such as 400 DEG C of the growth temperature of etching barrier layer 3
The top copper interconnection layer 1 of block structure is easy to produce copper and overflows and form mound shape bump defects, for these technical problems, this hair
Bright embodiment is formed on a semiconductor substrate after top copper interconnection layer 1, is not to directly adopt to generate compared with Seedling height temperature to etch
Barrier layer 3, but the copper for being initially formed growth temperature lower than etching barrier layer 3 overflows neutralizing layer 2, is made using reduced growth temperature
Copper overflows copper spill-out in 2 growth course of neutralizing layer and reduces or eliminates；It is compact medium layer that copper, which overflows neutralizing layer 2, simultaneously, makes shape
It is overflowed when neutralizing layer 2 carries out the growth technique of the subsequent etching barrier layer 3 again later at copper and no longer generates copper spilling, so
The copper that the embodiment of the present invention can substantially reduce top copper interconnection layer 1, which overflows and reduces the mound shape protrusion caused by copper spilling, to be lacked
It falls into, can finally improve product yield.
It can be realized in addition, the embodiment of the present invention need to only form copper spilling neutralizing layer 2 before the formation of etching barrier layer 3,
Simple process and at low cost, it is easy to accomplish.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of process for the mound shape bump defects for improving top copper interconnection layer, which comprises the steps of:
Step 1: forming top copper interconnection layer on a semiconductor substrate, the top copper interconnection layer includes multiple copper lines figures,
It is isolated between the copper lines figure by interlayer film, forms the copper lines figure and the layer after the top copper interconnection layer
Between film surface expose；
Step 2: forming copper on the semiconductor substrate overflows neutralizing layer, the growth temperature that the copper overflows neutralizing layer is lower than
The growth temperature on subsequent etching barrier layer makes the copper overflow copper spill-out in neutralizing layer growth course and reduces or eliminates；Simultaneously
It is compact medium layer that the copper, which overflows neutralizing layer, makes to carry out the subsequent etching resistance after forming the copper spilling neutralizing layer again
Copper is no longer generated when the growth technique of barrier to overflow；
The etching barrier layer is formed in compacting layer surface Step 3: overflowing in the copper.
2. improving the process of the mound shape bump defects of top copper interconnection layer as described in claim 1, it is characterised in that: institute
Stating semiconductor substrate is silicon substrate.
3. improving the process of the mound shape bump defects of top copper interconnection layer as claimed in claim 2, it is characterised in that: institute
State top copper interconnection layer bottom also and have one layer or more of bottom copper interconnection layer, the corresponding interlayer film of the top copper interconnection layer is
Top layer interlayer film.
4. improving the process of the mound shape bump defects of top copper interconnection layer as claimed in claim 3, it is characterised in that: step
Top copper interconnection layer described in rapid one is formed using Damascus technics.
5. improving the process of the mound shape bump defects of top copper interconnection layer as claimed in claim 4, it is characterised in that: step
Rapid one include it is following step by step:
Form top layer interlayer film；
The corresponding through-hole of the copper lines figure or groove are formed in the top layer interlayer film；
Plating forms the top copper interconnection layer, and the top copper interconnection layer is filled the through-hole or groove and extended to described logical
In the top layer interlayer film surface outside hole or groove；
Chemical mechanical grinding is carried out to the top copper interconnection layer, the institute after the chemical mechanical grinding outside the through-hole or groove
The top copper interconnection layer stated in top layer interlayer film surface is removed, the top copper interconnection layer in the through-hole or groove
It is equal with the surface of the top layer interlayer film, be made of the top copper interconnection layer being filled in the through-hole or groove described in
Graph line figure.
6. improving the process of the mound shape bump defects of top copper interconnection layer as claimed in claim 5, it is characterised in that: In
It further include to pretreated step after the completion of step 1 and before step 2, the pretreatment is for removing the exposed copper
The copper oxide that interconnection layer surfaces are formed.
7. improving the process of the mound shape bump defects of top copper interconnection layer as claimed in claim 6, it is characterised in that: institute
It states pretreatment and removes the copper oxide using ammonia plasmas.
8. improving the process of the mound shape bump defects of top copper interconnection layer as described in claim 1, it is characterised in that: institute
State the low dielectric layer that interlayer film is lower than silica using silicon dioxide layer or dielectric constant.
9. improving the process of the mound shape bump defects of top copper interconnection layer as described in claim 1, it is characterised in that: step
It is carbon dope silicon nitride that copper described in rapid two, which overflows neutralizing layer,.
10. improving the process of the mound shape bump defects of top copper interconnection layer as claimed in claim 9, it is characterised in that:
The compact medium layer is grown using pecvd process in step 2.
11. improving the process of the mound shape bump defects of top copper interconnection layer as claimed in claim 9, it is characterised in that:
The compact medium layer with a thickness of
12. improving the process of the mound shape bump defects of top copper interconnection layer as claimed in claim 10, it is characterised in that:
The temperature that the compact medium layer is formed in step 2 is 350 DEG C.
13. improving the process of the mound shape bump defects of top copper interconnection layer as described in claim 1, it is characterised in that:
Etching barrier layer described in step 3 is silicon nitride, and the growth temperature of the etching barrier layer is 400 DEG C or more.
14. improving the process of the mound shape bump defects of top copper interconnection layer as described in claim 1, it is characterised in that:
In step 1, it is formed with semiconductor devices on the semiconductor substrate, the process node of semiconductor devices is 65nm or less.
15. improving the process of the mound shape bump defects of top copper interconnection layer as claimed in claim 12, it is characterised in that:
The process node of the semiconductor devices includes 65nm, 55nm, 40nm, 28nm and 22nm.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111785747A (en) * | 2020-07-17 | 2020-10-16 | 上海华力集成电路制造有限公司 | CMOS protective layer structure and manufacturing method thereof |
| CN112038286A (en) * | 2020-08-27 | 2020-12-04 | 上海华力集成电路制造有限公司 | Method for improving hillock defect in copper interconnection process |
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| CN102881677A (en) * | 2012-09-24 | 2013-01-16 | 复旦大学 | Alloy copper diffusion barrier layer for copper interconnection and manufacturing method thereof |
| CN102881632A (en) * | 2011-07-13 | 2013-01-16 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN107895733A (en) * | 2017-11-16 | 2018-04-10 | 上海华力微电子有限公司 | A kind of method for reducing logical device metal and protruding defect |
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Patent Citations (4)
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| CN102881632A (en) * | 2011-07-13 | 2013-01-16 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN102543854A (en) * | 2012-01-18 | 2012-07-04 | 上海华力微电子有限公司 | Method for overcoming defect of copper bumps in copper interconnecting structure |
| CN102881677A (en) * | 2012-09-24 | 2013-01-16 | 复旦大学 | Alloy copper diffusion barrier layer for copper interconnection and manufacturing method thereof |
| CN107895733A (en) * | 2017-11-16 | 2018-04-10 | 上海华力微电子有限公司 | A kind of method for reducing logical device metal and protruding defect |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111785747A (en) * | 2020-07-17 | 2020-10-16 | 上海华力集成电路制造有限公司 | CMOS protective layer structure and manufacturing method thereof |
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