CN112038286A - Method for improving hillock defect in copper interconnection process - Google Patents
Method for improving hillock defect in copper interconnection process Download PDFInfo
- Publication number
- CN112038286A CN112038286A CN202010877270.6A CN202010877270A CN112038286A CN 112038286 A CN112038286 A CN 112038286A CN 202010877270 A CN202010877270 A CN 202010877270A CN 112038286 A CN112038286 A CN 112038286A
- Authority
- CN
- China
- Prior art keywords
- copper
- silicon carbide
- barrier layer
- carbide film
- improving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 77
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 77
- 239000010949 copper Substances 0.000 title claims abstract description 77
- 238000000034 method Methods 0.000 title claims abstract description 50
- 230000008569 process Effects 0.000 title claims abstract description 33
- 230000007547 defect Effects 0.000 title claims abstract description 27
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 32
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 238000000137 annealing Methods 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000005137 deposition process Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 5
- 230000000087 stabilizing effect Effects 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001125 extrusion Methods 0.000 description 2
- 230000008595 infiltration Effects 0.000 description 2
- 238000001764 infiltration Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 241000784732 Lycaena phlaeas Species 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
Abstract
The invention discloses a method for improving hillock-shaped bulge defects in a copper interconnection process, which comprises the following steps: step S1, forming a semiconductor device with a copper substrate pattern; step S2, depositing a 300-350 ℃ silicon carbide film on the surface of the semiconductor device as a copper overflow barrier layer; and S3, depositing the silicon carbide film, and then performing thermal annealing treatment by using a low-temperature furnace tube process at 300-350 ℃, and depositing a high-temperature silicon nitride film serving as an etching barrier layer on the surface of the copper overflow barrier layer in S4. According to the invention, a thin silicon carbide film is deposited at a low temperature before the silicon nitride film is deposited at a high temperature of 400 ℃ after copper CMP and is used as a copper overflow barrier layer, and low-temperature furnace tube annealing treatment is carried out after the copper overflow barrier layer is formed, so that copper overflow is blocked by using the silicon carbide layer, copper diffusion is reduced, the silicon carbide layer after annealing treatment can be better adhered to the copper surface, the copper property after annealing is more stable, the effect of stabilizing the copper surface is achieved, and the defect of the hillock-shaped bulge is further improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for improving hillock-shaped bulge defects in a copper interconnection process.
Background
With the development of the integrated circuit manufacturing process, the critical dimension of the device is smaller and smaller, the integration level is higher and higher, the line width of the metal interconnection line is continuously reduced, the occupied area and the cost of the metal interconnection line in the whole circuit are higher and higher, five to six layers of wiring are needed for the metal interconnection, and the influence of the back-end metal interconnection on the working speed, the power consumption and the like of the chip is larger and larger.
In back-end metal interconnection, due to the characteristics of low resistivity, strong electromigration resistance and the like of copper, aluminum metal is replaced, and the copper-based back-end metal interconnection is a material commonly adopted in the manufacturing of an interconnection layer of a semiconductor integrated circuit at present and becomes an industrial standard. To date, the mainstream 0.13 μm and below processes have used copper interconnect processes for back-end metal interconnects.
Because of the high reactivity of copper, preventing copper diffusion becomes critical, and many new methods are applied to device fabrication processes for improving device performance. Among them, silicon nitride is widely used because of its properties such as good etching selectivity, good copper adhesion, and capability of blocking copper diffusion between interfaces.
In the reports so far, researchers generally believe that the diffusion of copper between interfaces is better suppressed only by increasing the adhesion of silicon nitride to the copper surface, and therefore, most have focused on the addition of a pretreatment step after copper CMP (chemical mechanical polishing) to remove the copper oxide layer due to copper denuded, thereby reducing the contact resistance between interfaces and preventing the diffusion phenomenon of copper between interfaces.
In the current process node of 65/55/40/28/22nm and the like, a silicon nitride film (usually under a process condition of 400 ℃) is deposited as an etching barrier layer after the top copper CMP, as shown in FIG. 1, and a large amount of hillock defects inevitably occur after the silicon nitride film is deposited, as shown in FIG. 2 b. In essence, the reason for the hillock defect is that the hillock defect is caused by the fact that the copper-clad dielectric layer with low dielectric constant is adopted to satisfy the capacitive reactance caused by the lower dielectric layer, and the dielectric layer with low dielectric constant is often loose, and the loose dielectric layer has the side effect that the copper wire overflow is difficult to be pressed under high temperature or other external factors.
With the gradual shrinkage of the process node, the copper hillock defect becomes more serious to reach more than 250000 at the process node of 40nm, as shown in fig. 2 a. Copper hillock protruding defect has always had the copper infiltration phenomenon that the angle area is relatively weak, and the copper infiltration phenomenon is because the distance of copper line and copper line becomes shorter and shorter under the condition that the technology node reduces gradually to the risk that causes the electric current breakdown that shows can be bigger and bigger.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for improving the hillock-shaped protrusion defect in the copper interconnection process, which can solve the problem that a large amount of spherical protrusion defects appear after a silicon nitride film is deposited after copper CMP in the existing copper interconnection process.
In order to solve the above problems, the present invention provides a method for improving hillock defect in copper interconnect process, comprising the following steps:
step S1, forming a semiconductor device with a copper substrate pattern on the surface;
step S2, depositing a silicon carbide film on the surface of the semiconductor device, taking the silicon carbide film as a copper overflow barrier layer, and depositing the silicon carbide film at the temperature of 300-350 ℃;
step S3, after the silicon carbide film is deposited, carrying out thermal annealing treatment by using a low-temperature furnace tube process at 300-350 ℃, wherein the treatment time is 20-30 minutes;
and step S4, depositing a required silicon nitride film serving as an etching barrier layer on the surface of the silicon carbide film, wherein the silicon nitride film is deposited at the temperature of 400 ℃.
In step S2, the copper overflow barrier layer has a thickness of 50 to 200 angstroms.
Wherein, in step S2, the silicon carbide film is deposited under the condition of 350 ℃.
In step S3, the temperature of the thermal annealing treatment is 350 ℃.
Wherein the process conditions for forming the copper overflow barrier include: the pressure is 1 Torr-5 Torr, the flow rate of nitrogen is 100 sccm-10000 sccm, the flow rate of tetramethylsilane is 100 sccm-1000 sccm, the working power of the high-frequency radio frequency source is 100W-1000W, and the duration is 1 s-20 s.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, a layer of silicon carbide film is deposited at a low temperature before the deposition of the high-temperature silicon nitride film which causes the hillock-shaped bulge defect is carried out after copper CMP, the silicon carbide film is used as a copper overflow barrier layer to reduce the diffusion of copper, and the surface of the silicon carbide film is subjected to low-temperature annealing treatment, so that the silicon carbide film can be better adhered to the surface of the copper, the stability of the copper between interfaces is effectively improved, the number of hillock-shaped bulge defects caused by rapid extrusion due to the fact that the high-temperature silicon nitride deposition process is directly carried out on the surface of the copper can be obviously improved, and the effect is obvious.
Drawings
FIG. 1 is a schematic diagram of a conventional copper interconnect process;
FIG. 2a is a graph showing a hillock defect in a conventional copper interconnect process;
FIG. 2b is a schematic diagram of a hillock defect in a conventional copper interconnect process;
FIG. 3 is a flow chart of a method of an embodiment of the present invention;
FIG. 4 is a schematic diagram of a copper interconnect process in an embodiment of the invention;
FIG. 5 is a diagram illustrating hillock defects in a copper interconnect process according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described below with reference to the accompanying drawings, which are intended to illustrate general characteristics of methods, structures and/or materials used in certain exemplary embodiments of the present invention, and to supplement the description in the specification. The drawings of the present invention, however, are not to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the present invention.
Other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. In the following description, specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced or applied in different embodiments, and the details may be based on different viewpoints and applications, and may be widely spread and replaced by those skilled in the art without departing from the spirit of the present invention.
It should be noted that the features of the above embodiments and examples may be combined with each other without conflict. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
The method for improving the hillock defect in the copper interconnection process in the embodiment, as shown in fig. 3, includes the following steps:
step S1, forming a semiconductor device 100 with a copper substrate pattern, wherein the surface of the semiconductor device 100 is a plane formed by copper and dielectric;
step S2, depositing a silicon carbide film 101 on the surface of the semiconductor device 100, using the silicon carbide film 101 as a copper overflow barrier layer, and depositing the silicon carbide film 101 at 300-350 ℃;
preferably, the silicon carbide film 101 is deposited at 350 ℃;
step S3, depositing the silicon carbide film 101, and then performing thermal annealing treatment by using a low-temperature furnace tube process at 300-350 ℃, wherein the treatment time is 20-30 minutes;
step S4, depositing a silicon nitride film 102 as an etching barrier layer on the surface of the silicon carbide film 101, depositing the silicon nitride film 102 at 400 ℃, and forming a cross-sectional view of the device structure as shown in fig. 4.
In step S2, the copper overflow barrier 101 has a thickness of 50 to 200 angstroms.
In step S2, the process conditions for forming the copper overflow barrier 101 include: the pressure is 1Torr to 5Torr, the flow rate of nitrogen is 100sccm (standard cubic centimeter) to 10000sccm, the flow rate of tetramethylsilane (4MS) is 100sccm to 1000sccm, the working power of the high-frequency radio frequency source is 100W to 1000W, and the duration is 1s to 20 s.
In step S3, the temperature of the low-temperature annealing treatment is 300-350 ℃. In this embodiment, the temperature of the annealing treatment is preferably 350 ℃.
In step S4, the formation temperature of the silicon nitride film 102 is 400 ℃.
According to the embodiment of the invention, a silicon carbide film is deposited at a low temperature before a high-temperature silicon nitride film causing hillock defects is deposited after copper CMP, the silicon carbide film is used as a copper overflow barrier layer to reduce copper diffusion, and low-temperature annealing treatment is carried out on the surface of the silicon carbide film, so that the treated silicon carbide film can be better adhered to the copper surface, and the annealed copper property is more stable, thereby playing a role in stabilizing the copper surface, and effectively improving the stability of copper between interfaces, so that the number of hillock defects caused by sharp extrusion due to the fact that the copper surface is directly subjected to a high-temperature silicon nitride deposition process can be remarkably improved, as shown in FIG. 5, the hillock defects on the copper surface can be reduced to 0 from more than 250000 in FIG. 2a after the silicon carbide layer is deposited, and the effect is remarkable.
The present invention has been described in detail with reference to the specific embodiments, which are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. Equivalent alterations and modifications in the setting of process conditions by those skilled in the art without departing from the principles of the invention should be considered to be within the technical scope of the invention as defined by the appended claims.
Claims (7)
1. A method for improving hillock defects in a copper interconnect process, comprising the steps of:
step S1, forming a semiconductor device with a copper substrate pattern on the surface;
step S2, depositing a silicon carbide film on the surface of the semiconductor device, taking the silicon carbide film as a copper overflow barrier layer, and depositing the silicon carbide film at the temperature of 300-350 ℃;
step S3, after the silicon carbide film is deposited, carrying out thermal annealing treatment by using a low-temperature furnace tube process at 300-350 ℃, wherein the treatment time is 20-30 minutes;
and step S4, depositing a silicon nitride film which is required to be used as an etching barrier layer on the surface of the silicon carbide film.
2. The method of claim 1, wherein in step S2, the thickness of the copper overflow barrier layer is 50-200 angstroms.
3. The method of claim 1, wherein the process conditions for forming the copper overflow barrier layer comprise: the pressure is 1Torr to 5Torr, the flow rate of nitrogen is 100sccm to 10000sccm, the flow rate of tetramethylsilane is 100sccm to 1000sccm, and the working power of the high-frequency radio source is 100W to 1000W.
4. The method of improving hillock defects in a copper interconnect process as recited in claim 1, wherein in step S2, said silicon carbide film is deposited at 350 ℃.
5. The method for improving hillock defects in copper interconnect processes as recited in claim 1, wherein the thermal annealing treatment temperature is 350 ℃ in step S3.
6. The method of improving hillock defects in copper interconnect processes as recited in claim 1, wherein said silicon nitride film is deposited at 400 ℃ in step S4.
7. The method for improving hillock defects in copper interconnect processes as recited in claim 3, wherein the duration of said copper overflow barrier deposition process is in the range of 1s to 20 s.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010877270.6A CN112038286A (en) | 2020-08-27 | 2020-08-27 | Method for improving hillock defect in copper interconnection process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010877270.6A CN112038286A (en) | 2020-08-27 | 2020-08-27 | Method for improving hillock defect in copper interconnection process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112038286A true CN112038286A (en) | 2020-12-04 |
Family
ID=73580168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010877270.6A Pending CN112038286A (en) | 2020-08-27 | 2020-08-27 | Method for improving hillock defect in copper interconnection process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112038286A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113580557A (en) * | 2021-07-28 | 2021-11-02 | 沛顿科技（深圳）有限公司 | 3D printing method for replacing NCF in TSV process |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW455954B (en) * | 2000-09-26 | 2001-09-21 | Taiwan Semiconductor Mfg | Manufacturing process using thermal annealing process to reduce the generation of hillock on the surface of Cu damascene structure |
| US6734101B1 (en) * | 2001-10-31 | 2004-05-11 | Taiwan Semiconductor Manufacturing Company | Solution to the problem of copper hillocks |
| US6818557B1 (en) * | 2002-12-12 | 2004-11-16 | Advanced Micro Devices, Inc. | Method of forming SiC capped copper interconnects with reduced hillock formation and improved electromigration resistance |
| US20040231795A1 (en) * | 2003-05-20 | 2004-11-25 | Applied Materials, Inc | Reduction of hillocks prior to dielectric barrier deposition in Cu damascene |
| US20040259378A1 (en) * | 2003-06-18 | 2004-12-23 | Stephen Chambers | Methods and devices for the suppression of copper hillock formation |
| US20060019486A1 (en) * | 2003-09-24 | 2006-01-26 | Novellus Systems, Inc. | Novel film for copper diffusion barrier |
| CN101447472A (en) * | 2007-11-27 | 2009-06-03 | 中芯国际集成电路制造(上海)有限公司 | Etch stop layer, double-mosaic structure and forming method thereof |
| CN101740479A (en) * | 2008-11-14 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor device |
| CN101752298A (en) * | 2008-12-09 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for metal interconnecting structure |
| CN102054760A (en) * | 2009-11-10 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming copper interconnection structure |
| CN103187266A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Etching stop layer and forming method of copper-connection |
| CN110504211A (en) * | 2019-08-29 | 2019-11-26 | 上海华力集成电路制造有限公司 | Improve the process of the mound shape bump defects of top copper interconnection layer |
-
2020
- 2020-08-27 CN CN202010877270.6A patent/CN112038286A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW455954B (en) * | 2000-09-26 | 2001-09-21 | Taiwan Semiconductor Mfg | Manufacturing process using thermal annealing process to reduce the generation of hillock on the surface of Cu damascene structure |
| US6734101B1 (en) * | 2001-10-31 | 2004-05-11 | Taiwan Semiconductor Manufacturing Company | Solution to the problem of copper hillocks |
| US6818557B1 (en) * | 2002-12-12 | 2004-11-16 | Advanced Micro Devices, Inc. | Method of forming SiC capped copper interconnects with reduced hillock formation and improved electromigration resistance |
| US20040231795A1 (en) * | 2003-05-20 | 2004-11-25 | Applied Materials, Inc | Reduction of hillocks prior to dielectric barrier deposition in Cu damascene |
| US20040259378A1 (en) * | 2003-06-18 | 2004-12-23 | Stephen Chambers | Methods and devices for the suppression of copper hillock formation |
| US20060019486A1 (en) * | 2003-09-24 | 2006-01-26 | Novellus Systems, Inc. | Novel film for copper diffusion barrier |
| CN101447472A (en) * | 2007-11-27 | 2009-06-03 | 中芯国际集成电路制造(上海)有限公司 | Etch stop layer, double-mosaic structure and forming method thereof |
| CN101740479A (en) * | 2008-11-14 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor device |
| CN101752298A (en) * | 2008-12-09 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for metal interconnecting structure |
| CN102054760A (en) * | 2009-11-10 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming copper interconnection structure |
| CN103187266A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Etching stop layer and forming method of copper-connection |
| CN110504211A (en) * | 2019-08-29 | 2019-11-26 | 上海华力集成电路制造有限公司 | Improve the process of the mound shape bump defects of top copper interconnection layer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113580557A (en) * | 2021-07-28 | 2021-11-02 | 沛顿科技（深圳）有限公司 | 3D printing method for replacing NCF in TSV process |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100550316C (en) | The formation method and the semiconductor structure of semiconductor structure | |
| TW578216B (en) | Method of manufacturing low K layer | |
| CN112038286A (en) | Method for improving hillock defect in copper interconnection process | |
| US7413976B2 (en) | Uniform passivation method for conductive features | |
| KR100914982B1 (en) | Metal wiring of semiconductor device and method of manufacturing the same | |
| US6734101B1 (en) | Solution to the problem of copper hillocks | |
| US6723628B2 (en) | Method for forming bonding pad structures in semiconductor devices | |
| CN110957264A (en) | Preparation method of copper diffusion barrier layer | |
| CN106158729A (en) | The forming method of semiconductor structure | |
| US20040038526A1 (en) | Thermal process for reducing copper via distortion and crack | |
| CN115050694A (en) | Process method for improving hilly bulge defect | |
| KR950005259B1 (en) | Fabricating method of semiconductor device | |
| KR100523658B1 (en) | Method for manufacturing copper diffusion barrier | |
| KR100628216B1 (en) | method for forming metal line of semiconductor device | |
| KR100459945B1 (en) | Method of manufacturing a semiconductor device | |
| CN112259501B (en) | Optimization method for contact hole chemical mechanical planarization | |
| KR100617046B1 (en) | method for forming metal line of semiconductor device | |
| KR100645194B1 (en) | Method for Manufacturing MIM Capacitor | |
| KR100575884B1 (en) | Method for forming metal wiring of semiconductor device | |
| TWI249812B (en) | A method of diffusion barrier layer formation for protecting a dielectric layer | |
| KR101044007B1 (en) | Metal wiring of semiconductor device and method for forming the same | |
| TWI242260B (en) | Method of inhibiting crystal grain size on metal surfaces in a high temperature environment of semiconductor process, method of manufacturing metal interconnect, and method of manufacturing metal-insulator-metal capacitor on metal interconnect structure | |
| KR100417687B1 (en) | Pre-metal dielectric layer forming method of semiconductor device | |
| CN117202773A (en) | Capacitor structure and preparation method thereof | |
| CN108807262A (en) | Improve the method for interface between low dielectric material layer and silicon oxynitride layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201204 |