月丨>日修(更)正本 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種在低介電材料層與内連線間形成 保濩阻障層的方法。特別是有關於一種能避免影響介電層 之介電常數的保護阻障層形成方法。 【先前技術】 在積體電路（1C)製程中，需靠金屬線來將電子晶片中如 電曰曰體或電容等半導體元件連接起來。為將晶片内數百萬 顆（未來甚至可能增加到數十億顆）半導體元件相互連接， 必須使用多層的連接線路，而這些複雜的導線線路就是半 導體元件的内連線（interconnect)。 自有半V體元件以來，銘便因電阻值小，且其電路圖 案的沉積和蝕刻十分容易而成為主要的導線材料。但鋁的 缺點在於當導線變得很細，例如0·丨3微米時，便無法可靠 的承載電流，使得鋁在未來的元件應用方面受到限制。 並由於積體電路的製作技術已邁入超大型積體電路 (ultralarge-scale integration)，當元件的尺寸逐漸縮小的同 時，為了克服導線阻值與導線_介電層_導線結構之電容值所 造成的訊號傳輸延遲問題（RCdelay)，必須採用高導電率的 金屬導線與低介電常數的介電材料。就金屬而言，銅的電 阻值比鋁更小，可在較小的面積上承載較大的電流。亦由 於鋼的抗電致遷移（electro_migrati〇n)能力比鋁好，因此 可減輕其電移作用，提高元件的可靠度。因此，當晶片中 的元件尺寸越來越小時，銅開始取代鋁而成為内連線材料 5 9 1249812 的主流，以生產速度更快、電路更密集的晶片。 由於活性離子蝕刻的技術無法應用在銅上，因此銅導 =是以鑲嵌法來製作。目前製程係在隔離兩層内連線之低 介電常數的介電層中钱刻出欲形成銅導線的镶嵌圖案。隨 後在鑲嵌圖案中沉積銅原子以同時完成銅導線及連接上下 兩層匕内連線的插塞。然而，銅原子具有極高的擴散能力， 可能進入介電層中影響其絕緣性，進而影響元件的可靠 性。因此目前技術中，會先在介電層中的镶後圖案内沉積 一層擴散阻障層，如鈦（Ti)、氮化鈦（TiN)、鈕或氮化鈕等 金屬或金屬氮化物來防止銅擴散至介電層中。目前主要以 物理氣相沉積法（PVD)來沉積擴散阻障層。且在沉積過程 中，會對基材（晶圓）施加一 RF偏壓，如3〇〇 V，以期達到 更好的階梯覆蓋效果與沉積速度。 然而電漿中被離子化的沉積材料受到偏壓影響，以極 同速度揎擊並沉積在介電層上時，低介電常數的介電層會 因此受到損害而導致介電常數改變，例如介電常數提高。 介電層之低介電常數的改變，特別是提高，將會影響到導 線的RC時間延遲，並使元件性能不穩定。 因此，需要一種形成阻障層的方法，以避免介電層在 沉積阻障層的過程中受損而改變介電常數的問題。 【發明内容】 因此本發明的方向在於提供一種形成保護阻障層的方 法，以避免介電層在沉積擴散阻障層的過程中，因受損而 改變介電常數進而影響元件性能的問題。 1249812 根據本發明之上述目的，提出一種為介電層形成保護 阻障層的方法。依照本發明一較佳實施例，在具有至少一 個位於介電層内之開口的基材上形成一層同樣具有防止金 屬原子擴散的保護阻障層。此保護阻障層覆蓋在介電層上 與開口内。再形成一擴散阻障層於該保護阻障層上以防止 如銅等導線材料之金屬原子擴散至介電層中。 其中，保護阻障層之形成方法可為原子層沉積法 (ALD)、化學氣相沉積法（cVD)、或物理氣相沉積法vd)。 八中上述各,儿積方法需為沉積粒子到達基材表面時的動能 (速度）在撞擊介電層後不足以改變介電層之介電常數的方 法。例如以物理氣相沉積法來沉積保護阻障層時，施予基 材上之RF偏壓大小需介在不影響介電層之介電常數的^ 圍内’並可視所使用保護阻障層材料之不同來加以變化偏 壓範圍。 若使用物理氣相沉積法來形成保護阻障層時，保護阻 障層之厚度約介於Η) A至5〇 A之間。使用原子層沉積法 :形成保護阻障層時’其厚度約介於1〇 A至2〇 A之間。 ¥使用化學氣相沉積法來形成保護阻障層時，保護阻障層 之厚度則約介於20人至50 A之間。 保護阻障層的材質可為鈦、氮化鈦、组、氮化组或氮 化鎢。而擴散阻障層的材質可為鈦、氮化鈦、㉘、氣化組 ::化鎢。且基材上的開口為用來製作插塞的接觸窗或是 1作内連線的鑲嵌結構。 :發明之優點在於保護阻障層的形成，可避免在傳統 私利用對基板施予RF偏壓（如300 v)來增進擴散阻障層 較年.r月卜 1249812 之階梯覆蓋率的物理氣相沉積過程中，介電層因受高速離 子衝撞而損傷，進而改變介電常數的問題，如介電常數升 高。使得導線之間的介電層能在製作内連線，如銅^線的 過程中保持穩定的低介電常數。 【實施方式】丨 丨 日 日 日 日 九 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In particular, there is a method of forming a protective barrier layer that avoids affecting the dielectric constant of the dielectric layer. [Prior Art] In the integrated circuit (1C) process, metal wires are required to connect semiconductor components such as an electric body or a capacitor in an electronic chip. To interconnect millions of semiconductor components (and possibly even billions) in a wafer, multiple layers of interconnects must be used, and these complex conductor traces are the interconnects of the semiconductor components. Since its own half-V body component, Ming has become the main wire material due to its small resistance value and easy deposition and etching of its circuit pattern. However, aluminum has the disadvantage that when the wire becomes very thin, for example, 0 丨 3 μm, the current cannot be reliably carried, so that aluminum is limited in future component applications. And because the fabrication technology of the integrated circuit has entered the ultralarge-scale integration, when the size of the component is gradually reduced, in order to overcome the resistance value of the wire and the capacitance value of the wire-dielectric layer-wire structure The resulting signal transmission delay problem (RCdelay) must use high conductivity metal wires and low dielectric constant dielectric materials. In the case of metals, copper has a lower resistance value than aluminum and can carry a large current over a small area. It also has better electromigration resistance (electro_migrati〇n) than aluminum, so it can reduce its electromigration and improve component reliability. As a result, as component sizes in wafers become smaller and smaller, copper begins to replace aluminum as the mainstream of interconnect material 5 9 1249812 to produce faster, more densely populated wafers. Since the technique of reactive ion etching cannot be applied to copper, the copper lead = is fabricated by damascene. The current process is in which a mosaic of copper conductors is formed in a dielectric layer that isolates the low dielectric constants of the two interconnects. Copper atoms are then deposited in the damascene pattern to simultaneously complete the copper wires and the plugs connecting the upper and lower inner wires. However, copper atoms have a very high diffusion capacity and may enter the dielectric layer to affect their insulation, which in turn affects the reliability of the component. Therefore, in the current technology, a diffusion barrier layer such as titanium (Ti), titanium nitride (TiN), button or nitride button or the like is deposited in the inlay pattern in the dielectric layer to prevent it. Copper diffuses into the dielectric layer. Currently, a diffusion barrier layer is mainly deposited by physical vapor deposition (PVD). And during the deposition process, an RF bias, such as 3 〇〇 V, is applied to the substrate (wafer) to achieve better step coverage and deposition speed. However, the ionized deposition material in the plasma is affected by the bias voltage, and when it is slammed at the same speed and deposited on the dielectric layer, the dielectric layer of low dielectric constant is thus damaged to cause a change in dielectric constant, for example, The dielectric constant is increased. The change in the low dielectric constant of the dielectric layer, in particular the increase, will affect the RC time delay of the conductor and destabilize the component performance. Therefore, there is a need for a method of forming a barrier layer to avoid the problem of changing the dielectric constant when the dielectric layer is damaged during deposition of the barrier layer. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method of forming a protective barrier layer to prevent the dielectric layer from changing the dielectric constant and thereby affecting the performance of the device due to damage during deposition of the diffusion barrier layer. 1249812 In accordance with the above objects of the present invention, a method of forming a protective barrier layer for a dielectric layer is provided. In accordance with a preferred embodiment of the invention, a protective barrier layer is also formed over the substrate having at least one opening in the dielectric layer that also prevents diffusion of metal atoms. The protective barrier layer overlies the dielectric layer and the opening. A diffusion barrier layer is further formed on the protective barrier layer to prevent metal atoms such as copper from diffusing into the dielectric layer. The method for forming the protective barrier layer may be atomic layer deposition (ALD), chemical vapor deposition (cVD), or physical vapor deposition (vd). In the above eight methods, the kinetic energy (speed) when the deposited particles reach the surface of the substrate is insufficient to change the dielectric constant of the dielectric layer after striking the dielectric layer. For example, when the protective barrier layer is deposited by physical vapor deposition, the RF bias voltage applied to the substrate needs to be within a range that does not affect the dielectric constant of the dielectric layer and can be different depending on the material of the protective barrier layer used. To change the bias range. When physical vapor deposition is used to form the protective barrier layer, the thickness of the protective barrier layer is between about A) A and 5 〇 A. Use of atomic layer deposition: when forming a protective barrier layer, its thickness is between about 1 〇A and 2 〇A. When using chemical vapor deposition to form a protective barrier layer, the thickness of the protective barrier layer is between about 20 and 50 Å. The material of the protective barrier layer may be titanium, titanium nitride, group, nitrided group or tungsten nitride. The material of the diffusion barrier layer may be titanium, titanium nitride, 28, gasification group: tungsten. And the opening on the substrate is a contact window for making a plug or a mosaic structure for interconnecting. The invention has the advantages of protecting the formation of the barrier layer, and avoiding the application of an RF bias (for example, 300 v) to the substrate in the conventional private use to enhance the step coverage of the diffusion barrier layer. During the phase deposition process, the dielectric layer is damaged by high-speed ion collision, which in turn changes the dielectric constant, such as an increase in dielectric constant. The dielectric layer between the wires is capable of maintaining a stable low dielectric constant during the fabrication of interconnects, such as copper wires. [Embodiment]
本發明揭露一種為介電層形成保護阻障層的方法。係 在介電層上方具有接觸窗或鑲嵌結構之介電層的基材上， 先以原子層沉積法、化學氣相沉積法或物理氣相沉積法來 形成保護阻障層。其中上述各沉積方法需為沉積粒子到達 基材表面時的動能（速度）在撞擊介電層後不足以改變介電 層=介電常數的方法。例如以物理氣相沉積法來沉積保護 阻障層時，施予基材上之RF偏壓大小需介在不影響介電層 之介電常數的範圍内，如RF偏壓範圍約可介於0¥至100 v之間，或更可介於〇v至3〇v。隨後再以傳統常用2RF 偏壓範圍，如300 V之RF偏壓來執行物理氣相沉積以形成 擴散阻障層。 其中保護阻障層之材料可為任何具有防止内連線金屬 原子擴政的材料，如鈦、氮化鈦、鈕、氮化钽或氮化鎢等。 並且若以物理氣相沉積法來形成保護阻障層時，對基材施 用的RF偏壓範圍需視所使用低介電常數之介電層的材質 來決定’以沉積材料粒子不會因撞擊介電層而改變介電層 之介電常數為準，例如從0 V至1〇〇 V。 並且’若使用物理氣相沉積法來形成保護阻障層時， 保濩阻障層之厚度約介於10 A至50 A之間。使用原子層 1249812A method of forming a protective barrier layer for a dielectric layer is disclosed. A protective barrier layer is formed by atomic layer deposition, chemical vapor deposition, or physical vapor deposition on a substrate having a dielectric layer having a contact window or a damascene structure above the dielectric layer. Each of the above deposition methods requires a method in which the kinetic energy (velocity) when the deposited particles reach the surface of the substrate is insufficient to change the dielectric layer = dielectric constant after striking the dielectric layer. For example, when the protective barrier layer is deposited by physical vapor deposition, the RF bias voltage applied to the substrate needs to be within a range that does not affect the dielectric constant of the dielectric layer, such as an RF bias range of about 0¥ to Between 100 v, or more preferably 〇v to 3〇v. Physical vapor deposition is then performed to form a diffusion barrier layer using a conventional conventional 2RF bias range, such as an RF bias of 300V. The material for protecting the barrier layer may be any material having a function of preventing the diffusion of the interconnect metal atoms, such as titanium, titanium nitride, a button, tantalum nitride or tungsten nitride. And if the protective barrier layer is formed by physical vapor deposition, the RF bias range applied to the substrate is determined by the material of the dielectric layer using the low dielectric constant. The dielectric layer changes the dielectric constant of the dielectric layer, for example from 0 V to 1 〇〇V. And if the physical barrier layer is used to form the protective barrier layer, the thickness of the barrier layer is between about 10 A and 50 A. Using atomic layer 1249812
沉積法來形成保護阻障層時，其厚度約介於l〇 A至2〇 A 之間。若使用化學氣相沉積法來形成保護阻障層時，保護 阻障層之厚度則約介於20 A至50 A之間。 以下舉出數個應用本發明之較佳實施例來說明本發明 目的、方法與優點。請參照第i圖，其繪示—個半導體基 材100上具有半導體元件102、介電層104、插塞106、介 電層108以及絲製作内連線(如銅導線）的鑲嵌結構11〇。 其中介電f 108的材質可為任何低介電常數的介電材料， 如二氧化矽。 明參考第2圖，對基材1〇〇施予約3〇 v的偏壓（亦 可不施加RF偏壓）來進行物理氣相沉積以形成保護阻障層 Π2。在此較佳實施例中，保護阻障層可以是钽、氮化钽、 鈦或氮化鈦，且沉積厚度約介於10 A至50 A之間。 隨後對基材100施予300 V之RF偏壓來進行物理氣 相沉積以形成階梯覆蓋效果良好的擴散阻障層114。在沉積 擴散阻障層114的過程中，雖然對基材1〇〇施予3〇〇 v的 RF偏壓來加速沉積粒子的速度以求得較好的階梯覆蓋效 果以及沉積速度。但由於保護阻障層112保護了介電層 108’故介電層1〇8不會因高速沉積粒子的撞擊而受到損 害，也因此避免介電常數改變的問題。 根據本發明來完成擴散阻障層114後，即可依昭傳统 技術來沉積金屬層形成金屬内連線116，如銅導線。並於執 行化學機械研磨（CMP)以移除鑲嵌結構以外的銅層、擴散阻 障層與保護阻障層即可得到如第3圖所示之結構。 同樣地，本發明方法亦可應用在多重内連線的結構 1249812 % ⑽乂秀与穩4 上-月參考第4圖，當完成第一層金屬内連線ιΐ6後，同 樣可依序在其上方沉積介電| 118、硬罩幕12〇與介電層 ⑵。其中介電層118與122同樣為了達到降低rc時間延 遲的目的而使用低介電常數的介電材料，而硬罩幕12〇則 可以是如氮切等材質’以作為_反應的終止層。 利用硬罩幕120來作為姓刻終止層而在介電層ιΐ8與 122中形成用來連接上下兩層金屬内連線的接觸窗124 : 及用來作為導線的鑲嵌結構126(即溝渠126)。之後根據本 發明’利用原子層沉積法形成厚度範圍約$ l〇 A至2〇 a 的保”蒦阻&層，且保護阻障& 128的材料可為氮化组。此 步驟亦可利用化學氣相沉積法來形成厚度範圍約為20 A至 50 A、材質為氮化鈦的保護阻障層128。 完成保護阻障層來保護介電層122後，即可使用習知 技術常用之方法來形成擴散阻障層114,例如對基材1〇〇 施予300 V之RF偏壓來執行物理氣相沉積。隨後便可依照 傳統製程來形成第二層内金屬連線m以及連接上下兩層 内金屬連線的插塞。例如以物理氣相沉積法來沉積銅原子 以填滿接觸窗124與鑲嵌結構126,並執行化學機械研磨來 移除介電層122表面上的銅層、擴散阻障層13〇與保護阻 障層128即可得到如第4圖所示之結構。 由上述本發明較佳實施例可知，應用本發明來形成擴 散阻障層可具有保護介電層維持低介電常數值之優點。以 避免介電層在高RF偏壓下執行物理氣相沉積的過程中受 到知害因而改變介電常數進而影響元件性能的問題。 雖然本發明已以數個較佳實施例揭露如上，然其並非 1249812When the deposition method is used to form the protective barrier layer, the thickness is between about 1 〇 A and 2 〇 A. When chemical vapor deposition is used to form the protective barrier layer, the thickness of the protective barrier layer is between about 20 A and 50 A. The objects, methods, and advantages of the present invention are set forth in the preferred embodiments of the invention. Referring to FIG. 1 , a semiconductor substrate 100 having a semiconductor device 102 , a dielectric layer 104 , a plug 106 , a dielectric layer 108 , and a wire fabrication interconnect (such as a copper wire) are shown. . The material of the dielectric f 108 may be any low dielectric constant dielectric material such as cerium oxide. Referring to Fig. 2, a substrate bias of about 3 〇 v is applied (or RF bias is not applied) for physical vapor deposition to form a protective barrier layer Π2. In this preferred embodiment, the protective barrier layer can be tantalum, tantalum nitride, titanium or titanium nitride and deposited to a thickness of between about 10 A and 50 A. Substrate 100 is then subjected to an RF bias of 300 V for physical vapor deposition to form a diffusion barrier layer 114 having a good step coverage. In the process of depositing the diffusion barrier layer 114, an RF bias of 3 〇〇 v is applied to the substrate 1 to accelerate the deposition of particles to obtain a better step coverage effect and deposition speed. However, since the protective barrier layer 112 protects the dielectric layer 108', the dielectric layer 1〇8 is not damaged by the impact of the high-speed deposition particles, and thus the problem of the dielectric constant change is avoided. After the diffusion barrier layer 114 is completed in accordance with the present invention, the metal layer can be deposited to form a metal interconnect 116, such as a copper wire, in accordance with conventional techniques. The structure shown in Fig. 3 can be obtained by performing chemical mechanical polishing (CMP) to remove the copper layer, the diffusion barrier layer and the protective barrier layer other than the damascene structure. Similarly, the method of the present invention can also be applied to the structure of multiple interconnects 1249812% (10) 乂 与 and stable 4 上-月 reference 4, when the first layer of metal interconnect ιΐ6 is completed, it can also be sequentially The upper dielectric is deposited | 118, the hard mask 12 〇 and the dielectric layer (2). The dielectric layers 118 and 122 also use a low dielectric constant dielectric material for the purpose of reducing the rc time delay, and the hard mask 12 可以 may be a material such as nitrogen cut as a termination layer for the reaction. A contact mask 124 for connecting the upper and lower metal interconnects is formed in the dielectric layers ι 8 and 122 by using the hard mask 120 as a surname termination layer: and a damascene structure 126 (ie, trench 126) for use as a wire. . Then, according to the present invention, a layer of a resistive layer having a thickness ranging from about 10,000 Å to about 2 Å is formed by atomic layer deposition, and the material of the protective barrier & 128 can be a nitrided group. A chemical barrier layer is used to form a protective barrier layer 128 having a thickness of about 20 A to 50 A and a material of titanium nitride. After the protective barrier layer is formed to protect the dielectric layer 122, conventional techniques can be used. The method is to form a diffusion barrier layer 114, for example, applying an RF bias of 300 V to the substrate 1 to perform physical vapor deposition. Then, the metal wiring in the second layer and the connection can be formed according to a conventional process. a plug of metal wires in the upper and lower layers. For example, copper atoms are deposited by physical vapor deposition to fill the contact window 124 and the damascene structure 126, and chemical mechanical polishing is performed to remove the copper layer on the surface of the dielectric layer 122. The diffusion barrier layer 13 and the protective barrier layer 128 can be obtained as shown in Fig. 4. According to the preferred embodiment of the invention described above, the diffusion barrier layer can be formed by using the invention to have a protective dielectric layer. The advantage of maintaining a low dielectric constant value Layer performs the physical vapor deposition process in Injury by the known problem thus changing the dielectric constant thereby affecting performance of the device. While the present invention has been described in several preferred embodiments, they are not at a high RF bias 1,249,812
用以限定本發明，任何孰習舲 彳此技藝者，在不脫離本發明之 精神和範圍内，當可作各種 f 令禋夂更勳與濶飾，因此本發明之 保護範圍當視後附之中請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之詳細說明如下： 第1圖是-個半導體基材剖面圖，顯示在基材上方具 有半導體元件以及介電層，並在介電層上方具有插塞以及 用來形成内連線的鑲嵌結構。 第2圖為-半導體基材剖面圖，顯示根據本發明在介 電層上與鑲嵌結構内沉積一保護阻障層與一擴散阻障層。 第3圖為一半導體基材剖面圖，顯示根據本發明來形 成金屬内連線與介電層之間的擴散阻障層。 第4圖為依照本發明另一較佳實施例的半導體基材剖 面圖，顯示根據本發明來完成多重内連線與介電層之間的 擴散阻障層。 102 :半導體元件 106 :插塞 m:鑲嵌結構 114 :擴散阻障層 118 :介電層 【主要元件符號說明】 100 :基材 104 :介電層 108 :介電層 112 :保護阻障層 116 :金屬内連線 11 1249812 120 :硬罩幕 124 :接觸窗 128 :保護阻障層 132 :金屬内連線 122 :介電層 126 :鑲嵌結構 130 :擴散阻障層In order to limit the present invention, it is possible to make various modifications and accessories when the present invention can be made without departing from the spirit and scope of the present invention. The scope defined by the patent scope shall prevail. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious, the detailed description of the drawings is as follows: FIG. 1 is a cross-sectional view of a semiconductor substrate, showing There is a semiconductor element and a dielectric layer over the substrate, and a plug over the dielectric layer and a damascene structure for forming the interconnect. Figure 2 is a cross-sectional view of a semiconductor substrate showing deposition of a protective barrier layer and a diffusion barrier layer over the dielectric layer and the damascene structure in accordance with the present invention. Figure 3 is a cross-sectional view of a semiconductor substrate showing the formation of a diffusion barrier layer between a metal interconnect and a dielectric layer in accordance with the present invention. 4 is a cross-sectional view of a semiconductor substrate in accordance with another preferred embodiment of the present invention showing the diffusion barrier between a plurality of interconnect lines and a dielectric layer in accordance with the present invention. 102: semiconductor element 106: plug m: damascene structure 114: diffusion barrier layer 118: dielectric layer [main element symbol description] 100: substrate 104: dielectric layer 108: dielectric layer 112: protective barrier layer 116 : Metal interconnect 11 1249812 120 : Hard mask 124 : Contact window 128 : Protective barrier layer 132 : Metal interconnect 122 : Dielectric layer 126 : Mosaic structure 130 : Diffusion barrier layer
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