CN112928062B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate; forming a porous dielectric layer on a substrate; forming a conductive through hole in the porous dielectric layer; covering the bottom and the side wall of the conductive through hole with a nucleation layer in a conformal manner by adopting a physical vapor deposition process; an atomic layer deposition process is adopted, a first barrier layer is conformally covered on the nucleation layer, and a diffusion barrier layer is formed between the first barrier layer and the nucleation layer; and forming a conductive plug in the conductive through hole with the diffusion barrier layer. The embodiment of the invention is beneficial to reducing the forming difficulty of the diffusion barrier layer and improving the film quality of the diffusion barrier layer, thereby being beneficial to improving the diffusion barrier preventing capability of the diffusion barrier layer and further improving the electromigration problem, improving the reliability of the semiconductor structure, and enabling the thickness of the diffusion barrier layer to be smaller, thereby increasing the forming space of the conductive plug, further increasing the process window for forming the conductive plug, reducing the RC delay of the rear section and optimizing the performance of the semiconductor structure.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
As integrated circuit fabrication moves toward ultra large scale integrated circuits (ULSI), the density of circuitry within them increases, and the number of devices contained therein increases, such that the surface of the wafer does not provide sufficient area to fabricate the desired interconnect lines. In order to match with the increased requirement of the interconnection lines after the elements shrink, the design of more than two layers of multi-layer metal interconnection structures realized by using wiring grooves and through holes becomes a method which is necessary for the technology of the very large scale integrated circuit.
In the back-end fabrication of semiconductor devices, a metal interconnect structure formation process is typically required. The metal interconnect structure formation process is typically performed on a semiconductor substrate that typically has an active region on which semiconductor devices such as transistors and capacitors are formed. In the metal interconnection structure, there may be a plurality of metal plugs and metal interconnection lines, and the plurality of metal interconnection lines may be electrically connected through the metal plugs. When forming a subsequent metal plug or metal interconnect on a previous metal plug or metal interconnect, an interlayer dielectric layer is usually formed on the previous metal plug or metal interconnect, then a Via (Via) and a Trench (Trench) are formed in the interlayer dielectric layer, and finally the Via and the Trench are filled with metal to form the subsequent metal plug or metal interconnect.
After forming the through holes or trenches, before filling the through holes and trenches with metal, a diffusion barrier layer is usually formed on the surface of the through holes or trenches to prevent inter-diffusion between metals or diffusion of metals into an interlayer dielectric layer.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a porous dielectric layer on the substrate; forming a conductive through hole in the dielectric layer; forming a nuclear layer on the bottom and the side wall of the conductive through hole in a conformal mode by adopting a physical vapor deposition process; an atomic layer deposition process is adopted, and a first barrier layer is conformally covered on the nucleation layer and used for forming a diffusion barrier layer with the nucleation layer; and forming a conductive plug in the conductive through hole formed with the diffusion barrier layer.
Optionally, after forming the first barrier layer, before forming the conductive plug, the method for forming the semiconductor structure further includes: and a physical vapor deposition process is adopted to cover a second barrier layer on the first barrier layer in a conformal manner, and the second barrier layer is used for forming the diffusion barrier layer together with the first barrier layer and the nucleation layer.
Optionally, after forming the first barrier layer, before forming the conductive plug, the method for forming the semiconductor structure further includes: and sputtering the first barrier layer, wherein the sputtering treatment is suitable for improving the density of the first barrier layer.
Optionally, in the step of forming the nucleation layer, the thickness of the nucleation layer isTo the point of
Optionally, in the step of forming the nucleation layer by using a physical vapor deposition process, parameters of the physical vapor deposition process include: the bias power is 100W to 500W, and the direct current power is 8000W to 20000W.
Optionally, in the step of forming the first barrier layer, the thickness of the first barrier layer isTo the point of
Optionally, in the step of forming the second barrier layer, the second barrier layer has a thickness ofTo the point of
Optionally, in the step of forming the second barrier layer by using a physical vapor deposition process, parameters of the physical vapor deposition process include: the direct current power is 8000W to 20000W, the radio frequency coil power is 1000W to 2000W, and the bias power is 200W to 500W.
Optionally, in the step of performing sputtering treatment on the first barrier layer, parameters of the sputtering treatment include: the DC power is 100W to 2000W, the RF coil power is 1000W to 2000W, the bias power is 200W to 400W, and the DC coil power is 0W to 1000W.
Optionally, the material of the nucleation layer includes one or more of TaN, ta, ti and TiN.
Optionally, the material of the first barrier layer includes one or both of TaN and TiN.
Optionally, the material of the second barrier layer includes one or more of TaN, ta, ti and TiN.
Optionally, in the step of forming the first barrier layer by using an atomic layer deposition process, a precursor used by the atomic layer deposition process includes PDMAT and NH 3.
Optionally, the material of the porous dielectric layer is a low dielectric constant dielectric material or an ultra-low dielectric constant material.
Optionally, the material of the porous dielectric layer includes SiOCH, black diamond, silsesquioxane-based material, or fluorine doped silicon oxide.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a porous dielectric layer on the substrate, wherein a conductive through hole is formed in the porous dielectric layer; the nucleation layer is conformally covered on the bottom and the side wall of the conductive through hole, and the nucleation layer is formed through a physical vapor deposition process; a first barrier layer conformally overlying the nucleation layer, the first barrier layer formed by an atomic layer deposition process for forming a diffusion barrier layer with the nucleation layer; and the conductive plug is filled in the conductive through hole and is contacted with the diffusion barrier layer.
Optionally, the semiconductor structure further includes: and the second barrier layer is positioned between the first barrier layer and the conductive plug, is formed through a physical vapor deposition process and is used for forming the diffusion barrier layer together with the first barrier layer and the nucleation layer.
Optionally, the nucleation layer has a thickness ofTo the point of
Optionally, the first barrier layer has a thickness ofTo the point of
Optionally, the second barrier layer has a thickness ofTo the point of
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the method for forming the semiconductor structure, the nucleation layer is conformally covered on the bottom and the side wall of the conductive through hole by adopting a physical vapor deposition process before the first barrier layer is formed, so that the nucleation rate during the formation of the first barrier layer is improved, the film continuity and the formation quality of the first barrier layer are improved, and the nucleation layer is formed by adopting the physical vapor deposition process, so that the material of the nucleation layer can be filled into the holes on the bottom and the side wall of the conductive through hole to improve the surface roughness of the conductive through hole, a smooth and flat surface is provided for the formation of the first barrier layer, the thickness uniformity and the film formation quality of the first barrier layer are improved, the process difficulty for forming the first barrier layer is reduced, and the thickness of the formed first barrier layer is smaller; in addition, the step coverage performance of the atomic layer deposition process is good, and the conformal coverage capability of the first barrier layer on the bottom and the side wall of the conductive through hole is improved; in summary, the embodiment of the invention is beneficial to reducing the difficulty of forming the diffusion barrier layer and improving the film quality of the diffusion barrier layer, and the thickness of the diffusion barrier layer is smaller, which is beneficial to improving the diffusion barrier resistance of the diffusion barrier layer to improve the Electromigration (EM) problem, thereby improving the reliability of the semiconductor structure, reducing the difficulty of filling the conductive plug in the conductive through hole, increasing the process window for forming the conductive plug, correspondingly reducing the RC delay of the rear section, and optimizing the performance of the semiconductor structure.
Drawings
Fig. 1 to 4 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 5 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
Fig. 11 to 13 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known in the art, after forming the via hole or trench, before filling the via hole or trench with metal, a diffusion barrier layer is usually formed on the surface of the via hole or trench to prevent inter-diffusion between metals or diffusion of metals into an interlayer dielectric layer.
In semiconductor processing, the diffusion barrier layer is typically formed using a physical vapor deposition process. However, the step coverage capability of the physical vapor deposition process is poor, as the size of the device is further reduced, the size of the conductive via hole is also smaller and smaller, and the physical vapor deposition process is also more and more difficult and challenging to form a diffusion barrier layer in a conductive manner.
Another approach is currently proposed to facilitate the step coverage of the diffusion barrier, but the resulting device still has poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1 to 4, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate is provided; forming a porous dielectric layer 1 on the substrate; a conductive via 2 is formed in the porous dielectric layer 1.
Referring to fig. 2, a first barrier layer 3 is formed at the bottom and side walls of the conductive via 2 using an atomic layer deposition process.
Referring to fig. 3, a second barrier layer 4 is formed on the first barrier layer 3 using a physical vapor deposition process, and the second barrier layer 4 and the first barrier layer 3 are used to form a diffusion barrier layer 5.
Referring to fig. 4, a conductive plug 6 is formed in the conductive via 2 in which the diffusion barrier layer 5 is formed.
In the forming method, the diffusion barrier layer 5 is formed by adopting an atomic layer deposition process and a physical vapor deposition process in sequence, so that the advantage of strong step coverage capability of the atomic layer deposition process is combined with the advantage of high film density and strong barrier capability of the physical vapor deposition process, and the formed diffusion barrier layer 5 can be formed at the bottom and the side wall of the conductive through hole 2 and has diffusion barrier prevention capability.
However, the porous dielectric layer1 is in a porous structure, the surfaces of the side wall and the bottom of the conductive via 2 are rough, the first barrier layer3 formed by using the atomic layer deposition process is easy to form in the hole exposed at the side wall and the bottom of the conductive via 2, and the atomic layer deposition process has a strong step coverage capability, which easily results in poor film quality (for example, film continuity) of the first barrier layer3, and increases the difficulty of forming the first barrier layer3 by using the atomic layer deposition process.
Therefore, in order to ensure that the film continuity of the first barrier layer 3 is better and thus the film quality is better, so that the covering ability of the diffusion barrier layer 5 on the bottom and the side wall of the conductive via 2 is stronger, it is generally necessary to form the first barrier layer 3 with a larger thickness, which easily results in that the thickness of the diffusion barrier layer 5 is also larger. On the one hand, the larger thickness of the diffusion barrier layer 5 easily causes the size of the opening of the conductive through hole 2 to be reduced, so that the difficulty of filling the conductive plug 6 in the conductive through hole 2 is easily increased, and the process window for forming the conductive plug 6 is reduced; on the other hand, the thickness of the diffusion barrier layer 5 is larger, the space of the conductive through hole 2 occupied by the diffusion barrier layer 5 is more, the formation space of the conductive plug 6 is correspondingly smaller, and the volume of the conductive plug 6 is smaller, so that the interconnection resistance of the semiconductor structure is easily increased, the RC delay of the later stage is easily deteriorated, and the performance of the formed semiconductor structure is poor.
Moreover, as the feature size of the device is further reduced, the thickness and film quality of the diffusion barrier layer 5 formed by the forming method are also more and more difficult to meet the process requirements.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a porous dielectric layer on the substrate; forming a conductive through hole in the porous medium layer; forming a nuclear layer on the bottom and the side wall of the conductive through hole in a conformal mode by adopting a physical vapor deposition process; an atomic layer deposition process is adopted, and a first barrier layer is conformally covered on the nucleation layer and used for forming a diffusion barrier layer with the nucleation layer; and forming a conductive plug in the conductive through hole formed with the diffusion barrier layer.
In the method for forming the semiconductor structure, a physical vapor deposition process is adopted to cover the nucleation layer on the bottom and the side wall of the conductive through hole in a conformal manner before the first barrier layer is formed, so that the nucleation rate during forming the first barrier layer is improved, the film continuity and the formation quality of the first barrier layer are improved, and the material of the nucleation layer can be filled into holes on the bottom and the side wall of the conductive through hole to improve the surface roughness of the conductive through hole, so that a smooth and flat surface is provided for forming the first barrier layer, the thickness uniformity and the film formation quality of the first barrier layer are improved, the process difficulty for forming the first barrier layer is reduced, and the thickness of the formed first barrier layer is smaller; in addition, the step coverage performance of the atomic layer deposition process is good, and the conformal coverage capability of the first barrier layer on the bottom and the side wall of the conductive through hole is improved; in summary, the embodiment of the invention is beneficial to reducing the difficulty of forming the diffusion barrier layer and improving the film quality of the diffusion barrier layer, and the thickness of the diffusion barrier layer is smaller, which is beneficial to improving the diffusion barrier resistance of the diffusion barrier layer to improve the Electromigration (EM) problem, thereby improving the reliability of the semiconductor structure, reducing the difficulty of filling the conductive plug in the conductive through hole, increasing the process window for forming the conductive plug, correspondingly reducing the RC delay of the rear section, and optimizing the performance of the semiconductor structure.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 5 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5, a substrate 100 is provided.
The substrate 100 is used to provide a process platform for a process recipe.
In this embodiment, a semiconductor device such as a transistor or a capacitor may be formed in the substrate 100, and a functional structure such as a resistive structure or a conductive structure may be formed in the substrate 100.
In this embodiment, for convenience of illustration and description, only the substrate 100 is illustrated in fig. 5.
With continued reference to fig. 5, a porous dielectric layer 105 is formed on the substrate 100.
The porous dielectric layer 105 is used to electrically isolate the interconnect structures in a Back end of line (BEOL) process. Specifically, in this embodiment, the subsequent step further includes forming conductive plugs in the porous dielectric layer 105, where the porous dielectric layer 105 is used to achieve electrical isolation between the conductive plugs.
In this embodiment, the porous dielectric layer 105 is an inter-metal dielectric (INTER METAL DIELECTRIC, IMD) layer.
The porous dielectric layer 105 has a porosity, that is, the porous dielectric layer 105 has a plurality of cavities or hollows therein, which is beneficial to reducing the k value (dielectric constant) of the porous dielectric layer 105, thereby being beneficial to reducing parasitic capacitance between interconnection structures, and further improving the performance of the device, for example: improving the back-end RC delay, increasing the signal transmission rate, reducing the power loss, etc.
Thus, in this embodiment, the porous dielectric layer 105 is a low-k dielectric material (low-k dielectric material generally refers to a dielectric material having a relative dielectric constant less than that of silicon oxide) or an ultra-low dielectric material (ultra-low-k dielectric material generally refers to a dielectric material having a relative dielectric constant less than or equal to 3.0).
In this embodiment, the material of the porous dielectric layer 105 is Black Diamond (BD). The low dielectric constant of the black diamond material is beneficial to improving the back-end RC delay.
In other embodiments, the material of the porous dielectric layer may be SiOCH, a Silsesquioxane (SSQ) based material, or a fluorine doped silicon oxide (FSG) material.
In this embodiment, the porous dielectric layer 105 may be formed on the substrate 100 by a deposition process such as a Plasma enhanced chemical vapor deposition (Plasma-ENHANCED CVD, PECVD) process.
Referring to fig. 6, a conductive via 200 is formed in the porous dielectric layer 105.
The conductive vias 200 are used to provide a spatial location for the subsequent formation of conductive plugs.
In this embodiment, a dry etching process is used, for example: and etching the porous dielectric layer 105 by an anisotropic dry etching process, and forming the conductive through holes 200 in the porous dielectric layer 105.
The anisotropic dry etching process has the characteristic of anisotropic etching, has good profile control, is beneficial to improving the profile appearance quality of the conductive through hole 200, and is beneficial to improving the etching precision and the etching efficiency by adopting the dry etching process.
Referring to fig. 7, a physical vapor deposition (Physical vapor deposition, PVD) process is used to conformally cover the nucleation layer 110 at the bottom and sidewalls of the conductive via 200.
The subsequent steps further comprise: a first barrier layer is conformally deposited over the nucleation layer 110 using an atomic layer deposition (Atomic layer deposition, ALD) process.
The nucleation layer 110 is used to provide a good interface for the subsequent formation of the first barrier layer. The nucleation layer 110 also serves to form a portion of the diffusion barrier.
In this embodiment, before the first barrier layer is formed, a physical vapor deposition process is adopted to conformally cover the nucleation layer 110 at the bottom and the side wall of the conductive via 200, which is favorable for improving the nucleation (Nucleation) rate during the subsequent formation of the first barrier layer, thereby improving the film continuity and the formation quality of the first barrier layer, and further improving the film quality and the diffusion preventing capability of the subsequent diffusion barrier layer.
Specifically, the nucleation layer 110 can be used as a growth point (i.e., nucleation point) for forming the first barrier layer subsequently, so that energy required for nucleation of the first barrier layer subsequently can be reduced, thereby remarkably improving the nucleation rate of the first barrier layer, reducing the nucleation difficulty, further being beneficial to improving the film continuity and uniformity of the first barrier layer subsequently, and correspondingly improving the film quality of the first barrier layer.
Moreover, by forming the nucleation layer 110 by using a physical vapor deposition process, the material of the nucleation layer 110 can be filled into the holes at the bottom and the side walls of the conductive via 200, so as to improve the surface roughness of the conductive via 200, thereby providing a smooth, flat and compact surface for the subsequent formation of the first barrier layer, thereby being beneficial to reducing the difficulty of the subsequent formation of the first barrier layer by using an atomic layer deposition process, and enabling the thickness of the formed first barrier layer to be smaller.
Specifically, in this embodiment, the physical vapor deposition process is a Sputtering process (Sputtering). Sputtering is typically performed in a vacuum system filled with an inert gas, by the action of a high-voltage electric field, so that the inert gas is ionized to generate an ion flow, the ion flow bombards a target cathode, and sputtered target material atoms or molecules deposit and accumulate on a layer to be sputtered to form a film. By adopting the sputtering process, the material atoms or molecules of the nucleation layer 110 can be sputtered into the voids at the bottom and the side walls of the conductive via 200, so as to fill the voids at the bottom and the side walls of the conductive via 200, thereby being beneficial to improving the surface roughness and the compactness of the bottom and the side walls of the conductive via 200. In addition, the physical vapor deposition process has the advantages of high stability, low process cost and wide application.
In this embodiment, the material of the nucleation layer 110 includes one or more of TaN, ta, ti and TiN.
In this embodiment, during the process of forming the nucleation layer 110, the nucleation layer 110 is further formed on top of the porous medium layer 105.
It should be noted that the thickness of the nucleation layer 110 is not too small or too large. If the thickness of the nucleation layer 110 is too small, the effect of the nucleation layer 110 for improving the interface quality (e.g., surface roughness) of the bottom and side walls of the conductive via 200 is not significant; if the thickness of the nucleation layer 110 is too large, the thickness of the diffusion barrier layer is too large, and thus the excessive space of the conductive via 200 is easily occupied, and the process window for forming the subsequent conductive plug is easily reduced. For this reason, in the step of forming the nucleation layer 110 of the present embodiment, the thickness of the nucleation layer 110 isTo the point of
In the step of forming the nucleation layer 110 by using the physical vapor deposition process, the Bias power (Bias power) of the physical vapor deposition process is not preferably too small or too large. If the bias power of the physical vapor deposition process is too small, the energy of deposited atoms or molecules is easily reduced, thereby making it difficult for the material of the nucleation layer 110 to enter into the conductive via 200, making it difficult for the nucleation layer 110 to be formed on the bottom and the sidewalls of the conductive via 200, or making it difficult for the thickness of the nucleation layer 110 formed in the conductive via 200 to satisfy the requirements; if the bias power of the physical vapor deposition process is too high, the energy of the deposited atoms or molecules is easily excessive, and thus the porous dielectric layer 105 at the bottom and the sidewall of the conductive via 200 is easily damaged. For this reason, in the step of forming the nucleation layer 110 by using the physical vapor deposition process, the bias power of the physical vapor deposition process is 100W to 500W.
In the step of forming the nucleation layer 110 using a physical vapor deposition process, the direct current power (DC power) of the physical vapor deposition process is preferably not too small or too large. If the dc power of the physical vapor deposition process is too small, the generated plasma density (PLASMA DENSITY) is easily caused to be too small, the generated plasma stability is poor, the deposition rate and deposition stability of the nucleation layer 110 are easily reduced, and further the production capacity is easily reduced, in addition, the too small dc power also easily causes the deposition thickness of the nucleation layer 110 to be too small, so that the process requirement is difficult to be satisfied; if the direct current power of the physical vapor deposition process is too high, the deposition thickness of the nucleation layer 110 is easily too high, and it is difficult to meet the requirement of the thickness of the nucleation layer 110. For this reason, in this embodiment, the dc power of the physical vapor deposition process is 8000W to 20000W.
Referring to fig. 8 and 9, a first barrier layer 115 is conformally coated over the nucleation layer 110 using an atomic layer deposition (Atomic layer deposition, ALD) process for forming a diffusion barrier 130 with the nucleation layer 110.
The diffusion barrier layer 130 is used to prevent the material of the subsequent conductive plug from diffusing into the porous dielectric layer 105, so as to improve Electromigration (EM) problem and improve the reliability of the semiconductor structure; the diffusion barrier layer 130 is also used as a barrier layer to prevent impurities such as carbon atoms and oxygen atoms in the porous dielectric layer 105 from diffusing into the conductive plugs, and further to prevent corrosion of the conductive plugs.
In this embodiment, before the first barrier layer 115 is formed, the bottom and the side walls of the conductive via 200 are conformally covered with the nucleation layer 110 by using a physical vapor deposition process, so that the nucleation rate of the first barrier layer 115 is advantageously increased when the first barrier layer 115 is formed, thereby improving the film continuity and the formation quality of the first barrier layer 115; moreover, the nucleation layer 110 improves the surface roughness of the conductive via 200, provides a smooth and flat surface for forming the first barrier layer 115, and is further beneficial to improving the thickness uniformity and film forming quality of the first barrier layer 115, which is beneficial to reducing the process difficulty of forming the first barrier layer 115 by adopting an atomic layer deposition process, and enabling the thickness of the formed first barrier layer 115 to be smaller.
In addition, the step coverage performance of the atomic layer deposition process is better, which is beneficial to improving the conformal coverage capability of the diffusion barrier layer at the bottom and the side wall of the conductive through hole 200. Specifically, the atomic layer deposition process is based on a Self-limiting reaction process of the atomic layer deposition process, and the film obtained by deposition can reach the thickness of a single layer of atoms, because the atomic layer deposition process can accurately deposit one atomic layer in each period, the atomic layer deposition process is selected to be favorable for accurately controlling the thickness of the first barrier layer 115, and the thickness of the first barrier layer 115 is smaller to meet the process requirements, and in addition, the film prepared by the ALD process has the characteristics of good bonding strength, consistent film thickness, good component uniformity, good shape retention and the like, and is favorable for improving the thickness uniformity and the film quality of the first barrier layer 115.
In summary, the embodiment of the invention is beneficial to reducing the difficulty of forming the diffusion barrier layer and improving the film quality of the diffusion barrier layer by adopting the physical vapor deposition process to form the nucleation layer 110 and then adopting the atomic layer deposition process to form the first barrier layer 115, thereby improving the diffusion barrier resistance of the diffusion barrier layer, further improving the effect of the diffusion barrier layer for improving Electromigration (EM) problem, improving the reliability of a semiconductor structure, and the thickness of the diffusion barrier layer formed by the embodiment of the invention is smaller, thereby being beneficial to increasing the forming space of the subsequent conductive plug, further reducing the difficulty of filling the conductive plug in the conductive through hole 200 and increasing the process window for forming the conductive plug.
The material of the first barrier layer 115 includes one or both of TaN and TiN. In this embodiment, the material of the first blocking layer 115 is TaN.
In the step of forming the first barrier layer 115 using an atomic layer deposition process, precursors used by the atomic layer deposition process include PDMAT [ (penta (dimethylamino) tantalum), ta (Nme 2)5 ] and NH 3, and the first barrier layer 115 is formed through multiple PDMAT and NH 3 deposition cycles, wherein PDMAT is a solid source material for chemical vapor deposition or atomic layer deposition of highly conformal TaN films to provide Ta atoms for forming the first barrier layer 115, and NH 3 provides an N source for forming the first barrier layer 115.
The thickness of the first barrier layer 115 is not too small or too large. If the thickness of the first barrier layer 115 is too small, the film quality of the first barrier layer 115 (e.g., poor film continuity) is easily reduced, thereby easily reducing the diffusion barrier preventing capability of the diffusion barrier layer 130; if the thickness of the first barrier layer 115 is too large, it is also easy to cause the thickness of the diffusion barrier layer to be too large. For this purpose, in the present embodiment, the thickness of the first barrier layer 115 isTo the point of
Referring to fig. 9 in combination, in this embodiment, after the first blocking layer 115 is formed, the method for forming a semiconductor structure further includes: a physical vapor deposition process is used to conformally cover the second barrier layer 120 over the first barrier layer 115 to form the diffusion barrier layer 130 with the first barrier layer 115 and the nucleation layer 110.
By also conformally covering the second barrier layer 120 over the first barrier layer 115 using a physical vapor deposition process, further improvements in the density and diffusion barrier resistance of the diffusion barrier layer 130 are facilitated.
In this embodiment, the diffusion barrier 130 is also formed on top of the porous dielectric layer 105.
The material of the second barrier layer 120 includes one or more of TaN, ta, ti and TiN. In this embodiment, the material of the second barrier layer 120 is TaN.
The thickness of the second barrier layer 120 is not too small nor too large. If the thickness of the second barrier layer 120 is too small, the effect of the second barrier layer 120 for improving the compactness and the diffusion barrier resistance of the diffusion barrier layer 130 is not obvious; if the thickness of the second barrier layer 120 is too large, it is easy to cause the thickness of the diffusion barrier layer 130 to be too large, so that it is difficult to increase the filling window of the subsequent conductive plug in the conductive via 200, and it is also difficult to improve the RC delay of the subsequent stage. For this reason, in the step of forming the second barrier layer 120 in this embodiment, the thickness of the second barrier layer 120 isTo the point of
In the step of forming the second barrier layer 120 by using a physical vapor deposition process, the dc power of the physical vapor deposition process should not be too low or too high. If the dc power of the physical vapor deposition process is too low, the generated plasma density (PLASMA DENSITY) is easily reduced, and the generated plasma stability is poor, so that the deposition rate and deposition stability of the second barrier layer 120 are easily reduced, and the deposition thickness of the second barrier layer 120 is easily reduced; if the dc power of the pvd process is too high, the deposition thickness of the second barrier layer 120 is easily too high, and thus the thickness of the diffusion barrier layer 130 is easily too high. For this reason, in the step of forming the second barrier layer 120 by using a physical vapor deposition process, the dc power of the physical vapor deposition process is 8000W to 20000W.
In the step of forming the second barrier layer 120 by using a physical vapor deposition process, the RF coil power (RF coil) of the physical vapor deposition process is not too small or too large. If the rf coil power of the physical vapor deposition process is too low, the ionization rate of the metal is easily caused to be too low, so that the deposition rate of the second barrier layer 120 is easily reduced; if the rf coil power of the physical vapor deposition process is too high, the ionization rate of the metal is easily caused to be too high, which not only easily causes poor deposition stability and uniformity of the second barrier layer 120 and easily causes too large thickness of the second barrier layer 120, but also may cause plasma damage (PLASMA DAMAGE) to the semiconductor structure, thereby easily affecting the performance of the semiconductor structure, and the rf coil power of the physical vapor deposition process is also easily damaged to the first barrier layer 115, affecting the film continuity of the first barrier layer 115, and even easily causing damage to the porous dielectric layer 105 due to the plasma passing through the first barrier layer 115. For this reason, in the step of forming the second barrier layer 120 by using a physical vapor deposition process, the rf coil power of the physical vapor deposition process is 1000W to 2000W.
In the step of forming the second barrier layer 120 by using a physical vapor deposition process, the bias power of the physical vapor deposition process should not be too low or too high. If the bias power of the physical vapor deposition process is too small, the kinetic energy of the deposited atoms or molecules is easily reduced, which in turn easily causes the second barrier layer 120 to be difficult to deposit on the first barrier layer 115 of the bottom and sidewalls of the conductive via 200; if the bias power of the physical vapor deposition process is too high, it tends to cause excessive kinetic energy of the deposited atoms or molecules, which tends to increase the probability of damage to the first barrier layer 115. For this reason, in the step of forming the second barrier layer 120 by using a physical vapor deposition process, the bias power of the physical vapor deposition process is 200W to 500W.
Referring to fig. 10, a conductive plug 140 is formed in the conductive via 200 in which the diffusion barrier 130 is formed.
The conductive plugs 140 are used to make electrical connection between devices in the substrate 100 (shown in fig. 5) and other interconnect structures or external circuits.
As can be seen from the foregoing steps, the thickness of the diffusion barrier layer 130 formed in the present embodiment is smaller, so that the space for forming the conductive plug 140 in the conductive via 200 is larger, which is beneficial to reducing the filling difficulty of the conductive plug 140 in the conductive via 200, increasing the process window for forming the conductive plug 140, and making the volume of the conductive plug 140 larger, which is beneficial to improving the RC delay in the subsequent process.
In addition, the diffusion barrier layer 130 has a strong step coverage capability in the conductive via 200, and the diffusion barrier layer 130 has a good formation quality, and the diffusion barrier layer 130 has a strong diffusion preventing capability, so that the material of the conductive plug 140 diffuses into the porous dielectric layer 105, or the probability that impurity atoms such as "carbon" and "oxygen" in the porous dielectric layer 105 diffuse into the conductive plug 140 is low, which is beneficial to improving electromigration.
In this embodiment, the conductive plug 140 is made of cobalt. In other embodiments, the conductive plugs may also be made of tungsten, copper, or other conductive materials.
In this embodiment, the step of forming the conductive plug 140 includes: filling a conductive material layer (not shown) in the conductive via 200 formed with the diffusion barrier layer 130, wherein the conductive material layer also covers the diffusion barrier layer 130 on top of the porous dielectric layer 105; the conductive material layer and diffusion barrier 130 are removed above the porous dielectric layer 105, and the remaining conductive material layer in the conductive via 200 serves as the conductive plug 140.
In this embodiment, a chemical vapor deposition process is used to form the conductive material layer.
In this embodiment, a planarization process is used to remove the conductive material layer and the diffusion barrier 130 above the porous dielectric layer 105. Specifically, the planarization process may be a chemical mechanical polishing process or the like.
Fig. 11 to 13 are schematic structural views corresponding to steps in a method for forming a semiconductor structure according to another embodiment of the present invention.
The present embodiment is the same as the previous embodiment, and will not be described again here. This embodiment differs from the previous embodiments in that: after forming the first barrier layer, before forming the conductive plug, the method for forming the semiconductor structure further comprises: and sputtering the first barrier layer, wherein the sputtering treatment is suitable for improving the density of the first barrier layer.
Referring to fig. 11, a first barrier layer 215 is conformally coated on the nucleation layer 210 using an atomic layer deposition process for forming a diffusion barrier layer 230 with the nucleation layer 210.
The step of forming the first barrier layer 215 is the same as that of the previous embodiment, and the description of this embodiment is omitted here.
Referring to fig. 12, after the first blocking layer 215 is formed, the method for forming a semiconductor structure further includes: the first barrier layer 215 is subjected to a sputtering process 400 adapted to increase the density of the first barrier layer 215.
By performing the sputtering process 400 on the first barrier layer 215, the density of the first barrier layer 215 is improved, so that the diffusion preventing capability of the diffusion barrier layer 230 is improved, the Electromigration (EM) problem is improved, the reliability of the semiconductor structure is correspondingly improved, the thickness of the diffusion barrier layer 230 is smaller, the filling capability of the subsequent conductive plug in the conductive through hole 300 is further improved, and the subsequent RC delay is further improved.
Specifically, during the sputtering process 400, atoms or molecules for forming the first barrier layer 215 are driven into the first barrier layer 215 to fill up the vacancies in the first barrier layer 215, thereby achieving the effect of improving the density of the first barrier layer 215.
In the step of performing the sputtering process 400 on the first barrier layer 215, the dc power of the sputtering process 400 is not preferably too low or too high. If the dc power of the sputtering process 400 is too low, it is easy to cause the generated plasma density (PLASMA DENSITY) to be too low, and the generated plasma stability to be poor, so that the effect of the sputtering process 400 for improving the density of the first barrier layer 215 is not obvious; if the DC power of the sputtering process 400 is too high, it is easy to form an additional barrier layer on the first barrier layer 215. For this reason, in the step of performing the sputtering process 400 on the first barrier layer 215 in this embodiment, the dc power of the sputtering process 400 is 100W to 2000W.
In the step of performing the sputtering process 400 on the first barrier layer 215, the RF coil power (RF coil power) of the sputtering process 400 is not too small or too large. If the rf coil power of the sputtering process 400 is too low, the ionization rate of the metal is easily reduced, and the effect of the sputtering process 400 for improving the density of the first barrier layer 215 is easily reduced; if the rf coil power of the sputtering process 400 is too high, the uniformity and stability of the sputtering process 400 are easily reduced, and other film structures are easily damaged, such as: damage is caused to the first barrier layer 215 and the porous dielectric layer. For this reason, in the step of performing the sputtering process 400 on the first barrier layer 215 in this embodiment, the rf coil power of the sputtering process 400 is 1000W to 2000W.
In the step of performing the sputtering process 400 on the first barrier layer 215, the bias power of the sputtering process 400 is not preferably too small or too large. If the bias power of the sputtering process 400 is too small, it is easy to cause too small kinetic energy of sputtered atoms or molecules, so that the atoms or molecules are difficult to be driven into the first barrier layer 215, and thus the effect of improving the compactness of the first barrier layer 215 is difficult to be achieved; if the bias power of the sputtering process 400 is too high, damage to the first barrier layer 215 is easily caused. For this reason, in the step of performing the sputtering process 400 on the first barrier layer 215 in this embodiment, the bias power of the sputtering process 400 is 200W to 400W.
In addition, in the step of performing the sputtering process 400 on the first barrier layer 215, the dc coil power of the sputtering process 400 is 0W to 1000W, so that it is possible to ensure that atoms or molecules are sputtered into the first barrier layer 215 located at the bottom and the sidewall of the conductive via 300, thereby improving the uniformity of the sputtering process 400.
Referring to fig. 13, a conductive plug 240 is formed in the conductive via 300 in which the diffusion barrier 230 is formed.
The step of forming the conductive plugs 240 is the same as that of the previous embodiment, and the description of this embodiment is omitted here.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 10, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100 (shown in fig. 5); a porous dielectric layer 105 on the substrate 100, wherein a conductive via 200 (as shown in fig. 9) is formed in the porous dielectric layer 105; a nucleation layer 110 conformally covering the bottom and the sidewalls of the conductive via 200, the nucleation layer 110 being formed by a physical vapor deposition process; a first barrier layer 115 conformally overlying the nucleation layer 110, the first barrier layer 115 being formed by an atomic layer deposition process for forming a diffusion barrier layer 130 with the nucleation layer 110; and a conductive plug 140 filled in the conductive via 200 and contacting the diffusion barrier 130.
In this embodiment, by disposing the nucleation layer 110 conformally covering the bottom and the sidewalls of the conductive via 200 in the semiconductor structure, the nucleation layer 110 is beneficial to improving the nucleation rate when forming the first barrier layer 115, thereby improving the film continuity and the film quality of the first barrier layer 115; moreover, the nucleation layer 110 is formed by a physical vapor deposition process, which is beneficial to improving the surface roughness of the conductive via 200 of the nucleation layer 110, providing a smooth and flat surface for the formation of the first barrier layer 115, and further improving the thickness uniformity and film quality of the first barrier layer 115.
In addition, the first barrier layer 115 is formed by an atomic layer deposition process, and the step coverage performance of the atomic layer deposition process is better, which is beneficial to improving the conformal coverage capability of the first barrier layer 115 at the bottom and the side wall of the conductive via 200, and is beneficial to making the thickness of the first barrier layer 115 smaller.
In summary, the embodiment of the present invention is beneficial to improving the film quality of the diffusion barrier layer 130, thereby improving the capability of preventing diffusion barrier of the diffusion barrier layer 130, further being beneficial to improving the electromigration problem, and improving the reliability of the semiconductor structure, and the thickness of the diffusion barrier layer 130 of the embodiment of the present invention is smaller, thereby increasing the formation space and volume of the conductive plug 140, further being beneficial to improving the post RC delay, and optimizing the performance of the semiconductor structure.
The substrate 100 is used to provide a process platform for a process recipe.
In this embodiment, a semiconductor device such as a transistor or a capacitor may be formed in the substrate 100, and a functional structure such as a resistive structure or a conductive structure may be formed in the substrate 100.
The porous dielectric layer 105 is used to electrically isolate the interconnect structures in a Back end of line (BEOL) process. Specifically, in this embodiment, the porous dielectric layer 105 is used to achieve electrical isolation between the conductive plugs 140.
In this embodiment, the porous dielectric layer 105 is an inter-metal dielectric (INTER METAL DIELECTRIC, IMD) layer.
The porous dielectric layer 105 has a porosity, that is, the porous dielectric layer 105 has a plurality of cavities or hollows therein, which is beneficial to reducing the k value (dielectric constant) of the porous dielectric layer 105, thereby being beneficial to reducing parasitic capacitance between interconnection structures, and further improving the performance of the device, for example: improving the back-end RC delay, increasing the signal transmission rate, reducing the power loss, etc.
Therefore, in this embodiment, the porous dielectric layer 105 is a low-k dielectric material (low-k dielectric material generally refers to a dielectric material having a relative dielectric constant smaller than that of silicon oxide) or an ultra-low dielectric material (ultra-low-k dielectric material generally refers to a dielectric material having a relative dielectric constant smaller than or equal to 3.0).
In this embodiment, the material of the porous dielectric layer 105 is Black Diamond (BD). The low dielectric constant of the black diamond material is beneficial to improving the back-end RC delay.
In other embodiments, the material of the porous dielectric layer may be SiOCH, a Silsesquioxane (SSQ) based material, or a fluorine doped silicon oxide (FSG) material.
The conductive vias 200 are used to provide a spatial location for the formation of the conductive plugs 140.
The nucleation layer 110 is used to provide a good interface for the formation of the first barrier layer 115. The nucleation layer 110 also serves to form a portion of the diffusion barrier 130.
Specifically, the nucleation layer 110 can be used as a growth point (i.e., nucleation point) of the first barrier layer 115, so that energy required for nucleation of the first barrier layer 115 can be reduced, thereby significantly improving the nucleation rate of the first barrier layer 115, reducing the nucleation difficulty, and further being beneficial to improving the film continuity and uniformity of the first barrier layer 115; moreover, by forming the nucleation layer 110 using a physical vapor deposition process, the material of the nucleation layer 110 can be filled into the holes of the bottom and sidewalls of the conductive via 200 to improve the surface roughness of the conductive via 200, providing a smooth, flat and dense surface for the formation of the first barrier layer 115.
In this embodiment, the material of the nucleation layer 110 includes one or more of TaN, ta, ti and TiN.
It should be noted that the thickness of the nucleation layer 110 is not too small or too large. If the thickness of the nucleation layer 110 is too small, the effect of the nucleation layer 110 for improving the interface quality (e.g., surface roughness) of the bottom and side walls of the conductive via 200 is not significant; if the thickness of the nucleation layer 110 is too large, the thickness of the diffusion barrier layer 130 is too large, which in turn causes the diffusion barrier layer 130 to occupy too much space of the conductive via 200, accordingly, the filling capability of the conductive plug 140 in the conductive via 200 is easily reduced, and it is difficult to improve the back-end RC delay. For this purpose, in the present embodiment, the thickness of the nucleation layer 110 isTo the point of
The first barrier layer 115 is formed by an atomic layer deposition process, and the thickness uniformity of the first barrier layer 115 and the conformal coverage capability of the first barrier layer 115 at the bottom and the side wall of the conductive via 200 are both good, so that the film quality of the diffusion barrier layer 130 is improved, the diffusion barrier preventing capability of the diffusion barrier layer 130 is further improved, the Electromigration (EM) problem is improved correspondingly, and the reliability of the semiconductor structure is improved.
And the thickness of the film formed by the atomic layer deposition process is smaller, so that the thickness of the first barrier layer 115 is smaller, which is beneficial to making the thickness of the diffusion barrier layer 130 smaller, thereby being beneficial to making the formation space of the conductive plug 140 in the conductive through hole 200 larger, and further improving the back-end RC delay.
The material of the first barrier layer 115 includes one or both of TaN and TiN. In this embodiment, the material of the first blocking layer 115 is TaN.
The thickness of the first barrier layer 115 is not too small or too large. If the thickness of the first barrier layer 115 is too small, the film quality of the first barrier layer 115 (e.g., poor film continuity) is easily reduced, thereby easily reducing the diffusion barrier preventing capability of the diffusion barrier layer 130; too large a thickness of the diffusion barrier 130 is also easily caused if the thickness of the first barrier 115 is too large. For this purpose, in the present embodiment, the thickness of the first barrier layer 115 isTo the point of
In this embodiment, the semiconductor structure further includes: a second barrier layer 120 located between the first barrier layer 115 and the conductive plug 140, the second barrier layer 120 being formed by a physical vapor deposition process for forming the diffusion barrier layer 130 with the first barrier layer 115 and the nucleation layer 110.
By further providing the second barrier layer 120 between the first barrier layer 115 and the conductive plug 140, and forming the second barrier layer 120 by a physical vapor deposition process, the density and the diffusion barrier preventing capability of the diffusion barrier layer 130 are further improved.
The material of the second barrier layer 120 includes one or more of TaN, ta, ti and TiN. In this embodiment, the material of the second barrier layer 120 is TaN.
The thickness of the second barrier layer 120 is not too small nor too large. If the thickness of the second barrier layer 120 is too small, the effect of the second barrier layer 120 for improving the compactness and the diffusion barrier resistance of the diffusion barrier layer 130 is not obvious; if the thickness of the second barrier layer 120 is too large, it is easy to cause the thickness of the diffusion barrier layer 130 to be too large, so that it is difficult to increase the filling window of the conductive plug in the conductive via 200 and to improve the RC delay of the back stage. For this purpose, in this embodiment, the thickness of the second barrier layer 120 isTo the point of
The conductive plugs 140 are used to make electrical connection between devices in the substrate 100 and other interconnect structures or external circuits.
In this embodiment, the conductive plug 140 is made of cobalt. In other embodiments, the conductive plugs may also be made of tungsten, copper, or other conductive materials.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
Providing a substrate;
Forming a porous dielectric layer on the substrate;
forming a conductive through hole in the porous medium layer;
Forming a nuclear layer on the bottom and the side wall of the conductive through hole in a conformal mode by adopting a physical vapor deposition process; an atomic layer deposition process is adopted, and a first barrier layer is conformally covered on the nucleation layer and used for forming a diffusion barrier layer with the nucleation layer;
Forming a conductive plug in the conductive via hole formed with the diffusion barrier layer;
after forming the first barrier layer, before forming the conductive plug, the method for forming the semiconductor structure further comprises: and sputtering the first barrier layer, and striking atoms or molecules for forming the first barrier layer into the first barrier layer to fill up vacancies in the first barrier layer, so that the compactness of the first barrier layer is improved.
2. The method of forming a semiconductor structure of claim 1, wherein after forming the first barrier layer, prior to forming the conductive plug, the method of forming a semiconductor structure further comprises: and a physical vapor deposition process is adopted to cover a second barrier layer on the first barrier layer in a conformal manner, and the second barrier layer is used for forming the diffusion barrier layer together with the first barrier layer and the nucleation layer.
3. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the nucleation layer, the thickness of the nucleation layer isTo the point of
4. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the nucleation layer using a physical vapor deposition process, parameters of the physical vapor deposition process include: the bias power is 100W to 500W, and the direct current power is 8000W to 20000W.
5. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the first barrier layer, a thickness of the first barrier layer isTo the point of
6. The method of forming a semiconductor structure of claim 2, wherein in the step of forming the second barrier layer, a thickness of the second barrier layer isTo the point of
7. The method of forming a semiconductor structure of claim 2, wherein in the step of forming the second barrier layer using a physical vapor deposition process, parameters of the physical vapor deposition process include: the direct current power is 8000W to 20000W, the radio frequency coil power is 1000W to 2000W, and the bias power is 200W to 500W.
8. The method of forming a semiconductor structure of claim 1, wherein in the step of performing a sputtering process on the first barrier layer, parameters of the sputtering process include: the DC power is 100W to 2000W, the RF coil power is 1000W to 2000W, the bias power is 200W to 400W, and the DC coil power is 0W to 1000W.
9. The method of forming a semiconductor structure of claim 1, wherein the material of the nucleation layer comprises one or more of TaN, ta, ti and TiN.
10. The method of forming a semiconductor structure of claim 1, wherein the material of the first barrier layer comprises one or both of TaN and TiN.
11. The method of forming a semiconductor structure of claim 2, wherein the material of the second barrier layer comprises one or more of TaN, ta, ti and TiN.
12. The method of claim 1, wherein in the step of forming the first barrier layer using an atomic layer deposition process, the precursors used by the atomic layer deposition process include PDMAT and NH 3.
13. The method of claim 1, wherein the porous dielectric layer is made of a low-k dielectric material or an ultra-low-k dielectric material.
14. The method of forming a semiconductor structure of claim 1, wherein the material of the porous dielectric layer comprises SiOCH, black diamond, silsesquioxane-based material, or fluorine doped silicon oxide.
15. A semiconductor structure, comprising:
A substrate;
A porous dielectric layer on the substrate, wherein a conductive through hole is formed in the porous dielectric layer;
the nucleation layer is conformally covered on the bottom and the side wall of the conductive through hole, and the nucleation layer is formed through a physical vapor deposition process;
The first barrier layer is conformally covered on the nucleation layer, is formed through an atomic layer deposition process and is used for forming a diffusion barrier layer with the nucleation layer, the first barrier layer is subjected to sputtering treatment, atoms or molecules for forming the first barrier layer are beaten into the first barrier layer so as to fill vacancies in the first barrier layer, and the density of the first barrier layer is improved;
and the conductive plug is filled in the conductive through hole and is contacted with the diffusion barrier layer.
16. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: and the second barrier layer is positioned between the first barrier layer and the conductive plug, is formed through a physical vapor deposition process and is used for forming the diffusion barrier layer together with the first barrier layer and the nucleation layer.
17. The semiconductor structure of claim 15, wherein the nucleation layer has a thickness ofTo the point of
18. The semiconductor structure of claim 15, wherein the first barrier layer has a thickness ofTo the point of
19. The semiconductor structure of claim 16, wherein a thickness of the second barrier layer isTo the point of
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