KR100387265B1 - Method of manufacturing a metal wiring and a capacitor in a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a metal wiring and a capacitor of a semiconductor device, and to maintaining a dual damascene patterning process in a process of manufacturing a metal-insulator-metal capacitor having a high capacitance. High-k with a three-dimensional structure in the damascene pattern using a MIM capacitor manufacturing method that is compatible with the copper dual damascene wiring process that embeds a common damascene pattern into copper. ) By manufacturing MIM (Metal-Insulator-Metal) capacitors, MIM capacitors and Cu wirings can be formed on the same layer without adding metal layers, and the capacitance of capacitors can be secured to improve the electrical characteristics of the devices. Disclosed are a wiring and capacitor manufacturing method.

Description

Method of manufacturing a metal wiring and a capacitor in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring and a capacitor manufacturing method of a semiconductor device, and more particularly, to a metal wiring and a capacitor manufacturing method of a semiconductor device capable of increasing capacitance by forming a three-dimensional structure in a dual damascene pattern.

In general, a capacitor, which is a passive component, is manufactured during the device fabrication process to configure various logic devices. In this case, the manufactured capacitor includes a coupling coupling for an impedance matching between a decoupling capacitor in a MPU device, a system on a chip (SOC) device, and a block in a radio frequency (RF) device. And a capacitor array in a coupling bypass capacitor, an analog to digital (AD), or a digital to analog converter (DA) converter. These capacitors are made of junction capacitors using silicon junctions, or, in conventional aluminum (Al) wiring technology, Al / SiN / Al metal-insulator-metal (MIM) using PECVD SiN film as a dielectric film. ) Is made of a capacitor.

However, as the operating frequency increases and as the bits of the converter increase, more and more capacitors are needed.For CPUs operating at 1 GHz, for example, a capacitor capacity of 400 nF is required for decoupling. need. At this time, the capacitance is obtained (Capacitance) which may be the 34.5nF / mm ² when the Toxeq 1nm, eventually in order to obtain a capacitance of 400nF required area of 11.6mm ^2. The dielectric constant of PECVD SiN 1000Å currently used when referred to 7, rough Toxeq is 56nm, the capacitance has to manufacture the capacitor, the area is about 645mm ² in order to obtain the capacitance of the so 0.62nF / mm ² 400nF. Capacitors of this size are difficult to actually apply in semiconductor chip manufacturing.

Therefore, in order to solve the above problem, the present invention provides a dual damascene method using a MIM capacitor manufacturing method which is compatible with a copper dual damascene wiring process in which a general damascene pattern is embedded with copper. While maintaining the dual damascene patterning process, a three-dimensional high-k metal-insulator-metal (MIM) capacitor with a three-dimensional structure is fabricated in the damascene pattern, so that the MIM capacitor and the Cu wiring can be layered without adding a metal layer. The purpose of the present invention is to provide a method of manufacturing a metal wiring and a capacitor of a semiconductor device which can be formed at the same time and secure the capacitance of the capacitor to improve the electrical characteristics of the device.

1A to 1G are cross-sectional views of devices sequentially shown in order to explain a metal wiring and a capacitor manufacturing method of a semiconductor device according to the present invention.

FIG. 2 is a lay out view showing the shape of a trench formed by the process of FIG. 1B in a planar state. FIG.

<Description of the symbols for the main parts of the drawings>

1, 21: semiconductor substrate 2, 22: interlayer insulating film

3, 23: 1st metal wiring 4, 24: 1st metal diffusion prevention film

5, 25: 1st insulating film 6, 26: etching prevention film

7, 27: second insulating film 8, 28: hard mask

9a, 29a: trenches 9b, 29b: vias

9, 29: dual damascene pattern 10, 30: second metal diffusion barrier

11, 31: 2nd metal wiring 12, 32: Photosensitive film pattern

13, 33: lower electrode 14, 34: dielectric film

15, 35: upper electrode 16, 36: third metal diffusion barrier

17, 37: 3rd metal wiring 100, 200: MIM capacitor

A: capacitor formation area

A first embodiment of a method for manufacturing a metal wiring and a capacitor of a semiconductor device according to the present invention is a dual region consisting of trenches or trenches and vias by etching a predetermined region of an interlayer insulating film consisting of a first insulating film, an anti-etching film, a second insulating film and a hard mask. Providing a semiconductor substrate having a damascene pattern, forming a first metal diffusion barrier on the semiconductor substrate, depositing a metal material on the semiconductor substrate, and then forming a metal material on the interlayer insulating layer by a chemical mechanical polishing process. (1) forming a first metal wiring on a trench or a dual damascene pattern by removing the metal diffusion barrier layer, and forming a photoresist pattern on which a region where a capacitor is to be formed is exposed to form a photoresist pattern; 2 removing the insulating film and then removing the photoresist pattern, including the first metal wiring Sequentially forming a lower electrode, a dielectric film, an upper electrode, and a second metal diffusion barrier on a whole, depositing a metal material on the whole, and completely filling the rest of the space from which the second insulating film is removed, and chemically Mechanical polishing is performed to remove and planarize the metal material, the second metal diffusion barrier film, the upper electrode, the dielectric film, and the lower electrode on the second insulating film to form a second metal wiring and simultaneously form a capacitor.

The anti-etching film or the hard mask is formed by depositing a SiN or SiC film with a thickness in the range of 100 to 1000 Å by PECVD method, and the first insulating film or the second insulating film is formed by using SiO ₂ , FSG or a low dielectric constant insulating film having a dielectric constant of 3.0 or less. It is formed by a PECVD method, an HDP-CVD method, an APCVD method, or a spin coating method that can be carried out at a temperature of not more than ℃.

The trench or dual damascene pattern is formed in the serpentine form, but the entire area of the trench or dual damascene pattern is formed in consideration of the target capacitance of the capacitor manufactured in the final process.

The first metal diffusion barrier film or the second metal diffusion barrier film is formed by depositing and combining Ta, TaN, TiN, WN, TaC, WC, TiSiN, or at least one of them by PVD, CVD, or ALD. At this time, before forming the first metal diffusion barrier, cleaning with argon sputtering or reactive cleaning with plasma containing hydrogen such as H ₂ or NH ₃ may be performed in a high vacuum deposition apparatus.

The first metal wiring or the second metal wiring is formed by using Cu as a metal material, forming a Cu seed layer by PVD or CVD, and then embedding a trench or dual damascene pattern by Cu electroplating, or by electroplating. After forming a Cu seed layer by using Cu deposition, a trench or a dual damascene pattern is embedded by electroless or electroplating, or a trench or a dual damascene pattern is embedded by a method in which the above embedding method is mixed.

The hard mask is removed by a plasma dry etching process using a fluorine-containing gas, and then the second insulating film is removed by using a solution containing HF when formed of SiO ₂ , FSG, SiOC, SiOH, or SiOCH components. When formed with a low dielectric constant insulating film, it is removed using a 0 ₂ plasma.

The lower electrode or the upper electrode is formed by depositing Pt, Ru, Ir or W by CVD, PVD or ALD. Before forming the lower electrode, a glue layer such as TiN, TiAlN, or TiSiN may be formed as an adhesive layer on the interlayer insulating film in order to improve adhesive properties.

The dielectric film is formed by depositing a Ta oxide film, Ba-Sr-Ti oxide, Zr oxide, Hf oxide, Pb-Zn-Ti oxide, Sr-Bi-Ta oxide by CVD, PVD or ALD.

Hereinafter, a first embodiment of the present invention will be described in more detail with reference to the accompanying drawings.

1A to 1G are cross-sectional views of devices sequentially shown in order to explain a first embodiment of a metal wiring and a capacitor manufacturing method of a semiconductor device according to the present invention. FIG. 2 is a lay out view showing the shape of a trench formed by the process of FIG. 1B in a planar state. FIG.

Referring to FIG. 1A, an interlayer insulating film 2 is formed on a semiconductor substrate 1 on which various elements for forming a semiconductor device are formed in a predetermined process, and then a predetermined region of the interlayer insulating film 2 is etched by an etching process. The metal material is then buried to form the first metal wiring 3. At this time, in the present invention, the first metal wiring 3 is formed of copper wiring using copper as the metal material. Thereafter, the metal diffusion barrier 4, the first insulating layer 5, the etch barrier 6, the second insulating layer 7, and the hard mask 8 are sequentially formed on the whole including the entire first metal wiring 3. do.

In the above, the metal diffusion barrier film 4, the etch barrier film 6, or the hard mask 8 is formed by depositing a SiN or SiC film in a thickness ranging from 100 to 1000 mW by PECVD. In addition, the first insulating film 5 and the second insulating film 7 can be implemented at a temperature of 450 ° C. or less using ordinary SiO ₂ , Fluorine doped Silicate Glass (FSG), or a low dielectric constant insulating film having a dielectric constant of 3.0 or less; It is formed by HDP-CVD, APCVD, or spin coating. In general, a dual damascene patterning method to be formed in a subsequent process or a process of forming the etch stop layer 6 or the hard mask 8 may be omitted depending on the type of film deposited to form the insulating layer. .

1B and 2, a trench 9a is formed by etching a predetermined region of the second oxide layer 7 by an etching process using the patterned hard mask 7 as an etching mask. In the process of performing the etching process for forming the trench 9a, the first oxide layer 5 is not etched by the etch stop layer 6. After removing the predetermined region of the etch stop layer 6 exposed while the trench 9a is formed, the first metal diffusion barrier layer 4 and the exposed region of the first oxide layer 5 are etched by an etching process to etch the first metal. A via 9b through which the wiring 3 is exposed is formed. As a result, the dual damascene pattern 9 formed of the trench 9a and the via 9b is formed.

In general, the method of forming the dual damascene pattern 9 may form a trench after forming the via first, and may be formed by various methods such as a method using a dual top hardmask.

At this time, the form of the formed trench 9a or dual damascene pattern 9 is a serpentine structure that is serpentine, as shown in FIG. Therefore, the trench 9a of the entire serpentine structure is in a state of being long and meandering, and is electrically connected to the wiring of the first metal wiring 3 through the via 9b. In addition, the total area of the trenches 9a connected by the serpentine structure is formed in consideration of the required capacitance.

Referring to FIG. 1C, after the second metal diffusion barrier film 10 and the second metal wiring metal material are deposited on the entire surface including the dual damascene pattern 9, chemical mechanical polishing is performed on the hard mask 8. 2 The metal diffusion barrier film 10 and the metal material are removed and planarized. As a result, the metal material is embedded only in the dual damascene pattern 9 to form the second metal wiring 11. In the present invention, copper (Cu) is used as the metal material.

The second metal diffusion barrier 10 is deposited to prevent the deterioration of the characteristics of the CMOS device or the insulation of the dielectric due to the deterioration of the electrical characteristics of the capacitor due to the copper outdiffusion. do. The second metal diffusion barrier 10 may be cleaned using argon sputter or reactive cleaning using plasma containing hydrogen such as H ₂ or NH ₃ in a high vacuum deposition apparatus. Thereafter, at least one or more of Ta, TaN, TiN, WN, TaC, WC, TiSiN, or a combination of these layers is deposited and deposited by PVD, CVD, or atomic layer deposition (ALD).

Copper embedding into the dual damascene pattern 9 for forming the second metal wiring 11 is performed by Cu electroplating after forming a Cu seed layer (not shown) by PVD or CVD. Alternatively, the Cu seed layer is formed by Cu deposition using an electroplating method and then electroless or electroplating is performed. Or Cu is embedded by the vapor deposition method which combined the said method suitably.

Referring to FIG. 1D, the photoresist pattern 12 is formed by performing a photo process using a predetermined mask so that the region where the MIM capacitor is to be formed is opened in a subsequent process. At this time, the photoresist pattern 12 exposes the trench 9a of the serpentine structure as shown in FIG. 2.

Referring to FIG. 1E, the photoresist pattern 12 is formed to expose only the region A in which the capacitor is to be formed, and then the hard mask 8 and the second insulating layer 7 in the region A in which the capacitor is to be formed are etched. To remove it. When the hard mask 8 and the second insulating film 7 are removed, the photosensitive film pattern 12 is also removed.

In the etching process of the hard mask 8 and the second insulating film 7, the hard mask 8 is removed by a plasma dry etching process using a fluorine-containing gas, and then the hard mask 8 ) Is removed to remove the second insulating film 7 in the exposed area. In this case, when the second insulating film 7 is composed of SiO ₂ , FSG, SiOC, SiOH, and SiOCH components, it is removed using a solution containing HF, and in the case of being formed of a polymer-based low dielectric insulating film, 0 ₂ plasma. To remove it. The first insulating film 5 formed under the second insulating film 7 is not etched or damaged by the etch stop film 6.

Referring to FIG. 1F, the lower electrode 13, the dielectric layer 14, the upper electrode 15, and the third metal diffusion barrier layer 16 are disposed on the entire surface including the second metal wires exposed to the capacitor formation region A. FIG. ) Are formed sequentially.

The lower electrode 13 and the upper electrode 15 are formed by depositing Pt, Ru, Ir or W by CVD, PVD or ALD. In this case, when the adhesion between the lower electrode 13 and the lower element is poor, a lower layer of the lower electrode 13 is formed after forming a glue layer such as TiN, TiAlN, or TiSiN. The dielectric film 14 is formed by depositing a Ta oxide film, Ba-Sr-Ti oxide, Zr oxide, Hf oxide, Pb-Zn-Ti oxide, Sr-Bi-Ta oxide by CVD, PVD, or ALD. The third metal diffusion barrier film 16 is formed in order to prevent the Cu component of the metal wiring to be formed in the subsequent process from deteriorating the electrical characteristics of the lower capacitor due to out diffusion. The third metal diffusion barrier film 16 forms the same method as the method for forming the second metal diffusion barrier film 10 formed in FIG. 1C.

Referring to FIG. 1G, a chemical mechanical polishing is performed after depositing a metal material on the entire upper portion of the capacitor formation region A to a thickness sufficient to fill the remaining space of the portion where the second insulating film 7 is etched. All the layers on the hard mask 8 are removed and planarized to form the third metal wiring 17. At this time, the metal material is deposited in the same manner as the metal material deposition method for the second metal wiring performed in FIG. 1C.

As a result, the MIM capacitor 100 having a three-dimensional structure is manufactured using the trench 9a or the dual damascene pattern 9.

Subsequently, although not shown in the drawings, in the case where additional metal wiring formation is required on the third metal wiring 17, the respective insulating films are formed again after the deposition of the metal diffusion barrier film, and the same method as the metal wiring forming process described above. The process proceeds to form additional metal wiring. In the subsequent process, the entire wiring of the MIM capacitor is formed by electrically connecting the upper electrode of the MIM capacitor region with a metal wiring process.

According to a second embodiment of the method of manufacturing a metal wiring and a capacitor of a semiconductor device according to the present invention, a predetermined region of an interlayer insulating film including a first insulating film, an etch stop film, a second insulating film, and a hard mask is etched to form a dual layer formed of a trench or a trench and a via Providing a semiconductor substrate having a damascene pattern, forming a first metal diffusion barrier layer on the semiconductor substrate, depositing a metal material on the semiconductor substrate, and then chemically polishing the metal material on the interlayer insulating layer. And removing the first metal diffusion barrier to form a first metal wire in the trench or dual damascene pattern, and forming a photoresist pattern in which the region where the capacitor is to be formed is exposed to form a photoresist pattern so that the hard mask of the exposed region is not formed. Removing the photoresist pattern after removing the second insulating film and the first metal wiring. Step, sequentially forming a lower electrode, a dielectric layer, an upper electrode, and a second metal diffusion barrier on the whole including the first metal diffusion barrier, and depositing a metal material on the whole to rest the space in which the second insulating layer is removed. Filling the part completely and performing chemical mechanical polishing to remove and planarize the metal material, the second metal diffusion barrier film, the upper electrode, the dielectric film, and the lower electrode on the second insulating film to form a second metal wiring and simultaneously Forming step.

The etch stop layer or the hard mask is formed by depositing a SiN or SiC layer in a thickness ranging from 100 to 1000 으로 by PECVD, and the first insulating layer or the second insulating layer is formed by using SiO ₂ , FSG, or a dielectric constant of 3.0 or less. It is formed by a PECVD method, an HDP-CVD method, an APCVD method, or a spin coating method that can be carried out at a temperature of not more than ℃.

The trench or dual damascene pattern is formed in the serpentine form, but the entire area of the trench or dual damascene pattern is formed in consideration of the target capacitance of the capacitor manufactured in the final process.

The first metal diffusion barrier film or the second metal diffusion barrier film is formed by depositing and combining Ta, TaN, TiN, WN, TaC, WC, TiSiN, or at least one of them by PVD, CVD, or ALD. At this time, before forming the first metal diffusion barrier, cleaning with argon sputtering or reactive cleaning with plasma containing hydrogen such as H ₂ or NH ₃ may be performed in a high vacuum deposition apparatus.

The first metal wiring or the second metal wiring is formed by using Cu as a metal material, forming a Cu seed layer by PVD or CVD, and then embedding a trench or dual damascene pattern by Cu electroplating, or by electroplating. After forming a Cu seed layer by using Cu deposition, a trench or a dual damascene pattern is embedded by electroless or electroplating, or a trench or a dual damascene pattern is embedded by a method in which the above embedding method is mixed.

The hard mask is removed by a plasma dry etching process using a fluorine-containing gas, and then the second insulating film is removed by using a solution containing HF when formed of SiO ₂ , FSG, SiOC, SiOH, or SiOCH components. When formed with a low dielectric constant insulating film, it is removed using a 0 ₂ plasma. In addition, the first metal wire or metal material is removed using an acid solution such as HCI or H ₂ SO ₄ as an etchant.

The lower electrode or the upper electrode is formed by depositing Pt, Ru, Ir or W by CVD, PVD or ALD. Before forming the lower electrode, a glue layer such as TiN, TiAlN, or TiSiN may be formed as an adhesive layer on the interlayer insulating film in order to improve adhesive properties.

The dielectric film is formed by depositing a Ta oxide film, Ba-Sr-Ti oxide, Zr oxide, Hf oxide, Pb-Zn-Ti oxide, Sr-Bi-Ta oxide by CVD, PVD or ALD.

Hereinafter, a second embodiment of the present invention will be described in more detail with reference to the accompanying drawings.

3A to 3D are cross-sectional views of devices sequentially shown in order to explain a first embodiment of a metal wiring and a capacitor manufacturing method of a semiconductor device according to the present invention. FIG. 2 is a lay out view showing the shape of a trench formed by the process of FIG. 1B in a planar state. FIG.

Referring to FIG. 3A, the processes of FIGS. 1A to 1D are performed in the same manner as in the first embodiment of the method of manufacturing the metal wiring and the capacitor of the semiconductor device, thereby forming the photosensitive film pattern 32.

Referring to FIG. 3B, the photoresist pattern 32 is formed to expose only the region A in which the capacitor is to be formed, and then the hard mask 28, the second insulating layer 27, and the second region of the region A in which the capacitor is to be formed. The metal wiring 31 is removed by an etching process. When the hard mask 28, the second insulating film 27, and the second metal wiring 31 are removed, the photosensitive film pattern 32 is also removed.

In the etching process of the hard mask 28 and the second insulating layer 27, the hard mask 28 is removed by a plasma dry etching process using a fluorine-containing gas, and then the hard mask 28 ) Is removed to remove the second insulating layer 27 in the exposed area. At this time, when the second insulating film 27 is composed of SiO ₂ , FSG, SiOC, SiOH, SiOCH components, it is removed using a solution containing HF, and 0 ₂ plasma when it is formed of a polymer dielectric low dielectric constant insulating film. To remove it. The first insulating layer 25 formed under the second insulating layer 27 is not etched or damaged by the etch stop layer 26. Thereafter, the second metal wire 31 is etched and removed using an acid solution such as HCI or H ₂ SO ₄ as an etchant.

Referring to FIG. 3C, the lower electrode 33, the dielectric film 34, the upper electrode 35, and the third metal are disposed on the whole including the second metal diffusion barrier 30 exposed in the capacitor formation region A. FIG. The diffusion barrier 36 is formed sequentially.

The lower electrode 33 and the upper electrode 35 are formed by depositing Pt, Ru, Ir or W by CVD, PVD or ALD. At this time, when the adhesion characteristics (Adhesion) of the lower electrode 33 and the lower element is poor, after forming a glue layer (Glue layer) such as TiN, TiAlN or TiSiN, the lower electrode 33 is deposited. The dielectric film 34 is formed by depositing a Ta oxide film, Ba-Sr-Ti oxide, Zr oxide, Hf oxide, Pb-Zn-Ti oxide, Sr-Bi-Ta oxide by CVD, PVD, or ALD. The third metal diffusion barrier film 16 is formed in order to prevent the Cu component of the metal wiring to be formed in the subsequent process from deteriorating the electrical characteristics of the lower capacitor due to out diffusion. The third metal diffusion barrier film 36 forms the same method as the method of forming the second metal diffusion barrier film 10 formed in FIG. 1C.

Referring to FIG. 3D, the upper portion of the entire metal material is thick enough to sufficiently fill the remaining space of the portion where the second insulating layer 27 and the second metal wiring 31 are etched in the capacitor formation region A. FIG. After deposition on the substrate, chemical mechanical polishing is performed to remove all layers on the hard mask 28 and to planarize to form the third metal wiring 37. At this time, the metal material is deposited in the same manner as the metal material deposition method for the second metal wiring performed in FIG. 1C.

As a result, the MIM capacitor 200 having a three-dimensional structure is manufactured using the trench 29a or the dual damascene pattern 29.

Subsequently, although not shown in the drawings, in the case where additional metal wiring formation is required on the third metal wiring 37, the respective insulating films are formed after the deposition of the metal diffusion barrier film, and the same method as the above-described metal wiring forming process The process proceeds to form additional metal wiring. In the subsequent process, the entire wiring of the MIM capacitor is formed by electrically connecting the upper electrode of the MIM capacitor region with a metal wiring process.

In the above process, the MIM capacitor and the metal wiring can be formed in the same layer, and the upper surface is flattened to facilitate the subsequent process. In addition, by forming a capacitor in the three-dimensional structure of the dual damascene structure, the capacitance can be improved.

As described above, the present invention is to form a dual damascene pattern in a conventional process, and then to manufacture a three-dimensional MIM capacitor in the dual damascene pattern, which can be implanted into the existing wiring forming process and easily without increasing the metal layer. It is possible to manufacture a MIM capacitor having a high capacitance, thereby improving the electrical characteristics and reliability of the device.

Claims (25)

A predetermined region of the interlayer insulating layer including the first insulating layer, the etch stop layer, the second insulating layer, and the hard mask is etched to form a dual damascene pattern formed of a trench or a trench and vias, and the dual damascene pattern of the capacitor formation region is tortuous. Providing a semiconductor substrate formed of a serpentine structure; Forming a first metal diffusion barrier layer on the semiconductor substrate; Depositing a metal material on the semiconductor substrate, and then removing the metal material and the first metal diffusion barrier layer on the interlayer insulating layer by chemical mechanical polishing to form a first metal wire on the trench or the dual damascene pattern. step; Forming a photoresist pattern in which a region where a capacitor is to be formed is exposed, removing the hard mask and the second insulating layer in an exposed region because the photoresist pattern is not formed, and then removing the photoresist pattern; Sequentially forming a lower electrode, a dielectric film, an upper electrode, and a second metal diffusion barrier on the whole including the first metal wire; Depositing a metal material on the whole to completely fill the remaining part of the space from which the second insulating film has been removed; Chemical mechanical polishing is performed to remove and planarize the metal material, the second metal diffusion barrier, the upper electrode, the dielectric layer, and the lower electrode on the second insulating film to form a second metal wiring and simultaneously form a capacitor. Metal wiring and capacitor manufacturing method of a semiconductor device, characterized in that consisting of a step. The method of claim 1, The etching prevention film or the hard mask is a metal wiring and capacitor manufacturing method of a semiconductor device, characterized in that formed by depositing a SiN or SiC film thickness of 100 ~ 1000Å by PECVD method. The method of claim 1, The first insulating film or the second insulating film may be formed using SiO ₂ , FSG, or a dielectric constant of 3.0 or less by using a PECVD method, an HDP-CVD method, an APCVD method, or a spin coating method that may be performed at a temperature of 450 ° C. or less. Forming a metal wiring and a capacitor manufacturing method of a semiconductor element. The method of claim 1, The total area of the trench or dual damascene pattern is formed in consideration of the target capacitance of the capacitor manufactured in the final process, characterized in that the metal wiring and capacitor manufacturing method of the semiconductor device. The method of claim 1, The first metal diffusion barrier or the second metal diffusion barrier is formed by depositing a combination of Ta, TaN, TiN, WN, TaC, WC, TiSiN, or at least one of them by PVD, CVD, or ALD. A method of manufacturing a metal wiring and a capacitor of a semiconductor device. The method of claim 1, And performing reactive cleaning using an argon sputter or plasma containing hydrogen such as H ₂ or NH ₃ in a high vacuum deposition apparatus before the first metal diffusion barrier is formed. Method of manufacturing metal wiring and capacitors in the device. The method of claim 1, The first metal wiring or the second metal wiring may be formed by using Cu as a metal material, forming a Cu seed layer by PVD or CVD, and then embedding the trench or the dual damascene pattern by Cu electroplating. After forming a Cu seed layer by Cu deposition using an electroplating method, the trench or the dual damascene pattern by embedding the trench or the dual damascene pattern by an electroless or electroplating method, or by mixing the embedding method Method of manufacturing a metal wiring and a capacitor of a semiconductor device, characterized in that the buried to form. The method of claim 1, And the hard mask is removed by a plasma dry etching process using a fluorine-containing gas. The method of claim 1, The second insulating film is removed using a solution containing HF when formed of SiO ₂ , FSG, SiOC, SiOH, SiOCH components, and by using 0 ₂ plasma when formed of a polymer-based low dielectric constant insulating film. A metal wiring and a capacitor manufacturing method of a semiconductor element. The method of claim 1, The lower electrode or the upper electrode is formed by depositing Pt, Ru, Ir, or W by CVD, PVD, or ALD method. The method of claim 1, Forming a glue layer such as TiN, TiAlN or TiSiN as an adhesive layer on the interlayer insulating film before forming the lower electrode. The method of claim 1, The dielectric film is formed by depositing a Ta oxide film, Ba-Sr-Ti oxide, Zr oxide, Hf oxide, Pb-Zn-Ti oxide, Sr-Bi-Ta oxide by CVD, PVD, or ALD. Method for manufacturing metal wiring and capacitors in semiconductor devices. A predetermined region of the interlayer insulating layer including the first insulating layer, the etch stop layer, the second insulating layer, and the hard mask is etched to form a dual damascene pattern formed of a trench or a trench and vias, and the dual damascene pattern of the capacitor formation region is tortuous. Providing a semiconductor substrate formed of a serpentine structure; Forming a first metal diffusion barrier layer on the semiconductor substrate; Depositing a metal material on the semiconductor substrate, and then removing the metal material and the first metal diffusion barrier layer on the interlayer insulating layer by chemical mechanical polishing to form a first metal wire on the trench or the dual damascene pattern. step; Removing the hard mask, the second insulating film, and the first metal wiring of the exposed region by forming a photoresist pattern that exposes a region where a capacitor is to be formed, and then removing the photoresist pattern; Sequentially forming a lower electrode, a dielectric layer, an upper electrode, and a second metal diffusion barrier on the whole including the first metal diffusion barrier; Depositing a metal material on the whole to completely fill the remaining part of the space from which the second insulating film has been removed; Chemical mechanical polishing is performed to remove and planarize the metal material, the second metal diffusion barrier, the upper electrode, the dielectric layer, and the lower electrode on the second insulating film to form a second metal wiring and simultaneously form a capacitor. Metal wiring and capacitor manufacturing method of a semiconductor device, characterized in that consisting of a step. The method of claim 13, The etching prevention film or the hard mask is a metal wiring and capacitor manufacturing method of a semiconductor device, characterized in that formed by depositing a SiN or SiC film thickness of 100 ~ 1000Å by PECVD method. The method of claim 13, The first insulating film or the second insulating film may be formed using SiO ₂ , FSG, or a dielectric constant of 3.0 or less by using a PECVD method, an HDP-CVD method, an APCVD method, or a spin coating method that may be performed at a temperature of 450 ° C. or less. Forming a metal wiring and a capacitor manufacturing method of a semiconductor element. The method of claim 13, The total area of the trench or dual damascene pattern is formed in consideration of the target capacitance of the capacitor manufactured in the final process, characterized in that the metal wiring and capacitor manufacturing method of the semiconductor device. The method of claim 13, The first metal diffusion barrier or the second metal diffusion barrier is formed by depositing a combination of Ta, TaN, TiN, WN, TaC, WC, TiSiN, or at least one of them by PVD, CVD, or ALD. A method of manufacturing a metal wiring and a capacitor of a semiconductor device. The method of claim 13, And performing reactive cleaning using an argon sputter or plasma containing hydrogen such as H ₂ or NH ₃ in a high vacuum deposition apparatus before the first metal diffusion barrier is formed. Method of manufacturing metal wiring and capacitors in the device. The method of claim 13, The first metal wiring or the second metal wiring may be formed by using Cu as a metal material, forming a Cu seed layer by PVD or CVD, and then embedding the trench or the dual damascene pattern by Cu electroplating. After forming a Cu seed layer by Cu deposition using an electroplating method, the trench or the dual damascene pattern by embedding the trench or the dual damascene pattern by an electroless or electroplating method, or by mixing the embedding method Method of manufacturing a metal wiring and a capacitor of a semiconductor device, characterized in that the buried to form. The method of claim 13, And the hard mask is removed by a plasma dry etching process using a fluorine-containing gas. The method of claim 13, The second insulating film is removed using a solution containing HF when formed of SiO ₂ , FSG, SiOC, SiOH, SiOCH components, and by using 0 ₂ plasma when formed of a polymer-based low dielectric constant insulating film. A metal wiring and a capacitor manufacturing method of a semiconductor element. The method of claim 13, The first metal wire or the metal material is removed using an acid solution such as HCI or H ₂ SO ₄ as an etchant. The method of claim 13, The lower electrode or the upper electrode is formed by depositing Pt, Ru, Ir, or W by CVD, PVD, or ALD method. The method of claim 13, Forming a glue layer such as TiN, TiAlN or TiSiN as an adhesive layer on the interlayer insulating film before forming the lower electrode. The method of claim 13, The dielectric film is formed by depositing a Ta oxide film, Ba-Sr-Ti oxide, Zr oxide, Hf oxide, Pb-Zn-Ti oxide, Sr-Bi-Ta oxide by CVD, PVD, or ALD. Method for manufacturing metal wiring and capacitors in semiconductor devices.