KR100682246B1 - A semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device that can prevent the defect of the capacitor by suppressing the generation of a step on the surface of the lower electrode of the capacitor. A lower electrode formed on the lower electrode such that the lower electrode of the capacitor is formed along the inner surface of the trench and the inner surface of the trench, and the trench is embedded to connect the lower electrode to the first upper wiring. And a first contact formed on the upper electrode such that a dielectric film formed on the lower electrode exposed over the insulating film, an upper electrode of a capacitor formed on the dielectric film, and the upper electrode are connected to a second upper wiring. A plug and a lower wiring formed on the lower wiring such that the lower wiring is connected to the first upper wiring 2 provides a semiconductor device including a contact plug.

MIM, capacitors, copper, voids, bottom electrode.

Description

A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

1 is a cross-sectional view showing a semiconductor device formed in accordance with a preferred embodiment of the present invention.

2 to 7 are process cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

110 semiconductor substrate 111, 122 insulating film

112: first metal layer 113: lower wiring

114: dielectric film 115: second metal layer

116: hard mask 117: photoresist pattern

118, 119: etching process 112a: lower electrode of the capacitor

115a: upper electrode of capacitor 120: MIM capacitor

121: diffusion barrier 123a, 123b: first and second contact plug

124a, 124b: first and second upper wirings

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a metal-insulator-metal (MIM) capacitor applying a damascene process and a method of manufacturing a semiconductor device including the same.

In recent years, as the degree of integration of semiconductor devices increases, both upper and lower electrodes use metal-insulator-metal (MIM) capacitors made of precious metals or heat-resistant metals.

Meanwhile, as semiconductor devices are integrated and technology advances, speed, resistance, or parasitic capacitance between metals becomes a problem, and a wiring process using copper (Cu) instead of aluminum (Al) is the next generation. It is attracting attention in the wiring process of an element. Therefore, the wiring process using copper was applied also in forming said MIM capacitor. However, in the case of the wiring process using copper, the etching property of copper is very poor, and a damascene process is applied instead of the conventional process method.

In general, a method of forming a MIM capacitor using a damascene process is as follows.

First, a dual damascene process is applied to form a lower electrode made of copper in the interlayer insulating film, and a nitride film-based dielectric film is deposited on the interlayer insulating film including the lower electrode. An upper electrode made of a material such as TaN or TiN is formed in a predetermined region on the dielectric film.

However, when the MIM capacitor is formed in this manner, voids are generated on the lower electrode made of copper due to stress generated during the deposition process of the dielectric film made of the nitride film. These voids cause a step on the surface of the lower electrode to act as a defect of the capacitor.

Accordingly, the present invention has been proposed to solve the above-mentioned problems of the prior art, and provides a semiconductor device and a method of manufacturing the same, which can prevent the defect of the capacitor by suppressing the occurrence of a step on the surface of the lower electrode of the capacitor. There is a purpose.

According to an aspect of the present invention, there is provided an insulating film formed with a trench on a substrate, a lower electrode of a capacitor formed along an inner surface step of the insulating film and the trench exposed to one side of the trench, A lower wiring formed on the lower electrode so that the trench is buried so as to connect the lower electrode with the first upper wiring, a dielectric film formed on the lower electrode exposed over the insulating film, and a capacitor formed on the dielectric film. An upper electrode of the first electrode, a first contact plug formed on the upper electrode to connect the upper electrode to the second upper wiring, and a second contact plug formed on the lower wiring so that the lower wiring is connected to the first upper wiring It provides a semiconductor device comprising a.

According to another aspect of the present invention, there is provided a method of forming a first insulating film having a trench on an upper surface of a substrate, and forming a lower electrode of a capacitor along a stepped top surface of the first insulating film including the trench. Forming a lower wiring on the lower electrode such that the trench is buried, forming an upper electrode of a dielectric film and a capacitor on the lower electrode including the lower wiring, the lower wiring and Etching the upper electrode, the dielectric film, and the lower electrode to expose the insulating film on one side of the trench, depositing a second insulating film over the entire structure, and each of the upper electrode and the lower wiring in the second insulating film. It provides a method for manufacturing a semiconductor device comprising the step of forming the first and second contact plugs that are electrically connected.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

Example

1 is a cross-sectional view illustrating a semiconductor device in accordance with a preferred embodiment of the present invention.

Referring to FIG. 1, a semiconductor device according to an exemplary embodiment of the present invention may include an insulating layer 111 and a trench formed on a semiconductor substrate 110 on which a predetermined semiconductor structure layer (not shown) is formed. A lower wiring 113 formed so that the trench is embedded to connect the lower electrode 112a of the capacitor formed on the insulating film 111 of the inner wall of the trench and one side of the trench and the lower electrode 112a with the first upper wiring 124a. And a dielectric film 114 formed on the lower electrode 112a to overlap the insulating film 111 on one side of the lower wiring 113, and an upper electrode 115a of the capacitor formed on the dielectric film 114. . The semiconductor structure layer may include a plurality of active elements such as transistors, passive elements such as resistors, capacitors, and inductors, and a plurality of memory cells, metal wirings, metal plugs, and the like.

The lower wiring 113 is a lower wiring, and a first contact plug 123a is formed on the lower wiring 113 to connect the lower electrode 112a and the first upper wiring 124a through the lower wiring 113. The second contact plug 123b for connecting the upper electrode 115a and the second upper wiring 124b is formed on the upper electrode 115a. Here, the first and second contact plugs 123a and 123b are formed together with the first and second upper wires 124a and 124b through the dual damascene process.

The dielectric layer 114 and the upper electrode 115a may overlap the lower wiring 113 and a portion of the region, and a hard mask 116 may be further formed on the upper electrode 115a. In addition, a diffusion barrier 121 may be formed along the stepped portion of the insulating layer 111 including the hard mask 116 and the lower interconnection 113 to prevent the diffusion of the material forming the lower interconnection 113.

Here, the lower wiring 113 is formed of copper, and the upper electrode 115a and the lower electrode 112a may be formed of any one of Ti, TiN, Ta, and TaN, or may be formed of a stacked structure of Ti / TiN or Ta / TaN. Can be. In addition, the dielectric film 114 is formed of SiN or SiC, and the hard mask 116 is formed of SiN or SiC.

That is, in the semiconductor device according to the preferred embodiment of the present invention, since the lower electrode 112a of the MIM capacitor 120 is formed on the oxide film-based insulating film 111, the lower wiring 113 made of copper when the dielectric film 114 is deposited. Even if voids are generated, the lower electrode 112a is not affected. Therefore, since no step is generated on the surface of the lower electrode 112a, defects of the MIM capacitor 120 may be prevented, thereby improving characteristics of the semiconductor device.

2 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 2 to 7 are the same components that perform the same function.

First, as shown in FIG. 2, an insulating film 111 (hereinafter, referred to as a first insulating film) is deposited on the substrate 110 on which a predetermined semiconductor structure layer (not shown) is formed. In this case, the first insulating layer 111 is formed of an oxide film-based material. For example, the first insulating layer 111 may be an HDP (High Density Plasma) oxide film, a BPSG (Boron Phosphorus Silicate Glass) film, a PSG (Phosphorus Silicate Glass) film, a PETEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film, a PECVD (Plasma Enhanced Chemical) A single layer film or a laminate thereof is formed by using any one of a vapor deposition (USG) film, a USG (Un-doped Silicate Glass) film, a FSG (Fluorinated Silicate Glass) film, a carbon doped oxide (CDO) film, and an organic Silicate Glass (OSG) film. It is formed of a laminated film.

Subsequently, a via hole (not shown) and / or a trench having a predetermined depth are formed in the first insulating layer 111 by applying a dual damascene process.

Subsequently, the lower electrode metal layer 112 (hereinafter, referred to as a first metal layer) of the capacitor is deposited on the first insulating layer 111 along the step formed by the trench. At this time, the first metal layer 112 is deposited using any one of Ti, TiN, Ta, and TaN or a stack structure of Ti / TiN or Ta / TaN to have a thickness of at least 600 GPa.

Subsequently, the lower wiring 113 is deposited on the first metal layer 112 to fill the trench. At this time, the lower wiring 113 is formed of copper.

Next, as shown in FIG. 3, the lower wiring 113 is polished by performing a planarization process, preferably a chemical mechanical polishing (CMP) process using the first metal layer 112 as a planarization stop film. As a result, the lower wiring 113 is flattened and the first metal layer 112 formed on the first insulating layer 111 on both sides of the lower wiring 113 is left as it is. The slurry used in the CMP process is not scratched on the first metal layer 112 exposed by using an abrasive free slurry that is planarized by a chemical reaction, without using general granular silica. ) Does not occur.

Subsequently, the dielectric layer 114 and the upper electrode metal layer 115 (hereinafter, referred to as a second metal layer) of the capacitor are sequentially deposited on the lower wiring 113 and the first metal layer 112. At this time, the dielectric film 114 is deposited SiN or SiC, the second metal layer 115 is deposited any one of Ti, TiN, Ta and TaN or a stacked structure of Ti / TiN or Ta / TaN.

Subsequently, as shown in FIG. 4, a hard mask 116 is deposited on the second metal layer 115. At this time, the hard mask 116 deposits SiN.

Subsequently, after the photoresist (not shown) is applied on the hard mask 116, a photolithography process is performed to form the photoresist pattern 117. In this case, the photoresist pattern 117 is formed to cover the hard mask 116 in the region overlapping the first insulating layer 111 on one side of the lower wiring 113.

Next, an etching process 118 using the photoresist pattern 117 as a mask is performed to etch the exposed hard mask 116.

Subsequently, as shown in FIG. 5, a strip process is performed to remove the photoresist pattern 117 (see FIG. 4).

Subsequently, an etching process 119 using the hard mask 116 as an etching mask is performed to sequentially expose the exposed second metal layer 115 (see FIG. 4) and the dielectric film 114 to sequentially etch the upper electrode 115a of the capacitor. To form. At this time, the second metal layer 115 is etched by applying a dry etching process, the dielectric film 114 is etched by applying a dry etching process using a chemical of CFx (x is a natural number) or CHFx (x is a natural number) series. do.

Subsequently, a sputtering etching process using argon (Ar) may be performed to remove the copper polymer generated due to the etching of the dielectric film 114.

Subsequently, an etching process is performed to target the first metal layer 112 (see FIG. 4) exposed on the first insulating layer 111 due to the etching of the dielectric layer 114. A portion of the first metal layer 112 and the lower wiring 113 are etched. As a result, the lower electrode 112a of the capacitor is formed, and the MIM capacitor 120 is completed. For example, the first metal layer 112 is etched using BClx or Cl gas, and then a H ⁺ plasma process is performed to remove CuO and copper polymer formed on the surface of the lower wiring 113 during the stripping process. . Here, the dielectric film 114 and the upper electrode 115a may be formed so that the lower wiring 113 and some regions overlap.

Subsequently, as shown in FIG. 6, the diffusion barrier layer is formed along the stepped upper portion of the first insulating layer 111 including the hard mask 116 and the lower interconnect 113 to prevent diffusion of the lower interconnect 113. (121) is deposited. At this time, the diffusion barrier 121 is deposited SiN or SiC.

Subsequently, an insulating film 122 (hereinafter referred to as a second insulating film) is deposited on the diffusion barrier film 121. In this case, the second insulating layer 122 deposits an oxide film-based material similar to the first insulating layer 111.

Subsequently, as shown in FIG. 7, the first and second contact plugs 123a and 123b connected to the upper electrode 115a and the lower wiring 113 in the second insulating film 122 by applying the dual damascene process. Are respectively formed, and first and second upper interconnections 124a and 124b are connected to each other.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the lower electrode of the capacitor is formed on the oxide-based insulating film during the manufacturing of the semiconductor device including the capacitor, so that even if voids occur in the lower wiring made of copper during the deposition of the dielectric film, the lower electrode Does not affect. Therefore, it is possible to prevent the defect of the capacitor by suppressing the surface step of the lower electrode, thereby improving the characteristics of the semiconductor device.

In addition, according to the present invention, defects in the lower interconnection made of copper may be minimized by using a hard mask in etching the upper electrode and the dielectric layer of the capacitor when manufacturing the semiconductor device including the capacitor.

Claims (11)

An insulating film formed on the substrate with a trench; A lower electrode of the capacitor formed along the step of the insulating layer and the inner surface of the trench exposed to one side of the trench; A lower interconnection formed on the lower electrode to fill the trench to connect the lower electrode to the first upper interconnection; A dielectric film formed on the lower electrode exposed over the insulating film; An upper electrode of a capacitor formed on the dielectric film; A first contact plug formed on the upper electrode such that the upper electrode is connected to a second upper wiring; And A second contact plug formed on the lower wiring such that the lower wiring is connected to the first upper wiring Semiconductor device comprising a. The method of claim 1, The lower wiring is a semiconductor device formed of copper. The method according to claim 1 or 2, The lower electrode and the upper electrode is a semiconductor device formed of a single layer structure of any one of Ta, TaN, Ti and TiN or a stacked structure of Ta / Ta or Ti / TiN. The method according to claim 1 or 2, The dielectric film is a semiconductor device formed of SiN or SiC. The method according to claim 1 or 2, And a portion of the dielectric film and the upper electrode overlap the lower wiring. Forming a first insulating film having a trench over the substrate; Forming a lower electrode of the capacitor along a step of an upper surface of the first insulating layer including the trench; Forming a lower wiring on the lower electrode to fill the trench; Forming an upper electrode of a dielectric film and a capacitor on the lower electrode including the lower wiring; Etching the upper electrode, the dielectric layer, and the lower electrode to expose the lower wiring and the insulating layer on one side of the trench; Depositing a second insulating film over the entire structure; And Forming first and second contact plugs electrically connected to the upper electrode and the lower wiring, respectively, in the second insulating layer; Method of manufacturing a semiconductor device comprising a. The method of claim 6, The lower wiring is formed of copper. The method according to claim 6 or 7, Etching the upper electrode, the dielectric film and the lower electrode, Method of manufacturing a semiconductor device made through a separate hard mask pattern. The method according to claim 6 or 7, The lower electrode and the upper electrode is formed of a single layer structure of any one of Ta, TaN, Ti and TiN, or a semiconductor device manufacturing method of forming a stacked structure of Ta / Ta or Ti / TiN. The method according to claim 6 or 7, The dielectric film is a method of manufacturing a semiconductor device formed of SiN or SiC. The method according to claim 6 or 7, Etching the upper electrode, the dielectric film and the lower electrode, And a portion of the upper electrode and the dielectric layer overlapping the lower wiring.

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