KR100955838B1 - Semiconductor device and method for forming metal line in the same - Google Patents

Abstract

The present invention relates to a wiring fabrication technique of a semiconductor device. To this end, the present invention provides a buffer film having an etch selectivity on an upper surface of an interlayer insulating film of a semiconductor substrate, and forms contact holes in the buffer film and the interlayer insulating film. The conductive film is gap-filled into the contact hole and the contact film is formed by planarizing the gap-filled conductive film by a chemical mechanical polishing (CMP) process.The conductive film is formed on the entire surface of the flattened buffer film and then patterned together to form a conductive film. By forming the wiring and the buffer film pattern, the portion of the buffer film in which the micro scratches are generated during the wiring patterning process is removed, thereby preventing the occurrence of bridges and short circuits between the wirings caused by the scratches.

Description

Semiconductor device and its wiring manufacturing method {SEMICONDUCTOR DEVICE AND METHOD FOR FORMING METAL LINE IN THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to micro scratches caused by a particle source during a chemical mechanical polishing (CMP) process for planarization of an interlayer insulating film of a semiconductor substrate. The present invention relates to a semiconductor device and a wiring manufacturing method thereof suitable for preventing the occurrence of the same.

As is well known, as semiconductor devices become more integrated, the size of the device and the pitch of the metal wiring are simultaneously reduced. This reduction in metal wiring pitch increases wiring resistance and increases the capacitance formed between adjacent wirings, making it difficult to obtain a desired operating speed from the device.

To this end, semiconductor devices have formed multi-layered wirings having two or more layers, and in this multi-layered wiring process, a planarization process of an interlayer insulating film, which serves as an electrical insulation, is essential for forming the upper metal wiring pattern on the lower metal wiring pattern. It became.

As such a planarization process, a chemical mechanical polishing (CMP) process having good planarization characteristics is widely used.

1A to 1D are process flow charts sequentially showing a process of planarizing an interlayer insulating film using a general chemical mechanical polishing process, and with reference thereto, a manufacturing process of the related art proceeds as follows.

As shown in FIG. 1A, a semiconductor device process is performed on a semiconductor substrate 10, for example, a shallow trench isolation (STI) process is performed on a semiconductor substrate 10 such as silicon to define an active region and an inactive region. The device isolation film 12 is formed, and a well (not shown) is formed by ion implanting an n-type dopant or a p-type dopant into the semiconductor substrate 10 having the device isolation film 12.

Next, the gate electrode 14 is formed on the upper surface of the semiconductor substrate 10 via a gate insulating film (not shown), and an n-type or p-type dopant is ion-implanted to close the edge of the gate electrode 14. Source / drain regions 18 are formed in the substrate. Here, before forming the source / drain regions 18, a spacer 16 made of an insulating material may be further formed on the sidewalls of the gate electrode 14.

The interlayer insulating film 20 may be formed by performing a process such as chemical vapor deposition (CVD) with a material such as PSG (Phosphosilitcate Glass), BSG (Borosilicate Glass), or BPSG (Borophosphosilicate Glass) on the entire structure of the semiconductor substrate 10 as described above. ) And planarize it on a chemical mechanical polishing (CMP) process.

In this case, as an example, as shown in FIG. 1B, the micro scratch 22 may occur on the surface of the interlayer insulating film 20 planarized by the particle source during the chemical mechanical polishing (CMP) process.

Next, a process such as spin coating is performed to apply a photoresist, and a photoresist pattern (not shown) defining a contact hole region is formed by performing an exposure and development process using a contact mask, The dry etching process using the photoresist pattern as an etching mask is performed to selectively remove a portion of the interlayer insulating layer 20 with the upper portion exposed to form a contact hole. Here, the contact hole opens the surface of the source / drain region 18 or the gate electrode 14.

Subsequently, a sequential deposition process or the like is performed to form Ti / TiN as a barrier metal film in the interlayer insulating film 20 in which contact holes are formed, and tungsten (W) is gapfilled as a metal film, and then the interlayer insulating film 20 The tungsten and barrier metal films are planarized by a chemical mechanical polishing (CMP) process until the surface is exposed, thereby forming a contact 24 in contact with the gate electrode 14 as shown in FIG. 1C as an example.

Thereafter, as illustrated in FIG. 1D, a metal film is deposited on the entire structure of the semiconductor substrate 10 having the planarized interlayer insulating film 20 and the contact 24 formed thereon, and patterned by a photo and etching process to contact the contact 24. The metal wiring 26 is formed to be vertically connected to the source / drain region 18 or the gate electrode 14 through the via.

In addition, the upper interlayer insulating film 28 is formed by depositing an HDP oxide film on the entire upper surface of the interlayer insulating film 20 on which the metal wiring 26 is formed by a process such as high density plasma (CVD) or the like. The wiring and contact manufacturing process is performed again.

The planarization of the interlayer insulating film using the chemical mechanical polishing (CMP) process according to the related art described above makes it possible to implement the multilayer wiring because the surface of the interlayer insulating film between the contacts and the wirings or the wirings is flattened.

However, the chemical mechanical polishing (CMP) process, which exhibits excellent characteristics in planarization of the interlayer insulating film, may cause micro scratches or the like on the surface of the interlayer insulating film by particles generated in the film quality of the object to be polished or particles present in the polishing pad. The scratch then leads to the generation of metal residues in the wire fabrication process, which results in a problem that the metal residues remaining in the microscratches act as a cause of metal bridges and shorts between the wires.

In order to overcome such a problem, researches and developments are being actively conducted everywhere to reduce scratches of interlayer insulating films in the wiring manufacturing process of semiconductor devices.

As an example of these techniques, Korean Patent Laid-Open Publication No. 2003-0080311 discloses chemical mechanical polishing of a surface of an interlayer insulating film of a semiconductor substrate, applying a flowable film over the interlayer insulating film, and etching the flowable film and the interlayer insulating film to a predetermined depth. To remove scratches generated in the interlayer insulating film.

As another example, in Korean Patent Laid-Open Publication No. 2007-0054932, the interlayer insulating film is planarized and the step between the cell region and the surrounding region generated during the formation of the interlayer insulating film is removed, and a polysilicon film is formed on the interlayer insulating film. After oxidation, a technique is disclosed in which the oxidized polysilicon film is etched away to remove micro scratches generated on the surface of the interlayer insulating film.

However, these conventional technologies have a problem that the entire manufacturing process increases because the wiring manufacturing process is performed after adding a separate film (eg, a flowable film or a polysilicon film) and etching again to remove the scratched portion. In the end, such a problem is acting as a factor in lowering the yield and increasing the price of the semiconductor device.

Moreover, in the prior art using a polysilicon film, there is a problem in that the entire manufacturing process is very complicated because a thermal oxidation process is added.

Accordingly, the present invention eliminates the microscratched buffer film portion by adding a buffer film over the interlayer insulating film and patterning the metal film and the buffer film together during the wiring process to be connected to the contact. Provided are a method for manufacturing a wiring of a semiconductor device which can prevent a bridge or short phenomenon between the two.

According to an aspect of the present invention, there is provided a semiconductor substrate including an isolation layer, a gate electrode, and a source / drain region, an interlayer insulating layer formed on the entire surface of the semiconductor substrate, and the gate electrode or source / drain through the interlayer insulating layer. A semiconductor device includes a contact connected to an area, a wiring connected to an upper surface of the contact, and a buffer film disposed between an upper portion of the interlayer insulating layer and a lower surface of the wiring.

According to another aspect of the present invention, there is provided a wiring manufacturing method of a semiconductor device, the method comprising: forming a buffer film on an upper surface of an interlayer insulating film of a semiconductor substrate, forming a contact hole by etching the buffer film and the interlayer insulating film, and Forming a contact by gap-filling a conductive film in a contact hole and chemically mechanically polishing the buffer film and the conductive film, forming a conductive film over the entire surface of the planarized buffer film, and patterning the conductive film and the buffer film to connect the wiring connected to the contact. It provides a wiring manufacturing method of a semiconductor device comprising the step of forming.

According to the present invention, a buffer film having an etch selectivity is added to an upper surface of an interlayer insulating film in a wire fabrication process, a contact hole is formed in the buffer film and an interlayer insulating film, a gap film is filled into the contact hole, and a gap is filled by a chemical mechanical polishing (CMP) process. Forming a contact by planarizing the conductive film, forming a conductive film on the entire surface of the planarized buffer film, and patterning the conductive film and the buffer film together to form a wiring and a buffer film pattern connected to the contact. Since the generated buffer film portion is removed, bridge generation and short phenomena between wirings caused by scratches can be prevented in advance, thereby increasing the manufacturing yield of the semiconductor device.

In addition, the present invention has the advantage that the manufacturing process is simplified compared to the prior art because it does not perform a separate etching process for removing the micro scratches generated by the chemical mechanical polishing process.

SUMMARY OF THE INVENTION The present invention provides a buffer film on an upper surface of an interlayer insulating film of a semiconductor substrate, forms a contact hole by etching the buffer film and the interlayer insulating film, gap-fills a conductive film in the contact hole, and performs a chemical mechanical polishing (CMP) process. By forming a gap-filled contact in the contact hole of the interlayer insulating film and the buffer film, and forming a conductive film over the entire surface of the planarized buffer film, patterning the conductive film and the buffer film to form wiring and buffer film patterns connected to the contact, According to the present invention, the conductive film and the buffer film may be patterned together in the wire fabrication process to completely remove the portion of the buffer film where the micro scratches are generated through the chemical mechanical polishing (CMP) process without a separate etching process.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2D are process flowcharts sequentially illustrating a wire manufacturing process of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to these drawings, the wiring manufacturing process of the semiconductor device according to the embodiment of the present invention proceeds as follows.

First, referring to FIG. 2A, a semiconductor device process is performed on a semiconductor substrate 100, for example, an STI process is performed on a semiconductor substrate 100 such as silicon to define an active region and an inactive region. In an embodiment, a well (not shown) is formed by ion implanting an n-type dopant or a p-type dopant into the semiconductor substrate 100 having the device isolation layer 102.

Next, a gate electrode 104 is formed on the upper surface of the semiconductor substrate 100 via a gate insulating film (not shown), and an n-type or p-type dopant is ion-implanted to close the edge of the gate electrode 104. Source / drain regions 108 are formed in the substrate. In this case, before forming the source / drain regions 108, a spacer 106 made of an insulating material may be additionally formed on the sidewalls of the gate electrode 104.

Subsequently, by performing a process such as chemical vapor deposition (CVD), the interlayer insulating film 110 made of a material such as PSG, BSG, BPSG, etc. on the entire surface of the structure of the semiconductor substrate 100 as described above to a thickness of about 6000 Deposit.

Then, an additional buffer film 112 is formed on the upper surface of the interlayer insulating film 110. The buffer film 112 is an insulating film having an etching selectivity with respect to the interlayer insulating film 110, for example, silicon nitride film (SiN) or the like. Can be used. The buffer layer 112 may be changed to another insulating material having high etching selectivity with respect to the interlayer insulating layer 110.

Next, a photoresist (not shown) is applied to the upper surface of the buffer film 112 to apply a photoresist (not shown), and a photoresist pattern defining a contact hole region is formed by performing an exposure and development process using a contact mask ( (Not shown).

Subsequently, a dry etching process is performed to select and remove a portion of the buffer layer 112 and the interlayer insulating layer 110 whose upper portion is exposed by the photoresist pattern, thereby forming a contact hole (not shown). Here, the dry etching process may use a reactive ion etching (RIE) process or an etching process using a plasma gas.

Therefore, the contact holes of the buffer layer 112 and the interlayer insulating layer 110 open the surface of the source / drain region 108 or the gate electrode 104 through the dry etching process. In this embodiment, the gate electrode 104 is opened. ) To open the surface.

Thereafter, a process such as ashing is performed to remove the remaining photoresist pattern.

Referring again to FIG. 2B, Ti / TiN is formed as a barrier metal film in the interlayer insulating film 110 and the buffer film 112 with contact holes, and tungsten (W) is gap-filled as a conductive film.

Subsequently, a chemical mechanical polishing (CMP) process is performed to planarize the tungsten and barrier metal films until the surface of the buffer film 112 is exposed, thereby forming a contact 116 where a barrier metal film and a conductive film such as tungsten are gap-filled in the contact hole. Form. In this case, the bottom surface of the contact 116 is vertically connected to the gate electrode 104 (or the source / drain region).

In the chemical mechanical polishing (CMP) process for forming the contact, microscratch 114 may occur on the surface of the buffer film 112 planarized by particles generated in the film to be polished or particles present in the polishing pad. This micro scratch is removed by a subsequent wiring patterning process.

By further performing the deposition process, the metal film 118 is deposited as a conductive film on the entire structure of the semiconductor substrate with the planarized buffer film 112 and the contact 116.

Here, the metal film 118 is deposited by a process such as physical vapor deposition (PVD). In this case, the metal film 118 may include aluminum (Al), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), tantalum (Ta), titanium nitride film (TiN), The tantalum nitride film TaN, the tungsten nitride film WN, or the like, or a composite thereof.

Referring to FIG. 2C, a photoresist pattern (not shown) is applied to the top surface of the metal film 118 by spin coating, and the exposure and development processes using a contact mask are performed to define the wiring region. (Not shown), and dry etching the metal film 118 and the buffer film 112 exposed by the above photoresist pattern to form the wiring 118a and at the same time the wiring 118a and the interlayer insulating film. The buffer film pattern 112a is formed between the layers 110.

Here, the dry etching of the metal film and the buffer film may be performed using a plasma etching process using a CF-based gas and O ₂ or Ar gas.

Here, the dry etching process detects excited molecules such as N ₂ * and NO * using a detection apparatus such as an optical Emissiom Spectroscopy (OES) to find an end point of the buffer film and stops etching.

Therefore, in the patterning process for forming the wiring 118a, the buffer film of the remaining portions except for the lower portion of the wiring is patterned and removed together, so that the scratched portion of the buffer film generated by the chemical mechanical polishing (CMP) process is also removed.

Then, the remaining photoresist pattern is removed by performing a process such as etching.

That is, in the semiconductor device manufactured according to the present exemplary embodiment, the interlayer insulating layer 110 is formed on the semiconductor substrate 100 on which the device isolation layer 102, the gate electrode 104, and the source / drain region 108 are formed. The contact 116 penetrating the interlayer insulating layer 110 connects the gate electrode 104 and the wiring 118a formed on the upper surface of the contact 116, and the upper portion of the interlayer insulating layer 110 and the wiring ( The buffer film pattern 112a is disposed between the lower surfaces of 118a.

In addition, a process such as HDP chemical vapor deposition (CVD) is performed on the entire upper surface of the interlayer insulating layer 110 on which the metal interconnection 118a and the buffer layer pattern 112a are formed, to deposit an HDP oxide layer, and chemical mechanical polishing (CMP). By performing a process or the like, as shown in FIG. 2D, the planarized upper interlayer insulating film 120 is formed.

Subsequently, although not shown in the drawings, a process of manufacturing a contact, a wiring, and the like on the planarized upper interlayer insulating layer 120 will be performed.

Accordingly, in the wiring manufacturing process of the semiconductor device according to the present invention, after forming a contact on the buffer film and the interlayer insulating film using a chemical mechanical polishing (CMP) process, and forming a conductive film on the entire surface of the planarized buffer film, the conductive film and By patterning the buffer films together to form wiring and buffer film patterns connected to the contacts, the micro-scratched buffer film can be completely removed through chemical mechanical polishing (CMP) process without any etching process in the wiring manufacturing process. This prevents the occurrence of bridges between the wirings due to scratches.

Meanwhile, in the embodiment of the present invention, the wiring manufacturing process is described as a contact connected to the gate electrode and the wiring thereof as an example.

In the above description has been described by presenting a preferred embodiment of the present invention, the present invention is not necessarily limited thereto, and those skilled in the art to which the present invention pertains should be within the scope not departing from the technical spirit of the present invention. It will be readily appreciated that various substitutions, modifications, and variations are possible.

1A to 1D are process flowcharts sequentially illustrating a process of planarizing an interlayer insulating film using a general chemical mechanical polishing process;

2A to 2D are process flowcharts sequentially illustrating a wire manufacturing process of a semiconductor device according to an exemplary embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

100 semiconductor substrate 102 device isolation film

104: gate electrode 106: spacer

108: source / drain region 110: interlayer insulating film

112: buffer film 114: micro scratch

116 contact 118a wiring

120: upper interlayer insulating film 112: buffer film

112a: buffer film pattern

Claims (4)

As a wiring manufacturing method of a semiconductor element, Forming a buffer film on an upper surface of the interlayer insulating film of the semiconductor substrate; Etching the buffer film and the interlayer insulating film to form a contact hole; Gap-filling a first conductive layer in the contact hole and chemically polishing the buffer layer and the first conductive layer to form a contact; Forming a second conductive layer on the entire surface of the planarized buffer layer, and patterning the second conductive layer and the buffer layer to form wirings connected to the contacts; Wiring manufacturing method of a semiconductor device comprising a. The method of claim 1, And the buffer film is an insulating film having an etching selectivity with respect to the interlayer insulating film.  The method of claim 2, The buffer film is a silicon nitride film (SiN), the wiring manufacturing method of a semiconductor device. The method according to any one of claims 1 to 3, The patterning of the second conductive layer and the buffer layer is performed through a reactive ion etching (RIE) process or a plasma gas etching process.

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