KR100791694B1 - Method for manufacturing metal line by using dual damascene - Google Patents

Abstract

A method for fabricating a metal line using a dual damascene process is provided to precisely guarantee a CD(critical dimension) of a miniaturized via hole of a high integrated semiconductor device by eliminating the necessity of a mask process of a photoresist pattern for defining a via hole region and by forming spacers on sidewalls of a trench to define the via hole region. At least one interlayer dielectric is formed in a structure of a semiconductor substrate(100) having a semiconductor device, and a mask pattern layer is stacked on the resultant structure. The mask pattern and the interlayer dielectric are partially etched to form a trench, and spacers are formed on the sidewalls of the trench. While the mask pattern layer is removed, the interlayer dielectric exposed the spacer is etched to form a via hole and the spacer is eliminated. Metal is gap-filled in the trench and the via hole, and the interlayer dielectric and the metal are planarized to form a via and a metal interconnection vertically connected to the structure of the semiconductor substrate. The mask pattern layer can be made of an insulation material with etch selectivity with respect to the interlayer dielectric. The spacer can be made of an insulation material with etch selectivity with respect to the interlayer dielectric.

Description

Method for manufacturing metal wiring using dual damascene {METHOD FOR MANUFACTURING METAL LINE BY USING DUAL DAMASCENE}

1A to 1E are process flowcharts for explaining a method for manufacturing metal wiring using dual damascene according to the prior art;

2 is a view showing a defect that occurs during the manufacturing process of the metal wiring using the dual damascene according to the prior art,

3A to 3F are process flow charts for explaining a method for manufacturing metal wiring using dual damascene according to the present invention.

<Description of the code | symbol about the principal part of drawing>

100 semiconductor substrate 102 device isolation film

104: gate insulating film 106: gate electrode

108, 130: spacer 110: source / drain region

112: first interlayer insulating film 114: contact electrode

116: second interlayer insulating film 118: lower wiring

120: etch stop film 122: third interlayer insulating film

124: fourth interlayer insulating film 126: mask pattern film

128: trench 132: via hole

134: Vias and Top Wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a metal wiring of a semiconductor device, and in particular, a via hole mask is omitted during a via hole etching process of dual damascene, and a gap fill process of the via hole is omitted to minimize the generation of etching residues of the via hole. The manufacturing method of the metal wiring using dual damascene which can improve the yield of wiring.

In connection with the reduction of current semiconductor devices, the current density increases due to the reduction in the cross-sectional area of the metal wiring, which causes a serious problem in the reliability of the metal wiring due to the electromagnetization (EM). Accordingly, copper (Cu), which has a lower resistivity than aluminum (Al) and has excellent reliability, is used as the material of the metal wiring.

However, since copper is difficult to form a highly volatile compound and has a difficulty in a dry etching process for forming a fine pattern, copper wiring is mainly manufactured by a damascene process. In the damascene process, the interlayer insulating film is first deposited and the interlayer insulating film is patterned through a photolithography process to form a trench, a wiring region, and gap-fill copper in the trench, and then chemical mechanical polishing (CMP). It is planarized by a process and a copper wiring is formed. In addition, the dual damascene process, which is mainly used in multi-layer metal wiring, forms trenches as wiring regions in the interlayer insulating film, via holes in which the lower structure is opened at the bottom of the trenches, and then gap-fills copper and once chemical mechanical polishing. Planarization is performed by a (CMP) process to simultaneously form vias and metal lines.

1A to 1E are process flowcharts illustrating a method for manufacturing a metal wiring using dual damascene according to the prior art. Hereinafter, the manufacturing process of the metal wiring using the dual damascene by the prior art is demonstrated with reference to these drawings.

First, as shown in Fig. 1A, a MOS transistor or the like is formed as a semiconductor substrate 10 on a silicon substrate. That is, the device isolation film 12 such as shallow trench isolation (STI) is formed on the semiconductor substrate 10, and the gate insulating film 14 and the gate electrode 16 are sequentially stacked on the substrate between the device isolation films 12. After forming the spacer insulating film 18 on the sidewall of the gate electrode 16, the source / drain regions 20 are formed in the substrate.

The BPSG is deposited as the first interlayer insulating film 22 by a chemical vapor deposition (CVD) process on the entire surface of the semiconductor substrate 10, and the first interlayer insulating film 22 is dry etched to form a contact hole. The contact electrode 24 is formed by gap-filling a metal such as tungsten (W) into the contact hole by a physical vapor deposition (PVD) process. As a second interlayer insulating film 26, a high density oxide film (HDP oxide) is deposited on the entire surface of the resultant, and the second interlayer insulating film 26 is etched to form a trench defining a wiring region. The lower gap 28 is formed by gap-filling copper (Cu) in the trench by electroplating or physical vapor deposition, and planarizing it in a chemical mechanical polishing (CMP) process.

Next, after thinly depositing a silicon nitride film (SiN), a silicon carbide film (SiC), or the like as an etch stop film 30 on the upper surface of the lower wiring 28 and the second interlayer insulating film 26, at least one thereon. The above-mentioned multiple interlayer insulating films 32 and 34 are formed. For example, a chemical vapor deposition (CVD) process deposits a Fluorine doped Silicate Glass (FSG) as a third interlayer insulating film 32 on the etch stop layer 30 and a high density oxide film as a fourth interlayer insulating film 34 thereon. (HDP oxide) is deposited.

Subsequently, as shown in FIG. 1B, a photoresist pattern (not shown) defining a via hole region is formed on the fourth interlayer insulating layer 34 by performing a photolithography process, and a dry etching process is performed to form a photoresist pattern. The fourth interlayer insulating film 34, the third interlayer insulating film 32, and the etch stop film 30 exposed by the etching process are etched to form a via hole 36 in which the surface of the lower wiring 28 is opened.

After removing the photoresist pattern by performing a wet etching or etching process, the via hole is completely gapfilled with a gapfill material 38 such as novolac, and the etching process is performed at a predetermined depth from the surface of the via hole, for example, 1000 mm or less. The gap fill film 38 is recessed to a depth of. Here, the gap fill layer 38 such as a novolac gap-filled in the via hole may prevent foreign matters or the like from occurring in the via hole during the photoresist manufacturing process for forming the trench.

Then, as shown in FIG. 1C, a photoresist pattern (not shown) defining a trench region is formed by performing a photolithography process on the upper surface of the fourth interlayer insulating layer 34, and a dry or wet etching process is performed. The fourth interlayer insulating film 34 exposed by the photoresist pattern is etched to form the trench 40 defining the upper wiring region. At this time, a portion of the upper and / or side surfaces of the gap fill layer 38 of the via hole is opened by the trench 40.

Subsequently, as shown in FIG. 1D, a wet etching or etching process is performed to remove the gapfill film gap-filled into the photoresist pattern and the via hole.

Then, as illustrated in FIG. 1E, copper is filled in the trenches and via holes by an electroplating or physical vapor deposition (PVD) process and flattened by a chemical mechanical polishing (CMP) process to be perpendicular to the lower wiring 28. Vias and top wirings 42 are formed to be connected.

However, as the via hole size also decreases with increasing integration of semiconductor devices, it is difficult to completely remove a gap fill film such as novolac that is gap-filled in the via hole. In addition, it is also difficult to form a narrow via hole photoresist pattern with an accurate critical dimension (CD) in the mask process for the via hole etching process, that is, the photoresist pattern manufacturing process.

Therefore, the manufacturing process of the dual damascene metal wiring according to the prior art cannot secure the desired via hole critical dimension when the photoresist pattern for the via hole is not formed accurately, and the novolac gap-filled in the via hole of the interlayer insulating film for the trench etching. When the gap fill layer, such as the adhesive layer, is not completely removed, as shown in FIG. 2A, etching by-products such as polymers remain in the via hole without being removed, thereby lowering electrical characteristics and yield of the metal wiring.

An object of the present invention is to solve the problems of the prior art as described above, by performing the via hole etching process using a spacer, it is possible to omit the mask process for via hole etching and the gap fill process of the via hole to reduce the yield of metal wiring The present invention provides a method for manufacturing a metal wiring using dual damascene that can be improved.

In order to achieve the above object, the present invention provides a method for manufacturing a dual damascene metal wiring of a semiconductor device, the at least one interlayer insulating film formed on the structure of the semiconductor substrate on which the semiconductor device is formed, and a mask pattern film is laminated thereon Forming a trench by etching the mask pattern and a portion of the interlayer insulating film, forming a spacer on the trench sidewalls, and etching the interlayer insulating film exposed by the spacer to form a via hole while removing the mask pattern film. Removing gaps and gap-filling metals in the trenches and via-holes and planarizing the interlayer insulating film and the metal to form vias and metal interconnects perpendicular to the structure of the substrate.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

3A to 3F are flowcharts illustrating a method of manufacturing metal wiring using dual damascene according to the present invention. Referring to these drawings, the manufacturing process of the metal wiring using dual damascene according to one embodiment of the present invention proceeds as follows.

First, as shown in FIG. 3A, a MOS transistor or the like is formed as a semiconductor substrate 100 on a silicon substrate. That is, the device isolation film 102 such as STI is formed on the semiconductor substrate 100, the gate insulating film 104 and the gate electrode 106 are sequentially stacked on the substrate between the device isolation films 102, and the gate electrode 106 is formed. After the spacer insulating film 108 is formed on the sidewalls, the source / drain regions 110 are formed in the substrate.

The BPSG is deposited as the first interlayer insulating film 112 by a chemical vapor deposition (CVD) process or the like on the entire structure of the semiconductor substrate 100, and the first interlayer insulating film 112 is dry etched to form contact holes, The contact electrode 114 is formed by gap-filling a metal such as tungsten (W) in the contact hole by a vapor deposition (PVD) process or the like. As a second interlayer insulating film 116, a high density oxide film (HDP oxide) is deposited on the entire surface of the resultant, and the second interlayer insulating film 116 is etched to form a trench defining a wiring region. The lower gap 118 is formed by gap-filling copper (Cu) in the trench by electroplating or physical vapor deposition, and planarizing it in a chemical mechanical polishing (CMP) process.

Subsequently, a thin film of silicon nitride (SiN), silicon carbide (SiC), or the like is deposited as the etch stop layer 120 on the upper surface of the lower wiring 118 and the second interlayer insulating film 116, and then chemical vapor deposition ( The FSG is deposited as the third interlayer insulating film 122 on the etch stop layer 120 by the CVD process, and the HDP oxide is deposited as the fourth interlayer insulating film 124 thereon.

Subsequently, a silicon nitride film SiN is formed on the upper surface of the fourth interlayer insulating film 124 as the mask pattern film 126. In this case, the mask pattern layer 126 is formed of a material having an etching selectivity with the fourth interlayer insulating layer 124.

3B, a photoresist pattern (not shown) defining a trench region is formed on the mask pattern layer 126 by performing a photolithography process, and a dry etching process is performed on the photoresist pattern. A portion of the mask pattern layer 126 and the fourth interlayer insulating layer 124 exposed by the etching is etched to form the upper wiring trench 128.

Next, as shown in FIG. 3C, a silicon nitride layer (SiN) is deposited on the entire surface of the resultant trench, as an insulating layer, and as a material having an etching selectivity with the third interlayer insulating layer 122. The silicon nitride film is etched by performing a dry etching process such as) to form a spacer 130 on the sidewalls of the trench. In this case, the gap between the spacers 130 defines the via hole critical dimension CD, and accordingly, the thickness of the spacer 130 and the spacer width of the insulating layer 130 may be adjusted by the person skilled in the art according to the via hole critical dimension CD. It is preferable.

Subsequently, as shown in FIG. 3D, a via hole is formed in which the surface of the lower wiring 118 is opened by etching the third interlayer insulating layer 122 and the etch stop layer 120 exposed by the spacer 130a. 132). In this case, reference numeral 130a represents an etched spacer. In the dry etching process, the etching pattern ratio of the mask pattern layer and the third interlayer insulating layer is adjusted to etch the mask pattern layer together when the via hole 132 is formed.

Next, as shown in FIG. 3E, a wet etching process using a phosphoric acid solution or the like is performed to remove the spacers remaining on the trench sidewalls.

Then, as illustrated in FIG. 3F, a metal such as copper is gap-filled in the via holes and trenches formed in the third interlayer insulating layer 122 and the fourth interlayer insulating layer 124 by an electroplating or physical vapor deposition (PVD) process. The gap-filled metal is planarized by a chemical mechanical polishing (CMP) process to form vias and upper interconnections 134 that are vertically connected to the lower interconnections 118. At this time, before gap-filling a metal such as copper, a barrier metal layer may be further formed by thinly forming a tantalum nitride layer (TaN), tantalum (Ta), and a titanium silicide nitride layer (TiSiN) in via holes and trenches. .

Therefore, in the method of manufacturing the metal wiring using the dual damascene of the present invention, the trench is formed in the interlayer insulating film and the spacer is formed on the trench sidewall without proceeding a separate photoresist pattern manufacturing process for via hole etching. By forming the via holes by etching the interlayer insulating film exposed by the interlayer insulating film, the mask process for etching the via holes and the gap fill process of the via holes can be omitted, thereby minimizing the generation of etching by-products remaining in the via holes.

As described above, the present invention omits a mask process such as a photoresist pattern defining a via hole region and forms a spacer on the trench sidewall to define the via hole region, thereby forming a highly integrated semiconductor by spacer spacing of the trench sidewall without a separate mask process. Accurate via hole critical dimension (CD) of the device can be secured.

In addition, in the present invention, since the via hole is formed by etching the interlayer insulating layer exposed by the spacers of the trench sidewalls, manufacturing defects due to etching by-products of the via holes generated when the via holes are gap-filled during the trench etching process are formed in advance. It can prevent, and can improve the electrical characteristic and manufacture yield of a metal wiring.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (6)

In the method of manufacturing the metal wiring for dual damascene of a semiconductor element, Forming at least one interlayer insulating film on the structure of the semiconductor substrate on which the semiconductor device is formed, and stacking a mask pattern film thereon; Etching a portion of the mask pattern and the interlayer insulating layer to form a trench, and forming a spacer on the trench sidewalls; Removing the mask pattern layer and forming a via hole by etching the interlayer insulating layer exposed by the spacer, and then removing the spacer; Gap-filling the trench and via-holes and planarizing the interlayer insulating layer and the metal to form vias and metal interconnections perpendicular to the structure of the substrate; Method for producing a metal wiring using a dual damascene comprising a. The method of claim 1, And the mask pattern layer is formed of an insulating material having an etch selectivity with the interlayer insulating layer. The method of claim 2, The mask pattern film is formed of a silicon nitride film, the method for producing a metal wiring using dual damascene. The method of claim 1, And the spacer is formed of an insulating material having an etching selectivity with the interlayer insulating film. The method of claim 4, wherein The spacer is formed of a silicon nitride film, the method for producing a metal wiring using dual damascene. The method according to claim 1 or 3, And a gap between the spacers formed in the sidewalls of the trench and a width thereof are adjusted according to the via hole critical dimension (CD).

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