JP5272221B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its production method capable of restraining dispersions of the wiring resistance and the via resistance by the entire wiring layer. <P>SOLUTION: The resistance of a contact part of a conductive layer (wiring layer IL2), in a first via hole VH with a deep via depth BDE and a wiring layer IL1, is set smaller than the resistance of a contact part of the conductive layer (wiring layer IL2) in a second via hole VH with a shallow via depth BDE and the wiring layer IL1. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

The present invention relates to semiconductor equipment.

  With the miniaturization and speeding up of LSI (Large Scale Integrated circuit), Cu (copper) having a low electrical resistance is used instead of aluminum which has been conventionally used as a wiring material for LSI. By using Cu as the wiring material of the LSI, the wiring can be miniaturized while keeping the electrical resistance low, and the operation speed of the LSI can be improved. However, Cu has a property of easily diffusing into the insulating film. If Cu diffuses into the insulating film, the reliability of the wiring is lowered. Cu has the property that the reaction rate with plasma ions is very slow. For this reason, sufficient productivity cannot be obtained if wiring is formed by etching. Therefore, in recent years, a damascene method has been adopted as a method for forming a Cu wiring that can solve these problems.

  A technique that employs such a damascene method is disclosed in, for example, Japanese Patent Application Laid-Open No. 2006-24905.

In recent years, miniaturization of elements has progressed, and wiring dimensions and via dimensions have also been reduced. In order to increase the speed of the device, a low resistance and low capacity film is increasingly required even in multilayer wiring. In addition, suppression of variations in resistance and capacitance has become increasingly important.
JP 2006-24905 A

  However, in an actual wafer process, the process of each process varies even within the same wafer. For example, the interlayer film thickness, barrier metal film thickness, wiring dimension, via diameter, etc. at the center and edge of the wafer surface Variation occurs. As a result, there is a problem that wiring resistance and via resistance vary. Furthermore, there is a problem that the circuit timing does not have a margin due to variations in wiring resistance and via resistance, or yield deterioration and reliability deterioration occur.

The present invention has been made in view of the above problems, its object is to provide a semiconductor equipment which can suppress variations in wiring resistance and via resistance as a whole wiring layer.

The semiconductor device of the present embodiment includes a lower conductive layer, first and second wiring layers, an interlayer insulating film, and first and second via conductive layers. Each of the first and second wiring layers is formed on the lower conductive layer. The interlayer insulating film is formed between the lower conductive layer and the first and second wiring layers, and has a first via hole and a lower conductive layer for electrically connecting the lower conductive layer and the first wiring layer. There is a second via hole for electrically connecting the layer and the second wiring layer. The first and second via the conductive layer is embedded each of the interior of the first and second via holes. The first wiring layer has a narrower line width than the second wiring layer. The resistance of the contact portion between the first in-via conductive layer and the lower conductive layer is smaller than the resistance of the contact portion between the second in-via conductive layer and the lower conductive layer.

According to the semiconductor device of this embodiment, the resistance of the contact portion between the first via the conductive layer and the lower conductive layer is smaller than the contact portion of the resistance between the second via the conductive layer and the lower conductive layer It has become. Thereby, the dispersion | variation in resistance value as the whole wiring layer can be suppressed. Therefore, a margin in circuit timing is increased, and yield deterioration and reliability deterioration can be suppressed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, a semiconductor element (not shown) such as a MOS (Metal Oxide Semiconductor) transistor is formed on the surface of a semiconductor substrate SUB made of, for example, silicon. A contact interlayer insulating film CI made of, for example, a USG (Un-doped Silicon Glass) film having a thickness of 400 nm is formed so as to cover the surfaces of these semiconductor elements.

  Although not shown, a contact hole is formed in the contact interlayer insulating film CI. This contact hole is for electrically connecting the upper wiring layer IL1 and the lower conductive region (for example, the source / drain region of a MOS transistor). In this contact hole, for example, a laminated film of TiN (titanium nitride) and Ti (titanium) is formed along the wall surface of the contact hole. For example, a plug layer made of W (tungsten) is embedded in the contact hole. ing.

  On the contact interlayer insulating film CI, an interlayer insulating film II1 is formed. This interlayer insulating film II1 is made of, for example, a 100 nm thick SiOC film (dielectric constant k: 2.8 or less). The surface of the interlayer insulating film II1 is planarized. In the interlayer insulating film II1, a wiring trench IT1 reaching the contact interlayer insulating film CI is formed. A wiring layer IL1 is formed in the wiring groove IT1. The wiring layer IL1 is formed of a barrier metal layer BM1 made of Ta (tantalum) having a thickness of 15 nm, for example, and a conductive layer CL1 made of Cu, for example. The barrier metal layer BM1 is formed along the wall surface of the wiring trench IT1, and the conductive layer CL1 is formed so as to be embedded in the wiring trench IT1.

  Over the interlayer insulating film II1, a liner insulating film LF made of, for example, a SiC film (dielectric constant k: 4.8 or less) having a thickness of 40 nm is formed so as to cover the wiring layer IL1. On this liner insulating film LF, an interlayer insulating film II2 made of, for example, a 200 nm thick SiOC film (dielectric constant k: 2.8 or less) is formed. The surface of this interlayer insulating film II2 is planarized.

  A wiring trench IT2 is formed on the surface of the interlayer insulating film II2. A via hole VH is formed in the interlayer insulating film II2 and the liner insulating film LF so as to reach the wiring layer IL1 from the bottom of the wiring trench IT2.

  A wiring layer IL2 is formed in the via hole VH and the wiring groove IT2. This wiring layer IL2 is formed of a barrier metal layer BM2 and a conductive layer CL2 made of Cu, for example. The barrier metal layer BM2 has a first barrier metal layer BM2a and a second barrier metal layer BM2b. The first barrier metal layer BM2a has a two-layer structure of, for example, a Ta layer having a thickness of 5 nm and a TaN layer having a thickness of 5 nm. Second barrier metal layer BM2b is formed of a Ta layer having a thickness of 5 nm, for example.

  A recess (digging portion) CO is formed on the surface of the wiring layer IL1 immediately below the via hole VH. In the recess CO, the second barrier metal layer BM2b is in contact with the wiring layer IL1.

  In the present embodiment, variation in the thickness of the interlayer insulating film II2 causes a first via hole VH having a deep via depth BDE and a second via hole VH having a shallow via depth BDE in the wafer surface. Is formed. Here, each of the first via hole VH having the deep via depth BDE and the shallow second via hole VH have the same diameter BDI. For this reason, the first via hole VH having a deep via depth BDE has a larger aspect ratio (depth / diameter) than the second via hole VH having a shallow via depth BDE.

  The digging amount CDE of the concave portion CO immediately below the first via hole VH having the deep via depth BDE is larger than the digging amount CDE of the concave portion CO immediately below the second via hole VH having the shallow via depth BDE. . Here, the digging amount means a distance from the upper surface of the wiring layer IL1 to the lowermost end portion of the concave portion CO.

  In addition, the thickness of the portion of the second barrier metal layer BM2b that is in contact with the wiring layer IL1 is thinner immediately below the first via hole VH having a deep via depth BDE than in the second via hole VH having a shallow via depth BDE. ing.

  As described above, since the digging amount of the concave portion CO immediately below the first via hole VH having the deep via depth BDE is large, the contact area between the wiring layer IL1 and the wiring layer IL2 is increased, and the resistance is lowered. Further, the resistance is lowered by the thin thickness of the second barrier metal layer BM2b at the bottom of the first via hole VH having the deep via depth BDE. For this reason, the resistance of the contact portion between the in-via conductive layer (wiring layer IL2) and the wiring layer IL1 in the first via hole VH having the deep via depth BDE is in the second via hole VH having the shallow via depth BDE. The resistance of the contact portion between the in-via conductive layer (wiring layer IL2) and the wiring layer IL1 is smaller.

  In the present embodiment, the widths IW of the wiring grooves IT2 have substantially the same dimensions, and the depths TD of the wiring grooves IT2 and the diameters BDI of the via holes VH have substantially the same dimensions.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
2 to 10 are schematic cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. Referring to FIG. 2, a trench isolation structure (not shown) made of, for example, STI (Shallow Trench Isolation) is formed on a semiconductor substrate SUB made of, for example, silicon. A semiconductor element (not shown) made of, for example, a MOS transistor is formed on the surface of the semiconductor substrate SUB electrically isolated by the trench isolation structure.

  Next, a contact interlayer insulating film CI is formed so as to cover the surface of the semiconductor substrate SUB. The contact interlayer insulating film CI is formed, for example, by depositing a USG film with a thickness of 500 nm and then polishing and removing the thickness of 100 nm by a CMP (Chemical Mechanical Polishing) method.

  A contact hole (not shown) having a diameter of, for example, 70 nm is formed in the contact interlayer insulating film CI by using a normal photolithography technique and a dry etching technique. A barrier metal layer (not shown) is formed on the contact interlayer insulating film CI along the wall surface of the contact hole. This barrier metal layer is formed by a laminated structure of, for example, 20 nm thick TiN and 20 nm thick Ti. Next, a W layer having a thickness of, for example, 200 nm is formed on the barrier metal layer so as to fill the contact hole.

  Thereafter, CMP is performed on the W layer and the barrier metal layer until the surface of the contact interlayer insulating film is exposed. As a result, the W plug layer made of the W layer and the barrier metal layer remain in the contact hole.

  On the contact interlayer insulating film CI, an interlayer insulating film II1 made of, for example, a 150 nm thick SiOC film is formed. A photoresist PR1 is applied on the interlayer insulating film II1 and patterned by a normal photolithography technique. The interlayer insulating film II1 is subjected to anisotropic etching using the patterned photoresist PR1 as a mask. As a result, a wiring trench IT1 reaching the contact interlayer insulating film CI is formed in the interlayer insulating film II1. Thereafter, photoresist PR1 is removed by, for example, ashing.

  Referring to FIG. 3, barrier metal layer BM1 is formed on interlayer insulating film II1 along the wall surface of wiring trench IT1. This barrier metal layer BM1 is formed of Ta having a thickness of 15 nm, for example. A Cu seed layer having a thickness of 50 nm is formed on interlayer insulating film II1 and barrier metal layer BM1 by, for example, sputtering. Thereafter, a Cu layer CL1 is formed on the barrier metal layer BM1 so as to fill the wiring trench IT1 by plating.

  Thereafter, CMP is performed on the Cu layer CL1 and the barrier metal layer BM1 until the surface of the interlayer insulating film II1 is exposed. Thereby, the conductive layer CL1 made of the Cu layer and the barrier metal layer BM1 remain in the wiring trench IT1, and the wiring layer IL1 made of the conductive layer CL1 and the barrier metal layer BM1 is formed.

  Referring to FIG. 4, a liner insulating film LF made of, for example, a 40 nm-thick SiC film is formed on interlayer insulating film II1 so as to cover wiring layer IL1 by a CVD (Chemical Vapor Deposition) method. On this liner insulating film LF, for example, an interlayer insulating film II2 made of SiOC having a thickness of 250 nm is formed by a CVD method.

  A resist pattern PR2 is formed on the interlayer insulating film II2 by a normal photolithography technique. Using this resist pattern PR2 as a mask, dry etching is performed on interlayer insulating film II2. As a result, a via hole VH is formed in the interlayer insulating film II2, and the liner insulating film LF is exposed at the bottom of the via hole.

  At this time, when the thickness of the interlayer insulating film II2 varies, the depth of the via hole VH also varies, and the first via hole VH having a deep depth and the second via hole VH having a small depth Is formed.

Thereafter, resist pattern PR2 is removed by, for example, ashing.
Referring to FIG. 5, a resist plug PR3 is formed so as to fill the inside of each of first and second via holes VH.

  Referring to FIG. 6, resist pattern PR4 is formed on interlayer insulating film II2 using a normal photolithography technique. Using this resist pattern PR4 as a mask, dry etching is performed on interlayer insulating film II2. As a result, a wiring trench IT2 communicating with each of the first and second via holes VH is formed in the interlayer insulating film II2. Thereafter, resist patterns PR3 and PR4 are removed by, for example, ashing.

  Referring to FIG. 7, liner insulating film LF exposed from each of first and second via holes VH is removed by dry etching. As a result, a part of the surface of the wiring layer IL1 is exposed at the bottom of each of the first and second via holes VH.

  Referring to FIG. 8, first barrier metal layer BM2a is formed so as to cover the exposed surface of the wiring layer and along the wall surface of via hole VH and wiring groove IT. The first barrier metal layer BM2a is formed by a laminated structure of a Ta film having a thickness of 5 nm and a TaN film having a thickness of 5 nm, for example.

  Referring to FIG. 9, a resputtering process is performed by punch-through processing. As a result, the first barrier metal layer BM2a at the bottom of the via hole VH is removed to expose the surface of the wiring layer IL1, and the exposed surface of the wiring layer IL1 is dug to form a recess CO.

  This resputtering process is performed using a sputtering apparatus shown in FIG. In the chamber CMB of this sputtering apparatus, film formation of Ta and TaN and a resputtering process are performed. Control parameters for the resputtering process include substrate AC bias (AC Bias), coil DC power (DC Coil), target DC power (Target DC), and high frequency power (RF Coil) applied to the coil. There are four types. By controlling these parameters, the etching amount at the bottom of the via hole VH can be adjusted. These parameters are dependent on the diameter of the via hole VH, the aspect ratio (depth / diameter), and the like.

  The sputtering conditions in the present embodiment are, for example, a target DC power of 500 W, a substrate AC bias of 300 W, a high frequency power applied to the coil of 1200 W, and a DC power of the coil of 0 W.

  By performing resputtering under the above conditions, the amount of digging of the concave portion CO immediately below the first via hole VH having a deep depth increases, and the amount of digging of the concave portion CO immediately below the second via hole VH having a shallow depth. Becomes smaller.

  Referring to FIG. 10, second barrier metal layer BM2b is formed by, for example, sputtering so as to cover the surface of wiring layer IL1 exposed in recess CO and along the wall surface of via hole VH and wiring groove IT2. . This barrier metal layer BM2b is formed of a flash Ta film having a thickness of 5 nm, for example.

  This sputtering method is a film forming method in which step coverage is not conformal. For this reason, the thickness of the barrier metal layer BM2b at the bottom of the first via hole VH having a deep via depth BDE is thinner than the thickness of the barrier metal layer BM2b at the bottom of the second via hole VH having a shallow via depth BDE.

  Referring to FIG. 1, a Cu seed layer having a thickness of 50 nm is formed on barrier metal layer BM2 by, eg, sputtering. Thereafter, a Cu layer CL2 is formed on the barrier metal layer BM2 so as to fill the wiring trench IT2 by plating.

  Thereafter, CMP is performed on the Cu layer CL2 and the barrier metal layer BM2 until the surface of the interlayer insulating film II2 is exposed. As a result, the conductive layer CL2 made of the Cu layer and the barrier metal layer BM2 remain in the wiring trench IT2, and the wiring layer IL2 made of the conductive layer CL2 and the barrier metal layer BM2 is formed in the wiring trench IT2. . Thus, the semiconductor device of the present embodiment shown in FIG. 1 is manufactured.

Next, the effect of this Embodiment is demonstrated.
For example, due to variations in the thickness of the interlayer insulating film II2, the depth BDE of some via holes VH may increase from the designed value of 120 nm to 180 nm. In this case, if the diameter BDI of the bottom of the via hole VH is 60 nm, the aspect ratio of the via hole VH increases from 2.0 to 3.0. In the conductive layer of the via hole VH having a high aspect ratio (deep via depth), the resistance is larger than that of the conductive layer in the via hole VH having a low aspect ratio (shallow via depth), so there are via holes having different aspect ratios. As a result, the resistance varies.

  On the other hand, according to the present embodiment, as shown in FIG. 1, the digging amount CDE of the concave portion CO immediately below the first via hole VH having a deep via depth BDE is a second depth having a shallow via depth BDE. This is larger than the digging amount CDE of the concave portion CO immediately below the via hole VH. As a result, the resistance of the contact portion between the in-via conductive layer (wiring layer IL2) and the wiring layer IL1 in the first via hole VH having the deep via depth BDE is reduced due to the increase in the contact area. This is smaller than the resistance of the contact portion between the in-via conductive layer (wiring layer IL2) and the wiring layer IL1 in the second via hole VH.

  Further, the thickness of the barrier metal layer BM2b at the bottom of the first via hole VH having a deep via depth BDE is thinner than the thickness of the barrier metal layer BM2b at the bottom of the second via hole VH having a shallow via depth BDE. Also from this, the resistance of the contact portion between the in-via conductive layer (wiring layer IL2) and the wiring layer IL1 in the first via hole VH having the deep via depth BDE is the second via hole VH having the shallow via depth BDE. It is smaller than the resistance of the contact portion between the conductive layer in the via (wiring layer IL2) and the wiring layer IL1.

  As described above, in the first via hole VH, the resistance of the conductive layer in the via hole VH is higher than that in the second via hole VH, but the resistance of the contact portion between the wiring layer IL2 and the wiring layer IL1 is reduced. be able to. For this reason, the resistance value when viewed in the entire wiring layer connected by the first via hole VH can be brought close to the resistance value when viewed by the entire wiring layer connected by the second via hole VH. Thereby, the dispersion | variation as the whole wiring layer can be suppressed. Therefore, a margin in circuit timing is increased, and yield deterioration and reliability deterioration can be suppressed.

  Further, in the resputtering process shown in FIG. 9, by using the above-described conditions, the digging amount CDE of the deep via hole VH having the via depth BDE and the digging amount of the via hole VH having the shallow via depth BDE are self-aligned. It can be larger than CDE. For this reason, process variation can be reduced.

(Embodiment 2)
FIG. 12 is a cross sectional view schematically showing a configuration of the semiconductor device in the second embodiment of the present invention. Referring to FIG. 12, the configuration of the present embodiment differs from the configuration of the first embodiment in the thickness of interlayer insulating film II2 and the depth of the wiring trench.

  In the present embodiment, the thickness of the interlayer insulating film II2 does not vary or is extremely small. However, variation occurs in the depth TD of the wiring trench IT2. As a result, a wiring trench IT2 having a deep depth TD and a shallow wiring trench IT2 exist. The depth BDE of the first via hole VH connected to the wiring trench IT2 having a shallow depth TD is deeper than the depth BDE of the second via hole VH connected to the wiring trench IT2 having a deep depth TD. .

  The digging amount CDE of the recess CO in the wiring layer IL1 immediately below the first via hole VH having a deep via depth BDE is the digging of the recess CO in the wiring layer IL1 immediately below the second via hole VH having a shallow via depth BDE. It is larger than the quantity CDE. The thickness of the portion of the second barrier metal layer BM2b that is in contact with the wiring layer IL1 is lower in the first via hole VH having a deep via depth BDE than in the bottom portion of the second via hole VH having a shallow via depth BDE. Is thinning.

  As described above, the resistance of the contact portion between the conductive layer in the via (wiring layer IL2) in the first via hole VH having the deep via depth BDE and the wiring layer IL1 is in the second via hole VH having the shallow via depth BDE. The resistance of the contact portion between the in-via conductive layer (wiring layer IL2) and the wiring layer IL1 is smaller.

  In addition, since the structure of this Embodiment other than this and its manufacturing method are substantially the same as the structure and manufacturing method of Embodiment 1 mentioned above, the same code | symbol is attached | subjected about the same element and the description is repeated. Absent.

Next, the effect of this Embodiment is demonstrated.
For example, due to variations in the depth TD of the wiring trench IT2, the depth TD of the wiring trench IT2 becomes shallow from the designed value of 120 nm to 90 nm, and the depth BDE of a part of the via holes VH is accordingly reduced from the designed value of 120 nm to 150 nm. May be thicker. In this case, if the diameter BDI of the bottom of the via hole VH is 60 nm, the aspect ratio of the via hole VH increases from 2.0 to 2.5. In this case, the conductive layer in the via hole VH having a high aspect ratio (deep via depth) has a larger resistance and the resistance varies than the conductive layer in the via hole VH having a low aspect ratio (shallow via depth). Arise.

  On the other hand, in the present embodiment, the resistance of the contact portion between the conductive layer in the first via hole VH having the deep via depth BDE and the wiring layer IL1 has the resistance in the second via hole VH having the shallow via depth BDE. It is smaller than the resistance of the contact portion between the conductive layer and the wiring layer IL1. For this reason, as in the first embodiment, it is possible to suppress variations in resistance values when viewed in the entire wiring layer, increase a margin in circuit timing, and suppress deterioration in yield and reliability. .

(Embodiment 3)
FIG. 13 is a cross sectional view schematically showing a configuration of the semiconductor device in the third embodiment of the present invention. Referring to FIG. 13, the configuration of the present embodiment differs from the configuration of the first embodiment in the thickness of interlayer insulating film II2 and the diameter of the via hole.

  In the present embodiment, the thickness of the interlayer insulating film II2 does not vary or is extremely small. The depths of the plurality of wiring trenches IT2 are substantially the same, and the depths of the plurality of via holes VH are also substantially the same. However, the diameter BDI of the via hole VH varies. As a result, a first via hole VH having a small diameter BDI and a second via hole VH having a large diameter BDI exist.

  The amount CDE of the recess CO in the wiring layer IL1 immediately below the first via hole VH having a small diameter BDI is larger than the amount CDE of the recess CO in the wiring layer IL1 immediately below the second via hole VH having a large diameter BDI. It is getting bigger. The thickness of the portion of the second barrier metal layer BM2b that contacts the wiring layer IL1 is thinner at the bottom of the first via hole VH having a smaller diameter BDI than at the bottom of the second via hole VH having a larger diameter BDI. .

  As described above, the resistance of the contact portion between the conductive layer (wiring layer IL2) in the first via hole VH having a small diameter BDI and the wiring layer IL1 is reduced in the conductive layer (wiring layer IL2 in the second via hole VH having a large diameter BDI). ) And the wiring layer IL1 is smaller than the resistance of the contact portion.

  In addition, since the structure of this Embodiment other than this and its manufacturing method are substantially the same as the structure and manufacturing method of Embodiment 1 mentioned above, the same code | symbol is attached | subjected about the same element and the description is repeated. Absent.

Next, the effect of this Embodiment is demonstrated.
For example, due to variations in the diameter BDI of the via hole VH, the diameter BDI of the via hole VH may be reduced from the designed value of 60 nm to 45 nm. In this case, if the depth BDE of the via hole VH is 120 nm, the aspect ratio of the via hole VH increases from 2.0 to 2.67. In this case, the conductive layer of the via hole VH having a high aspect ratio (small diameter) has a larger resistance than the conductive layer in the via hole VH having a low aspect ratio (large diameter), and the resistance varies.

  On the other hand, in the present embodiment, the resistance of the contact portion between the conductive layer in the first via hole VH having a small diameter BDI and the wiring layer IL1 is equal to the conductive layer and the wiring in the second via hole VH having a large diameter BDI. It is smaller than the resistance of the contact portion with the layer IL1. For this reason, as in the first embodiment, it is possible to suppress variations in resistance values when viewed in the entire wiring layer, and a margin in circuit timing is increased.

  On the contrary, the diameter BDI of the via hole VH may increase from the designed value of 60 nm to 80 nm due to, for example, variations in the diameter BDI of the via hole VH. In this case, if the depth BDE of the via hole VH is 120 nm, the aspect ratio of the via hole VH is lowered from 2.0 to 1.5. In this case, the conductive layer in the via hole VH having a low aspect ratio (large diameter) has a smaller resistance than the conductive layer in the via hole VH having a high aspect ratio (small diameter), and the resistance varies.

  However, in the present embodiment, the resistance of the contact portion between the conductive layer in the via hole VH with a large diameter BDI and the wiring layer IL1 is the resistance of the contact portion between the conductive layer in the via hole VH with a small diameter BDI and the wiring layer IL1. Is bigger than. For this reason, as in the first embodiment, it is possible to suppress variations in resistance values when viewed in the entire wiring layer, increase a margin in circuit timing, and suppress deterioration in yield and reliability. .

  Accordingly, for example, a standard cell such as an SRAM (Static Random Access Memory) cell is used, and for example, the via diameter is increased in a specific via in which a sufficient margin for photolithography is not obtained and a problem such as a defective opening is concerned. Thus, yield deterioration can be suppressed. Further, when stacked, the same effect can be obtained even in a specific via in which a sufficient margin of photolithography cannot be obtained at the base step and there is a concern about problems such as an opening defect.

(Embodiment 4)
FIG. 14 is a plan view (A) and a cross-sectional view (B) schematically showing the configuration of the semiconductor device according to the fourth embodiment of the present invention. Referring to FIGS. 14A and 14B, the configuration of the present embodiment is different from that of the first embodiment in the thickness of interlayer insulating film II2 and width IW (wiring layer) of wiring trench IT2. Line width).

  In the present embodiment, the thickness of the interlayer insulating film II2 does not vary or is extremely small. However, there are wiring trenches IT2 (wiring layers having different line widths) having different widths IW. That is, the wiring groove IT2 having a small width IW and the wiring groove IT2 having a large width IW exist.

  The digging amount CDE of the concave portion CO of the wiring layer IL1 immediately below the first via hole VH connected to the wiring groove IT2 having a small width IW is directly below the second via hole VH connected to the wiring groove IT2 having a large width IW. Is larger than the amount CDE of the recess CO in the wiring layer IL1. The thickness of the portion of the second barrier metal layer BM2b that is in contact with the wiring layer IL1 is lower at the bottom of the first via hole VH having a deep via depth BDE than at the bottom of the second via hole VH having a shallow via depth BDE. It is getting thinner.

  As described above, the resistance of the contact portion between the conductive layer in the via (wiring layer IL2) and the wiring layer IL1 in the first via hole VH connected to the wiring groove IT2 having the small width IW is reduced in the wiring groove IT2 having the large width IW. It is smaller than the resistance of the contact portion between the in-via conductive layer (wiring layer IL2) and the wiring layer IL1 in the second via hole VH to be connected.

  In addition, since the structure of this Embodiment other than this and its manufacturing method are substantially the same as the structure and manufacturing method of Embodiment 1 mentioned above, the same code | symbol is attached | subjected about the same element and the description is repeated. Absent.

Next, the effect of this Embodiment is demonstrated.
For example, in the configuration shown on the left side of FIG. 14, the diameter BDI of the via hole VH is 60 nm, the depth BDE of the via hole is 120 nm, the depth TD of the wiring trench IT2 is 120 nm, and the minimum dimensions described in the DM (design manual) The line width IW (width of the wiring trench IT2) of the wiring layer IL2 may be laid out. In this case, since the line width IW of the wiring layer IL2 with respect to the diameter BDI of the via hole VH is small, the aspect ratio of the via hole VH appears to be effectively high. In other words, the aspect ratio of the via hole VH is originally 120 nm / 60 nm = 2.0, but it is considered that the depth of the via hole is increased by the depth TD of the wiring trench IT2, and (120 nm + 120 nm) / 60 nm. = 4.0 looks high. In this case, the conductive layer of the via hole VH having an effectively high aspect ratio has a larger resistance than the conductive layer in the via hole VH having a low aspect ratio, and the resistance varies.

  On the other hand, in the present embodiment, the resistance of the contact portion between the conductive layer in the first via hole VH connected to the wiring groove IT2 having the small width IW and the wiring layer IL1 is reduced to the wiring groove IT2 having the large width IW. The resistance is smaller than the resistance of the contact portion between the conductive layer in the second via hole VH to be connected and the wiring layer IL1. For this reason, as in the first embodiment, it is possible to suppress variations in resistance values when viewed in the entire wiring layer, increase a margin in circuit timing, and suppress deterioration in yield and reliability. .

(Embodiment 5)
In the present embodiment, a configuration in which a wiring layer is connected to each of the lower electrode and the upper electrode of the MIM capacitor will be described.

  FIG. 15 is a cross sectional view schematically showing a configuration of the semiconductor device in the fifth embodiment of the present invention. Referring to FIG. 15, contact interlayer insulating film CI is formed on the surface of semiconductor substrate SUB. An interlayer insulating film II1 is formed on the contact interlayer insulating film CI.

  A groove is formed in the interlayer insulating film II1, and a lower electrode SN of an MIM (Metal Insulator Metal) capacitor is formed in the groove. The lower electrode SN has a barrier metal layer BM3 formed along the side wall of the groove and a conductive layer CL3 filling the groove. Barrier metal layer BM3 is made of Ta, for example, and conductive layer CL3 is made of Cu, for example.

  An upper electrode CP of the MIM capacitor is formed on the lower electrode SN via a capacitor dielectric film CD. The capacitor dielectric film CD is made of, for example, SiN (silicon nitride), and the upper electrode CP is made of, for example, TiN. The side wall of the upper electrode CP is covered with the side wall insulating film SW.

  An insulating film IN and an interlayer insulating film II2 are formed so as to cover the MIM capacitor.

  A plurality of wiring trenches IT2 are formed on the surface of the interlayer insulating film II2. In the plurality of wiring trenches IT2, a wiring trench IT2 for routing the wiring layer IL2 electrically connected to the lower electrode SN of the MIM capacitor and a wiring layer IL2 electrically connected to the upper electrode CP are routed. Wiring trench IT2.

  The depth BDE of the first via hole VH for electrically connecting the wiring layer IL2 to the lower electrode SN is the depth BDE of the second via hole VH for electrically connecting the wiring layer IL2 to the upper electrode CP. It is deeper than. The amount CDE of the recess CO in the lower electrode SN immediately below the first via hole VH reaching the lower electrode SN is the amount CDE of the recess CO in the upper electrode CP immediately below the second via hole VH reaching the upper electrode CP. Is bigger than.

  The thickness of the portion of the second barrier metal layer BM2b that is in contact with the wiring layer IL1 is lower at the bottom of the first via hole VH having a deep via depth BDE than at the bottom of the second via hole VH having a shallow via depth BDE. It is getting thinner.

  As described above, the resistance of the contact portion between the conductive layer (wiring layer IL2) in the first via hole VH reaching the lower electrode SN and the lower electrode SN is reduced to the conductive layer (wiring in the second via hole VH reaching the upper electrode CP. The resistance of the contact portion between the layer IL2) and the upper electrode CP is smaller.

  In the present embodiment, each of the width IW and the depth TD of the wiring trench IT2 in which the wiring layer IL2 electrically connected to the lower electrode SN is formed is a wiring electrically connected to the upper electrode CP. The dimensions are substantially the same as the width IW and the depth TD of the wiring trench IT2 in which the layer IL2 is formed. The diameter of the conductive layer (wiring layer IL2) in the first via hole VH reaching the lower electrode SN and the diameter of the conductive layer (wiring layer IL2) in the second via hole VH reaching the upper electrode CP are substantially the same. Dimensions.

Next, the effect of this Embodiment is demonstrated.
When the MIM capacitor is formed, the depth BDE of the via hole VH reaching the lower electrode SN is deeper than the depth BDE of the via hole VH reaching the upper electrode CP. Therefore, when both via holes VH have the same diameter, the aspect ratio of the via hole VH reaching the lower electrode SN is larger than the aspect ratio of the via hole VH reaching the upper electrode CP.

  For example, when the diameter BDI of the via hole VH is 60 nm, the aspect of the via hole VH reaching the upper electrode CP when the depth BDE of the via hole VH reaching the upper electrode CP is 120 nm and the depth BDE of the via hole VH reaching the lower electrode SN is 270 nm. While the ratio is 2.0, the aspect ratio of the via hole VH reaching the lower electrode SN is as high as 4.5.

  On the other hand, in the present embodiment, the resistance of the contact portion between the conductive layer in the via in the first via hole VH reaching the lower electrode SN and the lower electrode SN becomes smaller in the second via hole VH reaching the upper electrode CP. It is smaller than the resistance at the contact portion between the conductive layer in the via and the upper electrode CP. For this reason, as in the first embodiment, it is possible to suppress variations in resistance values when viewed in the entire wiring layer, increase a margin in circuit timing, and suppress deterioration in yield and reliability. .

(Embodiment 6)
In the present embodiment, a structure in the case where a wiring layer is connected to each of a source / drain region and a gate electrode layer of a MOS transistor will be described.

  FIG. 16 is a cross sectional view schematically showing a configuration of the semiconductor device in the sixth embodiment of the present invention. Referring to FIG. 16, MOS transistor TR is formed on the surface of semiconductor substrate SUB. This MOS transistor TR mainly has a pair of source / drain regions SD, a gate insulating film GI, and a gate electrode layer GE.

  Each of the pair of source / drain regions SD is formed at a distance from the surface of the semiconductor substrate SUB. The gate electrode layer GE is formed on the region of the semiconductor substrate SUB sandwiched between the pair of source / drain regions SD via the gate insulating film GI.

  An insulating film IN and an interlayer insulating film II are sequentially stacked on the surface of the semiconductor substrate SUB so as to cover the MOS transistor TR.

  A plurality of wiring trenches IT2 are formed on the surface of the interlayer insulating film II. The plurality of wiring trenches IT2 include a wiring trench IT2 for routing a wiring layer IL2 electrically connected to the source / drain region SD of the MOS transistor TR, and a wiring layer electrically connected to the gate electrode layer GE. A wiring trench IT2 for routing IL2 is included.

  The depth BDE of the first via hole VH for electrically connecting the wiring layer IL2 to the source / drain region SD is that of the second via hole VH for electrically connecting the wiring layer IL2 to the gate electrode layer GE. It is deeper than the depth BDE. The digging amount CDE of the concave portion CO of the source / drain region SD immediately below the first via hole VH reaching the source / drain region SD is equal to the concave portion of the gate electrode layer GE immediately below the second via hole VH reaching the gate electrode layer GE. CO digging amount is larger than CDE.

  The thickness of the portion of the second barrier metal layer BM2b that is in contact with the wiring layer IL1 is lower at the bottom of the first via hole VH having a deep via depth BDE than at the bottom of the second via hole VH having a shallow via depth BDE. It is getting thinner.

  As described above, the resistance of the contact portion between the conductive layer (wiring layer IL2) in the first via hole VH reaching the source / drain region SD and the source / drain region SD is in the second via hole VH reaching the gate electrode layer GE. This is smaller than the resistance of the contact portion between the conductive layer (wiring layer IL2) and the gate electrode layer GE.

  In the present embodiment, each of the width IW and the depth TD of the wiring trench IT2 in which the wiring layer IL2 electrically connected to the source / drain region SD is formed is electrically connected to the gate electrode layer GE. The size is substantially the same as the width IW and the depth TD of the wiring trench IT2 in which the wiring layer IL2 to be formed is formed. The diameter of the conductive layer (wiring layer IL2) in the first via hole VH reaching the source / drain region SD and the diameter of the conductive layer (wiring layer IL2) in the second via hole VH reaching the gate electrode layer GE are substantially the same. Are the same dimensions.

Next, the effect of this Embodiment is demonstrated.
When forming the MOS transistor TR, the depth BDE of the via hole VH reaching the source / drain region SD is deeper than the depth BDE of the via hole VH reaching the gate electrode layer GE. Therefore, when both via holes VH have the same diameter, the aspect ratio of via hole VH reaching source / drain region SD is larger than the aspect ratio of via hole VH reaching gate electrode layer GE.

  For example, when the diameter BDI of the via hole VH is 60 nm, the depth BDE of the via hole VH reaching the gate electrode layer GE is 120 nm, and the depth BDE of the via hole VH reaching the source / drain region SD is 240 nm, the gate electrode layer GE is reached. The aspect ratio of the via hole VH is 2.0, whereas the aspect ratio of the via hole VH reaching the source / drain region SD is as high as 4.0.

  On the other hand, in the present embodiment, the resistance of the contact portion between the conductive layer in the via in the first via hole VH reaching the source / drain region SD and the source / drain region SD reaches the second gate electrode layer GE. The resistance of the contact portion between the conductive layer in the via in the via hole VH and the gate electrode layer GE is smaller. For this reason, as in the first embodiment, it is possible to suppress variations in resistance values when viewed in the entire wiring layer, increase a margin in circuit timing, and suppress deterioration in yield and reliability. .

In this case, the same can be said for the lifted source / drain structure of the active region portion.
In the above description, the MOS transistor has been described as an example. However, the present invention can be widely applied to all MIS (Metal Insulator Semiconductor) transistors.

(Embodiment 7)
In this embodiment, a structure in the case where a wiring layer is connected to each of a support substrate and a semiconductor layer of an SOI substrate will be described.

  FIG. 17 is a cross sectional view schematically showing a configuration of the semiconductor device according to the seventh embodiment of the present invention. Referring to FIG. 17, the SOI substrate includes a support substrate SS, a buried insulating film BI, and a semiconductor layer (SOI layer) TF. A bottom injection layer BT is formed on the surface of the support substrate SS. A mesa-isolated semiconductor layer (SOI layer) TF is formed on the surface of the support substrate SS via a buried insulating film BI. A sidewall insulating film SW is formed so as to cover the sidewall of the semiconductor layer TF.

An interlayer insulating film II is formed on the SOI substrate.
A plurality of wiring trenches IT2 are formed on the surface of the interlayer insulating film II. The plurality of wiring trenches IT2 include a wiring trench IT2 for routing the wiring layer IL2 electrically connected to the bottom injection layer BT and a wiring for routing the wiring layer IL2 electrically connected to the semiconductor layer TF. A groove IT2 is included.

  The depth BDE of the first via hole VH for electrically connecting the wiring layer IL2 to the bottom injection layer BT is the depth of the second via hole VH for electrically connecting the wiring layer IL2 to the semiconductor layer TF. It is deeper than BDE. The digging amount CDE of the recess CO in the bottom injection layer BT directly under the first via hole VH reaching the bottom injection layer BT is the digging of the recess CO in the semiconductor layer TF directly under the second via hole VH reaching the semiconductor layer TF. It is larger than the quantity CDE.

  The thickness of the portion of the second barrier metal layer BM2b that is in contact with the wiring layer IL1 is lower at the bottom of the first via hole VH having a deep via depth BDE than at the bottom of the second via hole VH having a shallow via depth BDE. It is getting thinner.

  As described above, the resistance of the contact portion between the conductive layer (wiring layer IL2) in the first via hole VH reaching the bottom injection layer BT and the bottom injection layer BT is equal to the conductive layer in the second via hole VH reaching the semiconductor layer TF. It is smaller than the resistance of the contact portion between (wiring layer IL2) and semiconductor layer TF.

  In the present embodiment, each of the width IW and the depth TD of the wiring trench IT2 in which the wiring layer IL2 electrically connected to the bottom injection layer BT is formed is electrically connected to the semiconductor layer TF. The wiring groove IL2 in which the wiring layer IL2 is formed has substantially the same dimensions as the width IW and the depth TD. The diameter of the conductive layer (wiring layer IL2) in the first via hole VH reaching the bottom injection layer BT and the diameter of the conductive layer (wiring layer IL2) in the second via hole VH reaching the semiconductor layer TF are substantially equal. Same dimensions.

Next, the effect of this Embodiment is demonstrated.
When the SOI substrate is used, the depth BDE of the via hole VH reaching the bottom injection layer BT becomes deeper than the depth BDE of the via hole VH reaching the semiconductor layer TF. For this reason, when both via holes VH have the same diameter, the aspect ratio of the via hole VH reaching the bottom injection layer BT is larger than the aspect ratio of the via hole VH reaching the semiconductor layer TF.

  For example, when the diameter BDI of the via hole VH is 60 nm, when the depth BDE of the via hole VH reaching the semiconductor layer TF is 180 nm and the depth BDE of the via hole VH reaching the bottom injection layer BT is 330 nm, the via hole VH reaching the semiconductor layer TF While the aspect ratio is 3.0, the aspect ratio of the via hole VH reaching the bottom injection layer BT is as high as 5.5.

  On the other hand, in the present embodiment, the resistance of the contact portion between the conductive layer in the first via hole VH reaching the bottom injection layer BT and the bottom injection layer BT has a resistance in the second via hole VH reaching the semiconductor layer TF. It is smaller than the resistance of the contact portion between the conductive layer and the semiconductor layer TF. For this reason, as in the first embodiment, it is possible to suppress variations in resistance values when viewed in the entire wiring layer, increase a margin in circuit timing, and suppress deterioration in yield and reliability. .

  In the first to seventh embodiments described above, the case where each of the interlayer insulating films II, II1, and II2 is a SiOC film has been described. However, the present invention is not limited to this. Each of the interlayer insulating films II, II1, and II2 includes a ULK (Ultra Low-k SiOC) film (dielectric constant k: 2.5 or less) and an ELK (Extremely Low-k SiOC) film (dielectric constant k: 2.2 or less). ), Spin-coated porous MSQ (Methyl Silses Quioxane) film (dielectric constant k: 2.2 or less), laminated film thereof, FSG (Fluorinated Silicate Glass) film or TEOS (Tetra Ethyl Ortho Silicate) film The present invention can be similarly applied even to a laminated film.

  Further, although the case where the liner insulating film LF is a p-SiC film has been described, the liner insulating film LF may be a p-SiCO film, a p-SiCN film, or a laminated film thereof. Further, the liner insulating film LF may be omitted.

  In the first to seventh embodiments, each of the barrier metal layers BM1, BM2a, and BM2b is one or more materials selected from the group consisting of TaN, TiN, Ta, Ti, Ru, and Mn, and those materials. These oxides, nitrides thereof, and laminated films of these materials may also be used.

Embodiments of the present invention will be described below with reference to the drawings.
Example 1
The present inventor has examined the amount of digging of the concave portion CO immediately below the via hole VH. The contents and results of the study are described below.

  In circuit design, there is a demand to suppress resistance variation to 10% or less. For example, even when patterns having different line widths IW as shown in FIGS. 18 and 19 are mixed, (1) resistance at the junction interface between the wiring layers IL1 and IL2, and (2) via holes. The total of the resistance of the conductive layer in VH and (3) the resistance of the wiring layer IL2 in the wiring groove IT2 should be kept within ± 10% (2.7 to 3.3Ω) of the assumed resistance (for example, 3Ω). Is preferred.

  18 shows a configuration in which the minimum line width IW of the wiring layer is 70 nm, and FIG. 19 shows a configuration in which the maximum line width IW of the wiring layer is 1 μm.

  Therefore, when the line width IW of the wiring layer is changed from 70 nm to 1 μm, the total value of the resistances (1) to (3) is ± 10% (2.7 to 3) of the assumed resistance (for example, 3Ω). .3Ω) was investigated for the amount of recess CO digging. The results are shown in FIG. 20 and FIG.

  As shown in FIG. 20, the digging amount when the line width IW is 70 nm is about 50 nm, the digging amount when the line width IW is 1 μm is about 40 nm, and the line width IW is gradually dug from 70 nm to 1 μm. It has been found that the total resistance value can be suppressed to 2.7 to 3.3Ω as shown in FIG.

  From this, it was found that the digging amount of the minimum line width IW (70 nm) is preferably 1.2 times or more of the digging amount of the maximum line width IW (1 μm).

(Example 2)
The inventor has also studied the aspect ratio of the via hole VH. The contents and results of the study are described below.

  Using the sputtering apparatus shown in FIG. 11, the change in the amount of digging of the recess CO when the substrate AC bias or the DC power of the target was changed at various aspect ratios was examined. The result is shown in FIG.

  From the results of FIG. 22, it can be seen that the digging amount increases when the aspect ratio is high. In particular, it can be seen that when the aspect ratio is 2.5 or more, the digging amount of the recess CO is 30 nm or more. When the aspect ratio was 2.0 or less, the digging amount of the recess CO was less than 30 nm, and the electromigration lifetime was deteriorated.

  From this, it was found that the aspect ratio of the via hole VH is preferably 2.5 or more.

(Example 3)
The inventor has also studied the relationship between the radius of the via hole VH and the amount of digging of the concave portion CO. The contents and results of the study are described below.

  The allowable amount of resistance at the junction interface between the wiring layer IL1 and the wiring layer IL2 allowed in the generation of the via hole VH having a diameter of 70 nm is less than 1.0Ω. Therefore, the amount of digging of the recess CO where the resistance value at the junction interface between the wiring layer IL1 and the wiring layer IL2 is less than 1.0Ω was examined. The result is shown in FIG.

  From the results shown in FIG. 23, it was found that the digging amount of the concave portion CO needs to be larger than 30 nm in order to make the resistance value at the junction interface between the wiring layer IL1 and the wiring layer IL2 less than 1.0Ω. Here, the diameter of the via hole VH is 70 nm. For this reason, it was found that when the amount of digging of the concave portion CO is equal to or larger than the radius of the via hole VH, the resistance value at the junction interface between the wiring layer IL1 and the wiring layer IL2 is less than 1.0Ω.

  It should be noted that the digging amount of the recess CO can be controlled by the resputtering time using the sputtering apparatus shown in FIG. 11 as shown in FIG. If the resputtering time is longer than 10.5 seconds, the digging amount of the recess CO can be made larger than 30 nm.

  From the results of Examples 1 to 3, the digging amount of the concave portion CO immediately below the first via hole VH in Embodiments 1 to 7 is 1.2 of the digging amount of the concave portion CO immediately below the second via hole VH. It is preferable that it is twice or more. In the first to seventh embodiments, it is preferable that the digging amount of the concave portion CO immediately below the first via hole VH is larger than the radius of the first via hole VH. The aspect ratio of each of first and second via holes VH in the first to seventh embodiments is preferably 2.5 or more.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a cross sectional view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 5th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 6th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 7th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 8th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 9th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic diagram which shows the structure of the sputtering device used for a resputtering process. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 3 of this invention. FIG. 6 is a plan view (A) and a cross-sectional view (B) schematically showing a configuration of a semiconductor device in a fourth embodiment of the present invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 5 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 6 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 7 of this invention. 2A and 2B are a plan view and a cross-sectional view showing a configuration in which the minimum line width IW of the wiring layer is 70 nm. 2A and 2B are a plan view and a cross-sectional view showing a configuration in which the maximum line width IW of the wiring layer is 1 μm. It is a figure which shows the relationship between the line width of a wiring layer, and the amount of digging of a recessed part. It is a figure which shows the relationship between the line | wire width of a wiring layer, and the resistance of each part. It is a figure which shows the relationship between the sputter | spatter conditions in resputtering when the aspect ratio of a via hole is changed, and the digging amount of a recessed part. It is a figure which shows the relationship between the digging amount of a recessed part, and the resistance of the junction interface between wiring layers. It is a figure which shows the relationship between resputtering time and the amount of digging of a recessed part.

Explanation of symbols

  BI buried insulating film, BM1, BM2, BM2a, BM2b, BM3 barrier metal layer, BT bottom injection layer, CD capacitor dielectric film, CI contact interlayer insulating film, CL1, CL2, CL3 conductive layer, CO recess, CP upper electrode, GE gate electrode layer, GI gate insulating film, II, II1, II2 interlayer insulating film, IL1, IL2 wiring layer, IN insulating film, IT, IT1, IT2 wiring groove, LF liner insulating film, PR1, PR2, PR3, PR4 photo Resist, SD drain region, SN lower electrode, SS support substrate, SUB semiconductor substrate, SW sidewall insulating film, TF semiconductor layer, TR MOS transistor, VH via hole.

Claims (6)

A lower conductive layer;
First and second wiring layers each formed on the lower conductive layer;
A first via hole formed between the lower conductive layer and the first and second wiring layers and electrically connecting the lower conductive layer and the first wiring layer and the lower conductive layer An interlayer insulating film having a second via hole for electrically connecting the layer and the second wiring layer;
First and second via conductive layers that embed each of the first and second via holes,
The first wiring layer has a narrower line width than the second wiring layer,
A semiconductor device, wherein a resistance of a contact portion between the first conductive layer in the via and the lower conductive layer is smaller than a resistance of a contact portion between the second conductive layer in the via and the lower conductive layer. A recess is formed on the surface of the lower conductive layer immediately below the first via hole and immediately below the second via hole, and the amount of digging of the recess immediately below the first via hole is The semiconductor device according to claim 1, wherein the semiconductor device is larger than a digging amount of the concave portion immediately below the second via hole. 3. The semiconductor device according to claim 2, wherein an amount of digging of the concave portion immediately below the first via hole is 1.2 times or more of an amount of digging of the concave portion immediately below the second via hole. Wherein the amount of engraving of the recess directly below the first via hole is larger than the radius of said first via hole, the semiconductor device according to claim 2 or 3. Each of the first and second in-via conductive layers includes first and second barrier metal layers;
The thickness of the first barrier metal layer in the bottom of the first via hole is thinner than the thickness of the second barrier metal layer at the bottom of the second via hole, claim 1-4 A semiconductor device according to 1. Wherein each aspect ratio of the first and second via holes is 2.5 or more, the semiconductor device according to any one of claims 1-5.

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