JP7247305B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device and its manufacturing technology, and more particularly to a technology effectively applied to a semiconductor device including copper wiring and its manufacturing technology.

International Publication No. 2006/016678 (Patent Document 1) describes a semiconductor device in which a first copper wiring and a second copper wiring having different wiring widths are formed in the same wiring layer.

International Publication No. 2006/016678

For example, in a semiconductor device, a copper wiring containing copper as a main component is sometimes used. may be formed. Specifically, the wide wiring is used, for example, as a power supply wiring that supplies a power supply potential, and the narrow wiring is used as a signal wiring that transmits signals.

Here, the wide wiring and narrow wiring formed in the same layer are formed in the same process by, for example, the "damascene method". A narrow wiring is, for example, a fine wiring formed with the minimum processing dimensions, and in order to ensure the embedding characteristics of the film by the "damascene method", it is necessary to reduce the film thickness of the barrier conductor film included in the narrow wiring. be. Therefore, even when the wide wiring is formed in the same layer as the narrow wiring, the film thickness of the barrier conductor film included in the wide wiring is inevitably thin because it is formed in the same process as the narrow wiring. Become.

For example, focusing on the "dual damascene method" in which a copper wiring and a plug are formed together, a barrier conductor film is formed on the bottom of the plug formed together with the copper wiring. For this reason, if the thickness of the barrier conductor film is reduced in consideration of the embedding characteristics of the narrow wiring formed with the minimum processing dimensions, the plug placed under the narrow wiring and connected to the narrow wiring will not have a sufficient thickness to fill the bottom of the plug. The thickness of the barrier conductor film to be formed is also reduced, and the thickness of the barrier conductor film formed on the bottom portion of the plug arranged in the lower layer of the wide wiring and connected to the wide wiring is also reduced.

At this time, a barrier conductor film intervenes between the plug and the lower layer wiring. According to studies by the present inventors, the resistance value of the plug increases as the thickness of the barrier conductor film decreases. It was revealed. On the other hand, since a wide wiring requires a large current to flow, it is desirable to reduce the resistance value of a plug that is arranged in a layer below the wide wiring and is connected to the wide wiring. Therefore, in the current semiconductor device and its manufacturing technology, there is room for improvement from the viewpoint of lowering the resistance value of the plug arranged in the lower layer of the wide wiring and connected to the wide wiring. In other words, there is room for improvement in the current semiconductor device and its manufacturing technology from the viewpoint of improving the performance of the semiconductor device.

Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

A semiconductor device according to one embodiment includes a wide wiring (first copper wiring) and a narrow wiring (second copper wiring) formed in the same layer, and is arranged below the wide wiring and connected to the wide wiring. The resistance value of the first plug (first copper plug) is smaller than the resistance value of the second plug (second copper plug) arranged below the narrow wire and connected to the narrow wire.

A method of manufacturing a semiconductor device according to one embodiment includes a step of forming a tantalum nitride film by a sputtering method in which tantalum is used as a target and nitrogen gas is introduced into a processing chamber. is within a range in which the film thickness of the tantalum nitride film formed on the bottom of the first plug (first copper plug) is 5 nm or more and 10 nm or less.

Further, in the method of manufacturing a semiconductor device according to one embodiment, after nitrogen gas is exhausted, the tantalum film is formed on the tantalum nitride film by a sputtering method using tantalum as a target and applying a substrate pull-in bias to the semiconductor substrate. In this step, a substrate pull-in bias is applied so that the potential on the semiconductor substrate is in the range of -350V to -800V.

According to one embodiment, the performance of a semiconductor device can be improved.

1 is a cross-sectional view showing a device structure example of a semiconductor device; FIG. FIG. 3 is a cross-sectional view schematically showing a configuration example in which a part of the multilayer wiring structure is enlarged; For example, it is a cross-sectional view schematically showing an enlarged configuration example of a part of a multilayer wiring structure having fine wiring with a half pitch of about 60 nm or about 45 nm. 4 is a graph showing the relationship between the specific resistance (resistivity) of a laminated film in which a tantalum film is formed on a tantalum nitride film and the film thickness of the tantalum nitride film. 2 is a cross-sectional view showing an enlarged part of the multilayer wiring structure shown in FIG. 1; FIG. A qualitative description will be given of the difference between the thickness of a barrier conductor film formed on the bottom of a plug connected to a wide wiring and the thickness of a barrier conductor film formed on the bottom of a plug connected to a narrow wiring. It is a diagram. 7 is a graph showing measurement results of the plug resistance of a plug connected to a wide wiring and the plug resistance of a plug connected to a narrow wiring in the prior art. 1 is a cross-sectional view showing an enlarged part of a multilayer wiring structure in an embodiment; FIG. 7 is a graph showing measurement results of plug resistance of a plug connected to a wide wiring and plug resistance of a plug connected to a narrow wiring in an embodiment; 4A to 4C are cross-sectional views showing a manufacturing process of the semiconductor device in the embodiment; 11 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 10; FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 11; FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 12; FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 13; FIG. 15 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 14; FIG. It is a figure which shows the structure of the sputtering device used in embodiment. 4 is a table showing film formation conditions in a tantalum nitride film formation process. 4 is a table showing film formation conditions in a tantalum film formation process; FIG. 10 is a diagram for explaining the introduction timing of nitrogen gas in the process of forming a tantalum nitride film in a modified example;

For the sake of convenience, the following embodiments are divided into a plurality of sections or embodiments when necessary, but unless otherwise specified, they are not independent of each other, and one There is a relationship of part or all of the modification, details, supplementary explanation, etc.

In addition, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), when it is particularly specified, when it is clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Needless to say.

Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., unless otherwise explicitly stated or in principle clearly considered to be otherwise, It shall include those that approximate or resemble the shape, etc. This also applies to the above numerical values and ranges.

In addition, in all the drawings for explaining the embodiments, the same members are basically given the same reference numerals, and repeated description thereof will be omitted. In order to make the drawing easier to understand, even a plan view may be hatched.

(Embodiment)
<Device structure of semiconductor device>
First, an example of the device structure of a semiconductor device will be described. FIG. 1 is a cross-sectional view showing an example of the device structure of a semiconductor device. In FIG. 1, for example, a MISFETQ is formed on a semiconductor substrate 1S made of silicon single crystal. The MISFETQ has a gate insulating film made of, for example, a silicon oxide film on the main surface of the semiconductor substrate 1S. ) has a gate electrode made of a laminated film. Sidewalls made of, for example, a silicon oxide film are formed on both side walls of the gate electrode, and a source region and a drain region are formed in alignment with the gate electrode in the semiconductor substrate 1S below the side walls. there is As described above, the MISFETQ is formed on the semiconductor substrate 1S.

Subsequently, as shown in FIG. 1, a contact interlayer insulating film CIL is formed over the semiconductor substrate 1S on which the MISFETQ is formed. The contact interlayer insulating film CIL is composed of, for example, an ozone TEOS film formed by a thermal CVD method using ozone and TEOS (tetraethyl orthosilicate) as raw materials, and TEOS provided on the ozone TEOS film as raw materials. It is formed of a laminated film with a plasma TEOS film formed by the plasma CVD method used. A plug PLG0 is formed to penetrate the contact interlayer insulating film CIL and reach the source region and the drain region of the MISFETQ. The plug PLG0 includes a barrier conductor film made of, for example, a titanium/titanium nitride film (hereinafter, the titanium/titanium nitride film indicates a film formed of titanium and titanium nitride provided on the titanium), and the barrier conductor film. It is formed by filling the contact hole with a tungsten film formed on the film. The titanium/titanium nitride film is a film provided to prevent tungsten forming the tungsten film from diffusing into silicon, and WF6 (tungsten fluoride) is reduced when forming the tungsten film. This is to prevent the contact interlayer insulating film CIL and the semiconductor substrate 1S from being damaged by the fluorine attack in the CVD method. Note that the contact interlayer insulating film CIL may be formed of any one of a silicon oxide film (SiO ₂ film), an SiOF film, or a silicon nitride film.

Next, a wiring L1, which is a first layer wiring, is formed over the contact interlayer insulating film CIL. Specifically, the wiring L1 is formed so as to be embedded in the interlayer insulating film IL1 formed over the contact interlayer insulating film CIL in which the plug PLG0 is formed. That is, the wiring L1 is formed by embedding a film mainly containing copper (hereinafter referred to as a copper film) in the wiring trench penetrating the interlayer insulating film IL1 and exposing the plug PLG0 at the bottom.

Here, the "main component" as used in this specification refers to a material component that is contained in the largest amount among the constituent materials that constitute the member (layer or film). The term "membrane having a high density" means that the material of the film contains the most copper (Cu). The intention of using the term “main component” in this specification is to express that, for example, the conductor film is basically composed of copper, but does not exclude the case where other impurities are included. are using.

The interlayer insulating film IL1 is, for example, a SiOC film, an HSQ (hydrogen silsesquioxane, silicon oxide film formed by a coating process and having Si—H bonds, or a hydrogen-containing silsesquioxane) film, or an MSQ film. (methyl silsesquioxane, a silicon oxide film formed by a coating process and having Si—C bonds, or carbon-containing silsesquioxane) film. Here, the wiring layer in which the wiring L1 is formed may be called a fine layer in this specification.

Subsequently, a second layer wiring is formed over the interlayer insulating film IL1 on which the wiring L1 is formed. In FIG. 1, for example, a wide wiring WL2 and a narrow wiring NL2 having different wiring widths are shown as the second layer wiring. That is, in the second layer wiring shown in FIG. 1, wide wiring WL2 with a large wiring width and narrow wiring NL2 with a small wiring width are formed. That is, in the semiconductor device, for example, a wide wiring WL2 and a narrow wiring NL2 having different wiring widths are formed in the same wiring layer where the second layer wiring is formed. At this time, the wide wiring WL2 is used, for example, as a power supply wiring through which a large current flows, while the narrow wiring NL2 is used as a signal wiring which does not require a large current to flow. Here, an example is described in which a wide wiring WL2 and a narrow wiring NL2 having different wiring widths are formed in the second layer wiring. Wiring is provided.

Thus, the second layer wiring is formed over the interlayer insulating film IL1. Specifically, the barrier insulating film BIF1 (liner film) is formed over the interlayer insulating film IL1 on which the wiring L1 is formed, An interlayer insulating film IL2 is formed over the barrier insulating film BIF1. The barrier insulating film BIF1 is formed of, for example, any one of a laminated film of a SiCN film and a SiCO film provided on the SiCN film, a SiC film, or a SiN film. The interlayer insulating film IL2 is formed of, for example, a SiOC film having holes, an HSQ film having holes, or an MSQ film having holes. The size (diameter) of the pores is, for example, about 1 nm. A wide wiring WL2, a narrow wiring NL2, a plug PLG1A and a plug PLG1B are formed so as to be embedded in the barrier insulating film BIF1 and the interlayer insulating film IL2. At this time, the plug PLG1A and the plug PLG1B have the same size and are formed in the same layer. The wide wiring WL2, the narrow wiring NL2, the plug PLG1A and the plug PLG1B described above are formed of, for example, a copper film. A wiring layer in which a second layer wiring including the wide wiring WL2 and the narrow wiring NL2 is formed is also called a fine layer.

Then, as shown in FIG. 1, third-layer wiring to fourth-layer wiring are formed in the same manner as the second-layer wiring. Specifically, a barrier insulating film BIF2 is formed over the interlayer insulating film IL2, and an interlayer insulating film IL3 is formed over the barrier insulating film BIF2. The barrier insulating film BIF2 is formed of, for example, any one of a stacked film of a SiCN film and a SiCO film provided on the SiCN film, a SiC film, or a SiN film, and the interlayer insulating film IL3 is , for example, a SiOC film with holes, an HSQ film with holes, or an MSQ film with holes. The barrier insulating film BIF2 and the interlayer insulating film IL3 are formed so as to be embedded with the wiring L3 and the plug PLG2 which are the third layer wiring. This wiring L3 and plug PLG2 are also formed of, for example, a copper film.

Subsequently, a barrier insulating film BIF3 is formed over the interlayer insulating film IL3, and an interlayer insulating film IL4 is formed over the barrier insulating film BI3. The barrier insulating film BIF3 is formed of, for example, any one of a laminated film of a SiCN film and a SiCO film provided on the SiCN film, a SiC film, or a SiN film. Further, the interlayer insulating film IL4 is formed of, for example, a SiOC film having holes, an HSQ film having holes, or an MSQ film having holes. The barrier insulating film BIF3 and the interlayer insulating film IL4 are formed so as to be embedded with the wiring L4 and the plug PLG3 which are the fourth layer wiring. This wiring L4 and plug PLG3 are also formed of, for example, a copper film. Here, the wiring layer in which the wiring L3 is formed and the wiring layer in which the wiring L4 is formed are also called fine layers.

Further, a barrier insulating film BIF4 is formed over the interlayer insulating film IL4, and an interlayer insulating film IL5 is formed over this barrier insulating film BIF4. The barrier insulating film BIF4 is formed of, for example, any one of a stacked film of a SiCN film and a SiCO film, a SiC film, or a SiN film. Also, the interlayer insulating film IL5 is formed of, for example, a silicon oxide film (SiO ₂ film), an SiOF film, or a TEOS film. In the barrier insulating film BIF4 and the interlayer insulating film IL5, the plug PLG4 and the wiring L5, which is the fifth layer wiring, are formed so as to be embedded. This wiring L5 and plug PLG4 are also formed of, for example, a copper film. Here, the wiring layer in which the wiring L5 is formed is called a global layer.

Subsequently, a pad PD, which is a sixth layer wiring, is formed on the interlayer insulating film IL5. The pad PD is made of, for example, a film containing aluminum as its main component. Specifically, the pad is composed of, for example, an aluminum film, an AlSi film in which silicon is added to aluminum, or an AlSiCu film in which silicon and copper are added to aluminum.

A surface protective film PAS (passivation film) is formed over the pad PD, and a part of the pad PD is exposed through an opening formed in the surface protective film PAS. The surface protection film PAS has a function of protecting the device from intrusion of impurities, and is formed of, for example, a silicon oxide film and a silicon nitride film provided on the silicon oxide film. A polyimide film (not shown) is formed on the surface protective film PAS. This polyimide film also has an opening in the region where the pad PD is formed.

For example, a wire (not shown) is connected to the pad PD, and the polyimide film including the pad PD to which the wire is connected is sealed with a resin serving as a sealing body. Thus, the device structure of the semiconductor device shown in FIG. 1 is realized.

In the device structure shown in FIG. 1, first to sixth wiring layers are formed. For example, the first to fourth wiring layers constitute fine layers, and the fifth layer is a global layer. constitutes Here, the "fine layer" means a wiring layer in which fine wirings close to the minimum processing dimension are formed, and the "global layer" means a wiring layer in which wirings larger in size than the "fine layer" are formed. It means a wiring layer with FIG. 1 shows an example in which the "global layer" is formed on the "fine layer" in order to simplify the explanation of the multilayer wiring structure. Generally, a "semi-global layer" is formed, and a "global layer" is formed on this "semi-global layer". The "semi-global layer" means a wiring layer in which wirings larger than the "fine layer" but smaller than the "global layer" are formed. In other words, focusing on the wiring size, the "semi-global layer" can be said to be a wiring layer having wiring of an intermediate size between the "fine layer" and the "global layer".

<Room for improvement>
Although a schematic device structure of a semiconductor device has been described with reference to FIG. 1, for example, if attention is paid to an actual copper wiring, the copper wiring is composed of a barrier conductor film and a copper film. In order to reduce the size and improve the degree of integration of semiconductor devices, it is necessary to miniaturize copper wiring. The study by the present inventor has revealed that there is room for improvement from the viewpoint of improving the performance of the semiconductor device. That is, when focusing on the barrier conductor film included in the copper wiring, there is room for improvement in the current semiconductor device from the viewpoint of improving the performance of the semiconductor device. Specifically, in a semiconductor device having a copper wiring and a copper plug formed by the "damascene method", the improvement is made from the viewpoint of lowering the resistance value of the copper plug that is arranged in the lower layer of the copper wiring and connected to the copper wiring. There is room for This room for improvement will be described below with reference to the drawings.

FIG. 2 is a cross-sectional view schematically showing a configuration example in which a part of the multilayer wiring structure is enlarged. As shown in FIG. 2, for example, on a wiring line L1 mainly composed of copper formed by a "single damascene method", a plug PLG mainly composed of copper integrally formed by a "dual damascene method" and a A wiring L2 is arranged. That is, the wiring L1, which is the lower wiring, and the wiring L2, which is the upper wiring, are electrically connected via the plug PLG. Here, the plug PLG is formed by embedding the barrier conductor film BCF and the copper film CF in the contact hole CNT, and the wiring L2 is formed in the wiring groove WD integrally formed with the contact hole CNT with the barrier conductor film BCF. It is formed by embedding a copper film CF. At this time, the barrier conductor film BCF is composed of, for example, a tantalum nitride film TNF formed on the inner wall of the connection hole CNT and the inner wall of the wiring trench WD, and a tantalum film TF formed on the tantalum nitride film TNF. there is

The reason why the barrier conductor film BCF is formed without directly forming the copper film on the inner wall of the connection hole CNT and the inner wall of the wiring groove WD is that the copper forming the copper film forms the semiconductor substrate by heat treatment or the like. This is to prevent diffusion into silicon. That is, since the diffusion constant of copper atoms into silicon is relatively large, copper atoms easily diffuse into silicon. In this case, a semiconductor element such as a MISFET is formed on the semiconductor substrate, and if copper atoms are diffused into these forming regions, the characteristic deterioration of the semiconductor element such as a breakdown voltage failure is caused. For this reason, the barrier conductor film BCF is provided so that the copper atoms do not diffuse from the copper film forming the wiring. In other words, it can be seen that the barrier conductor film BCF is a film having a function of preventing the diffusion of copper atoms. As described above, an actual multi-layer wiring is formed by, for example, plugs PLG and wiring L2 mainly made of copper integrally formed on wiring L1 mainly made of copper, as shown in FIG. It will be placed.

Here, in FIG. 2, it is assumed that the wiring width of the wiring L2 is relatively large compared to the minimum processing dimension. Since deterioration of embedding characteristics when embedding in the trench WD is unlikely to become apparent as a problem, the thickness of the barrier conductor film BCF formed on the inner wall of the connection hole CNT and the inner wall of the wiring trench WD is increased.

However, for example, when forming fine wiring with a half pitch of about 60 nm or a half pitch of about 45 nm, the situation changes completely. FIG. 3 is a cross-sectional view schematically showing an enlarged configuration example of a part of a multilayer wiring structure having fine wiring with a half pitch of about 60 nm or about 45 nm, for example. In FIG. 3 as well, the plug PLG and the wiring L2 mainly composed of copper integrally formed by the "dual damascene method" are arranged on the wiring L1 mainly composed of copper formed by the "single damascene method". It is At this time, when the wiring L2 is a fine wiring, if the thickness of the barrier conductor film BCF is increased, deterioration in embedding characteristics when the copper film CF is embedded in the wiring trench WD becomes apparent as a problem. Therefore, in FIG. 3, the barrier conductor film BCF formed on the inner wall of the connection hole CNT and the inner wall of the wiring trench WD needs to be thinner than the barrier conductor film BCF shown in FIG.

2 and 3, even if the size of the plug PLG shown in FIG. 2 and the size of the plug PLG shown in FIG. 3 are the same, the barrier conductor formed at the bottom of the plug PLG shown in FIG. The thickness of the film BCF is thinner than the thickness of the barrier conductor film BCF formed at the bottom of the plug PLG shown in FIG. For this reason, the plug resistance (via resistance) of the plug PLG shown in FIG. 2 and the plug resistance of the plug PLG shown in FIG. 3 are different.

Specifically, the resistivity (specific resistance) of the barrier conductor film BCF is higher than that of the copper film CF. For this reason, when a current flows from the wiring L2 to the wiring L1 via the plug PLG (see the arrows in FIGS. 2 and 3), at first glance, the plug PLG having the thick barrier conductor film BCF shown in FIG. The plug resistance is considered to be higher than the plug resistance of the plug PLG with the thin barrier conductor film BCF shown in FIG. However, in practice, the plug resistance of the plug PLG with the thick barrier conductor film BCF shown in FIG. 2 is lower than the plug resistance of the plug PLG with the thin barrier conductor film BCF shown in FIG. of. In other words, the plug resistance of the plug PLG with the thin barrier conductor film BCF shown in FIG. 3 is higher than the plug resistance of the plug PLG with the thick barrier conductor film BCF shown in FIG. That is, as shown in FIG. 3, when the wiring L2 is composed of a fine wiring with a half pitch of about 60 nm or about 45 nm, the plug resistance of the plug PLG arranged in the lower layer of the wiring L2 and connected to the wiring L2 increases. I do.

Here, the reason why the plug resistance of the plug PLG with the thin barrier conductor film BCF shown in FIG. 3 is higher than the plug resistance of the plug PLG with the thick barrier conductor film BCF shown in FIG. 2 will be described. do.

In FIG. 2, the barrier conductor film BCF formed at the bottom of the plug PLG is thick. At this time, since the barrier conductor film BCF is composed of the tantalum nitride film TNF and the tantalum film TF formed on the tantalum nitride film TNF, the film thickness of the tantalum nitride film TNF is sufficiently thick. can be considered. When the film thickness of the tantalum nitride film TNF is secured in this way, the crystal structure of the tantalum film TF formed on the tantalum nitride film TNF becomes the α-Ta structure, which is a body-centered cubic structure.

On the other hand, in FIG. 3, the thickness of the barrier conductor film BCF formed at the bottom of the plug PLG is thin. Therefore, it can be considered that the film thickness of the tantalum nitride film TNF, which is a constituent film of the barrier conductor film BCF, is also reduced. When the tantalum nitride film TNF is thin in this way, the crystal structure of the tantalum film TF formed on the tantalum nitride film TNF is a β-Ta structure, which is a tetragonal structure.

In other words, in the plug PLG with the thick barrier conductor film BCF shown in FIG. , the crystal structure of tantalum becomes a β-Ta structure. Due to this, the plug resistance of the plug PLG shown in FIG. 3 is higher than that of the plug PLG shown in FIG. This is because the resistivity of the α-Ta structure is lower than that of the β-Ta structure. That is, in the plug PLG having the thick barrier conductor film BCF shown in FIG. 2, the thickness of the barrier conductor film BCF itself is large, but the crystalline structure of the tantalum film, which is a constituent film of the barrier conductor film BCF, has a low resistivity. Because of the α-Ta structure, the overall plug resistance of the plug PLG shown in FIG. 2 is lowered. On the other hand, in the plug PLG with the thin barrier conductor film BCF shown in FIG. As a result, the plug resistance of the plug PLG shown in FIG. 3 is generally increased.

Therefore, focusing only on the film thickness of the barrier conductor film BCF itself, the plug resistance of the plug PLG shown in FIG. 2 is likely to be higher than the plug resistance of the plug PLG shown in FIG. Considering the difference in crystal structure of the tantalum film between the plug PLG shown in FIG. 2 and the plug PLG shown in FIG. 3, the plug resistance of the plug PLG shown in FIG. will be smaller than In other words, when the tantalum nitride film is thick, the crystal structure of the tantalum film formed on the tantalum nitride film becomes an α-Ta structure with low resistivity. Therefore, it is desirable to increase the thickness of the tantalum nitride film formed under the tantalum film to such an extent that the crystal structure of the tantalum film has an α-Ta structure.

FIG. 4 is a graph showing the relationship between the specific resistance (resistivity) of a laminated film in which a tantalum film is formed on a tantalum nitride film and the film thickness of the tantalum nitride film. In FIG. 4, the horizontal axis indicates the film thickness of the tantalum nitride film (TaN film thickness), and the vertical axis indicates the resistivity of the laminated film. At this time, the graph shown in FIG. 4 is obtained by changing the thickness of the tantalum nitride film while the thickness of the tantalum film (Ta thickness) is fixed in the laminated film in which the tantalum film is formed on the tantalum nitride film. 10 shows the measurement results of the specific resistance of the laminated film in the case. As shown in FIG. 4, as the film thickness of the tantalum nitride film is increased, the specific resistance of the laminated film in which the tantalum film is formed on the tantalum nitride film decreases. Specifically, when the thickness of the tantalum nitride film is about 3 nm, the resistivity of the laminated film is about 210 μΩ·cm, and when the thickness of the tantalum nitride film is about 5 nm, the resistivity of the laminated film is 150 μΩ·cm. to some extent. Furthermore, when the thickness of the tantalum nitride film is about 6 nm, the specific resistance of the laminated film is about 90 μΩ·cm, and when the thickness of the tantalum nitride film is about 7 nm, the specific resistance of the laminated film is about 70 μΩ·cm. It can be seen that it decreases to In particular, it can be seen that the specific resistance of the laminated film changes significantly when the film thickness of the tantalum nitride film is about 5 nm. From this, for example, when the thickness of the tantalum nitride film is 5 nm or more, the crystal structure of the tantalum film formed on the tantalum nitride film becomes the α-Ta structure, and the specific resistance of the laminated film becomes low. can think. In other words, for example, when the film thickness of the tantalum nitride film is less than 5 nm, the crystal structure of the tantalum film formed on the tantalum nitride film becomes the β-Ta structure, and the specific resistance of the laminated film is considered to be low. be able to. Therefore, from the results shown in FIG. 4, from the viewpoint of reducing the plug resistance of the plug PLG, the thickness of the tantalum nitride film formed under the tantalum film should be such that the crystal structure of the tantalum film becomes the α-Ta structure. It can be considered that the fact that it is desirable to thicken the

As described above, from the viewpoint of reducing the plug resistance of the plug PLG, it is desirable to increase the film thickness of the tantalum nitride film formed under the tantalum film. When the pitch is about 60 nm or the half pitch is about 45 nm), if the thickness of the barrier conductor film BCF is increased, deterioration of embedding characteristics when the copper film CF is embedded in the wiring trench WD becomes apparent as a problem. For this reason, in the wiring L2, which is a fine wiring shown in FIG. 3, the film thickness of the barrier conductor film BCF formed on the inner wall of the connection hole CNT and the inner wall of the wiring groove WD is reduced from the viewpoint of improving the embedding characteristics. There is a need. However, in this case, as shown in FIG. 3, the thickness of the tantalum nitride film formed at the bottom of the plug PLG is reduced, and the crystal structure of the tantalum film formed on the tantalum nitride film is β- A Ta structure is formed. As a result, the plug resistance of the plug PLG connected to the wiring L2, which is a fine wiring shown in FIG. 3, increases.

However, the problem of increased plug resistance actually manifests itself, for example, in the plug PLG1A electrically connected to the wide wiring WL2 formed in the same layer as the narrow wiring NL2 shown in FIG. be. That is, the above-described problem becomes obvious because, focusing on the wide wiring WL2 and the narrow wiring NL2 formed in the same layer shown in FIG. The plug PLG1A is electrically connected to the wide wiring WL2 having a large wiring width and formed in the same layer as the narrow wiring NL2, instead of the plug PLG1B. This point will be described below.

FIG. 5 is a cross-sectional view showing an enlarged part of the multilayer wiring structure shown in FIG. In FIG. 5, for example, a barrier insulating film BIF1 is formed over the interlayer insulating film IL1 on which the wiring L1 that is the first layer wiring is formed, and an interlayer insulating film IL2 is formed over the barrier insulating film BIF1. . A wiring trench WD2A and a connection hole CNT1A are integrally formed in the barrier insulating film BIF1 and the interlayer insulating film IL2 so as to penetrate the barrier insulating film BIF1 and the interlayer insulating film IL2. Similarly, in the barrier insulating film BIF1 and the interlayer insulating film IL2, a wiring trench WD2B and a connection hole CNT1B are integrally formed so as to penetrate the barrier insulating film BIF1 and the interlayer insulating film IL2.

A barrier conductor film BCF is formed on the inner wall of the wiring trench WD2A and the inner wall of the contact hole CNT1A, and a copper film CF is formed on the barrier conductor film BCF so as to fill the wiring trench WD2A and the contact hole CNT1A. It is As a result, the plug PLG1A with the barrier conductor film BCF and the copper film CF embedded in the connection hole CNT1A and the wide wiring WL2 with the barrier conductor film BCF and the copper film CF embedded in the wiring trench WD2A are formed.

Similarly, a barrier conductor film BCF is formed on the inner wall of the wiring trench WD2B and the inner wall of the connection hole CNT1B. CF is formed. As a result, a plug PLG1B in which the barrier conductor film BCF and the copper film CF are embedded in the connection hole CNT1B, and a narrow wiring NL2 in which the barrier conductor film BCF and the copper film CF are embedded in the wiring groove WD2B are formed.

Thus, the wide wiring WL2 and the narrow wiring NL2 are formed in the same layer, and the plug PLG1A and the plug PLG1B are formed in the same layer. That is, as shown in FIG. 5, a wide wiring WL2 and a narrow wiring NL2 having different wiring widths are formed in the same layer. At this time, the wide wiring WL2 and the narrow wiring NL2 formed in the same layer are formed in the same process by, for example, the "damascene method". The narrow wiring NL2 is, for example, a fine wiring formed with a minimum processing dimension. There is a need to. Therefore, since the wide wiring WL2 formed in the same layer as the narrow wiring NL2 is also formed in the same process as the narrow wiring NL2, the thickness of the barrier conductor film BCF included in the wide wiring WL2 is inevitably will also become thinner. Therefore, the thickness of the tantalum nitride film TNF formed at the bottom of the plug PLG1A connected to the wide wiring WL2 is reduced, and the crystal structure of the tantalum film TF formed on the tantalum nitride film TNF is β- A Ta structure is formed. As a result, the plug resistance of the plug PLG1A connected to the wide wiring WL2 increases. Of course, the film thickness of the tantalum nitride film TNF formed at the bottom of the plug PLG1B connected to the narrow wiring NL2 is also reduced, and the crystal structure of the tantalum film TF formed on the tantalum nitride film TNF has a high resistivity β -Ta structure. As a result, the plug resistance also increases in the plug PLG1B connected to the narrow wiring NL2.

As described above, the wide wiring WL2 and the narrow wiring NL2 formed in the same layer are formed in the same process (“dual damascene method”). The rate is limited from the viewpoint of embedding characteristics. Therefore, both the plug PLG1A connected to the wide wiring WL2 and the plug PLG1B connected to the narrow wiring NL2 have high plug resistance. In this case, in particular, an increase in the plug resistance of the plug PLG1A connected to the wide wiring WL2 manifests itself as a problem that causes deterioration in the performance of the semiconductor device. The reason for this will be explained below.

The first reason is that, for example, the wide wiring WL2 is used as a power supply wiring for supplying a power supply potential. That is, the wide wiring WL2 is required to have a low wiring resistance because it is used as a power supply wiring through which a large current flows. Therefore, the plug PLG1A electrically connected to the wide wiring WL2 is also required to have a low plug resistance. This is because when the plug resistance of the plug PLG1A connected to the wide wiring WL2 increases, the voltage drop at the plug PLG1A increases when a large current flows through the wide wiring WL2, and the voltage drop from the power supply voltage becomes apparent. It is from.

On the other hand, in the plug PLG1B connected to the narrow wiring NL2, even if the plug resistance is increased to some extent, it is considered that the problem will not become so obvious. This is because the narrow wiring NL2 is used, for example, as a signal wiring for transmitting an electric signal, and does not pass a current as large as the power supply wiring. That is, due to the difference in function between the narrow wiring NL2 and the wide wiring WL2, the narrow wiring NL2 is considered to be less affected by the plug resistance than the wide wiring WL2. From the above, it is particularly important to increase the plug resistance in the plug PLG1A connected to the wide wiring WL2 from the viewpoint of suppressing the deterioration of the performance of the semiconductor device.

Next, the second reason will be explained. As shown in FIG. 5, the barrier conductor film BCF at the bottom of the plug PLG1A connected to the wide wiring WL2 is thicker than the barrier conductor film BCF at the bottom of the plug PLG1B connected to the narrow wiring NL2. thicken. That is, even if the barrier conductor film BCF is formed in the same process, the thickness of the barrier conductor film BCF formed at the bottom of the plug PLG1A is equal to the thickness of the barrier conductor film BCF formed at the bottom of the plug PLG1B. It will be thicker than

This phenomenon can be considered qualitatively, for example, as follows. For example, the barrier conductor film BCF is formed by using a sputtering method. In the sputtering method, for example, a film is formed by causing argon to collide with a target made of a film-forming material, so that target atoms ejected from the target are attached to the semiconductor substrate. Here, as shown in FIG. 6, consider forming a barrier conductor film on the bottom surface of the connection hole CNT1A and the bottom surface of the connection hole CNT1B by sputtering in the same step. In this case, the target atoms adhering to the bottom of the connection hole CNT1A can be considered to be target atoms coming in from directions within the range of the angle θ1 shown in FIG. On the other hand, the target atoms adhering to the bottom of the connection hole CNT1B can be considered to be the target atoms coming in from the direction within the range of the angle θ2 shown in FIG. Here, as shown in FIG. 6, considering that the width of the wiring groove WD2A formed over the connection hole CNT1A is larger than the width of the wiring groove WD2B formed over the connection hole CNT1B, the angle θ1 is greater than the angle θ2. This means that the number of target atoms attached to the bottom of connection hole CNT1A is greater than the number of target atoms attached to the bottom of connection hole CNT1B. As a result, the thickness of the barrier conductor film formed at the bottom of the connection hole CNT1A becomes thicker than the thickness of the barrier conductor film formed at the bottom of the connection hole CNT1B. From the above, as shown in FIG. 5, the barrier conductor film BCF formed at the bottom of the plug PLG1A is thicker than the barrier conductor film BCF formed at the bottom of the plug PLG1B. .

Therefore, since the barrier conductor film BCF formed at the bottom of the plug PLG1B connected to the narrow wiring NL2 is thin, the tantalum film TF formed at the bottom of the plug PLG1B connected to the narrow wiring NL2 has a β-Ta structure with high resistivity. On the other hand, the barrier conductor film BCF formed at the bottom of the plug PLG1A connected to the wide wiring WL2 is thicker than the barrier conductor film BCF formed at the bottom of the plug PLG1B. The film thickness of the tantalum nitride film TNF is not formed so thick that the crystal structure of the film TF becomes the α-Ta structure. That is, even considering that the barrier conductor film BCF formed at the bottom of the plug PLG1A is formed to be thicker than the barrier conductor film BCF formed at the bottom of the plug PLG1B, the conventional growth method is not sufficient. As for the film conditions, the film thickness of the tantalum nitride film TNF formed on the bottom of the plug PLG1A is considered to be less than 5 nm. From this, it is considered that the crystalline structure of the tantalum film TF formed at the bottom of the plug PLG1A connected to the wide wiring WL2 is also a β-Ta structure with high resistivity.

Therefore, the crystal structure of the tantalum film TF formed on the bottom of the plug PLG1A and the crystal structure of the tantalum film TF formed on the bottom of the plug PLG1B both have the same β-Ta structure. Assuming this, considering that the barrier conductor film BCF formed at the bottom of the plug PLG1A is thicker than the barrier conductor film BCF formed at the bottom of the plug PLG1B, wide wiring WL2 It can be said that the plug resistance of the plug PLG1A connected to .

FIG. 7 is a graph showing measurement results of the plug resistance of the plug PLG1A connected to the wide wiring WL2 and the plug resistance of the plug PLG1B connected to the narrow wiring NL2 in the prior art. In FIG. 7, the graph indicated by "Wide" indicates the plug resistance of the plug PLG1A connected to the wide wiring WL2, and the graph indicated by "Narrow" is connected to the narrow wiring NL2. The plug resistance of the plug PLG1B is shown. As shown in FIG. 7, it can be seen that the plug resistance of the plug PLG1A connected to the wide wiring WL2 is higher than the plug resistance of the plug PLG1B connected to the narrow wiring NL2.

From the above, the increase in the plug resistance in the plug PLG1A connected to the wide wiring WL2 becomes apparent as a problem. That is, the wide wiring WL2 is used as a power supply wiring through which a large current flows, and the plug resistance of the plug PLG1A connected to the wide wiring WL2 is greater than the plug resistance of the plug PLG1B connected to the narrow wiring NL2. Due to the synergistic factor, the increase in the plug resistance in the plug PLG1A connected to the wide wiring WL2 becomes apparent as a problem.

Therefore, in the present embodiment, in a semiconductor device in which a wide wiring and a narrow wiring are formed in the same layer, measures are taken to suppress an increase in plug resistance in a plug connected to a wide wiring. The technical idea of this embodiment with this ingenuity will be described below.

<Structural features of the embodiment>
FIG. 8 is a cross-sectional view showing an enlarged part of the multilayer wiring structure according to the present embodiment. In FIG. 8, for example, a barrier insulating film BIF1 is formed over the interlayer insulating film IL1 on which the wiring L1 that is the first layer wiring is formed, and an interlayer insulating film IL2 is formed over the barrier insulating film BIF1. . A wiring trench WD2A and a connection hole CNT1A are integrally formed in the barrier insulating film BIF1 and the interlayer insulating film IL2 so as to penetrate the barrier insulating film BIF1 and the interlayer insulating film IL2. Similarly, in the barrier insulating film BIF1 and the interlayer insulating film IL2, a wiring trench WD2B and a connection hole CNT1B are integrally formed so as to penetrate the barrier insulating film BIF1 and the interlayer insulating film IL2.

A barrier conductor film BCF is formed on the inner wall of the wiring trench WD2A and the inner wall of the contact hole CNT1A, and a copper film CF is formed on the barrier conductor film BCF so as to fill the wiring trench WD2A and the contact hole CNT1A. It is As a result, the plug PLG1A with the barrier conductor film BCF and the copper film CF embedded in the connection hole CNT1A and the wide wiring WL2 with the barrier conductor film BCF and the copper film CF embedded in the wiring trench WD2A are formed.

Similarly, a barrier conductor film BCF is formed on the inner wall of the wiring trench WD2B and the inner wall of the connection hole CNT1B. CF is formed. As a result, a plug PLG1B in which the barrier conductor film BCF and the copper film CF are embedded in the connection hole CNT1B, and a narrow wiring NL2 in which the barrier conductor film BCF and the copper film CF are embedded in the wiring groove WD2B are formed.

As described above, the semiconductor device according to the present embodiment includes a wide wiring WL2 containing copper as a main component, a narrow wiring NL2 containing copper as a main component, and a wide wiring WL2 formed in the same layer (same wiring layer). A plug PLG1A mainly composed of copper arranged in a layer below WL2 and connected to the wide wiring WL2, and a plug PLG1B mainly composed of copper arranged in a layer below the narrow wiring NL2 and connected to the narrow wiring NL2. and Each of the plug PLG1A and the plug PLG1B includes a barrier conductor film BCF. At this time, the wiring width of the wide wiring WL2 is larger than that of the narrow wiring NL2, while the plug PLG1A and the plug PLG1B have the same size and are formed in the same layer. Then, for example, the barrier conductor film BCF is composed of a tantalum nitride film TNF and a tantalum film TF formed on the tantalum nitride film TNF.

Here, the characteristic point of this embodiment is that, for example, as shown in FIG. 8, the thickness of the barrier conductor film BCF formed at the bottom of the plug PLG1A connected to the wide wiring WL2 is equal to that of the narrow wiring NL2. is thicker than the barrier conductor film BCF formed at the bottom of the plug PLG1B connected to the . More specifically, the thickness of the tantalum nitride film TNF formed at the bottom of the plug PLG1A is thicker than the thickness of the tantalum nitride film TNF formed at the bottom of the plug PLG1B. The thickness of the tantalum nitride film TNF formed on the bottom of the PLG 1A is so thick that the crystalline structure of the tantalum film TF formed on the tantalum nitride film TNF becomes the α-Ta structure. Specifically, the thickness of the tantalum nitride film TNF formed at the bottom of the plug PLG1A connected to the wide wiring WL2 is 5 nm or more and 10 nm or less. On the other hand, the thickness of the tantalum nitride film TNF formed at the bottom of the plug PLG1B connected to the narrow wire NL2 is greater than 0 nm and less than or equal to 3 nm. In this case, the crystal structure of the tantalum film TF formed on the tantalum nitride film TNF at the bottom of the plug PLG1A connected to the wide wiring WL2 is the α-Ta structure with low resistivity. On the other hand, the crystal structure of the tantalum film TF formed on the tantalum nitride film TNF at the bottom of the plug PLG1B connected to the narrow wire NL2 is a β-Ta structure with high resistivity. Therefore, in the present embodiment, the resistivity of the tantalum film TF formed on the bottom of the plug PLG1A is lower than that of the tantalum film TF formed on the bottom of the plug PLG1B.

Specifically, FIG. 9 is a graph showing measurement results of the plug resistance of the plug PLG1A connected to the wide wiring WL2 and the plug resistance of the plug PLG1B connected to the narrow wiring NL2 in the present embodiment. In FIG. 9, the graph indicated by "Wide" indicates the plug resistance of the plug PLG1A connected to the wide wiring WL2, and the graph indicated by "Narrow" is connected to the narrow wiring NL2. The plug resistance of the plug PLG1B is shown. As shown in FIG. 9, it can be seen that the plug resistance of the plug PLG1A connected to the wide wiring WL2 is lower than the plug resistance of the plug PLG1B connected to the narrow wiring NL2.

Thus, according to the present embodiment, the resistance value (plug resistance) of the plug PLG1A connected to the wide wiring WL2 is lower than the resistance value (plug resistance) of the plug PLG1B connected to the narrow wiring NL2. can do. Therefore, according to the present embodiment, for example, an increase in the plug resistance of the plug PLG1A connected to the wide wiring WL2 used as the power supply wiring can be suppressed, so that the performance of the semiconductor device can be improved. .

On the other hand, according to the present embodiment, the thickness of the barrier conductor film BCF formed on the inner wall of the wiring trench WD2B can be reduced, so that the narrow wiring NL2 formed with a processing accuracy equivalent to the minimum processing dimension can be formed. It is possible to improve the embedding characteristics for forming.

From the above, in the present embodiment, for example, the wide wiring WL2 used as a power supply wiring through which a large current flows and the narrow wiring NL2 formed with processing accuracy of about the minimum processing dimension are formed in the same layer. In the semiconductor device, it is possible to obtain a remarkable effect that the embedding characteristics for forming the narrow wiring NL2, which is a fine wiring, can be improved while reducing the plug resistance of the plug PLG1A connected to the wide wiring WL2. You can.

<Method for manufacturing a semiconductor device>
The semiconductor device according to the present embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings. In the manufacturing process shown below, a multilayer wiring structure is formed by a so-called "dual damascene method" after forming a wiring L1 in an interlayer insulating film formed above a semiconductor substrate by a "single damascene method" as an example. I will list and explain.

First, as shown in FIG. 10, the barrier insulating film BIF1 is formed over the interlayer insulating film IL1 in which the wiring L1 is formed, and the interlayer insulating film IL2 is formed over the barrier insulating film BIF1. The barrier insulating film BIF1 is formed of, for example, any one of a stacked film of a SiCN film and a SiCO film provided on the SiCN film, a SiC film, or a SiN film. Vapor Deposition) method. Also, the interlayer insulating film IL2 is formed of, for example, a low dielectric constant film having a dielectric constant lower than that of a silicon oxide film. Specifically, the interlayer insulating film IL2 can be formed of, for example, a SiOC film formed by a CVD method, or a low dielectric constant film such as an HSQ film and an MSQ film formed by a coating method.

Next, as shown in FIG. 11, by using a photolithographic technique and an etching technique, the integrated wiring trench WD2A and the contact hole CNT1A are integrated so as to penetrate the barrier insulating film BIF1 and the interlayer insulating film IL2. Then, a widened wiring groove WD2B and a connection hole CNT1B are formed. At this time, the surface of the wiring L1 formed so as to be embedded in the interlayer insulating film IL1 is exposed at the bottoms of the connection holes CNT1A and CNT1B. In this step, as shown in FIG. 11, the width of the wiring groove WD2A is formed larger than the width of the wiring groove WD2B, and the size of the connection hole CNT1A and the size of the connection hole CNT1B are formed to be the same size. In other words, the wiring trench WD2B is formed with an accuracy approximately equal to the minimum processing dimension, for example, and the wiring trench WD2A is formed with an accuracy lower than the minimum processing dimension, for example.

Subsequently, as shown in FIG. 12, the interlayer insulating film IL2 including the inner wall of the wiring trench WD2A and the inner wall of the contact hole CNT1A, and the inner wall of the wiring trench WD2B and the inner wall of the contact hole CNT1B are subjected to sputtering, for example. By using it, a tantalum nitride film TNF is formed. At this time, as shown in FIG. 12, the tantalum nitride film TNF formed on the bottom surface of the connection hole CNT1A is formed thicker than the tantalum nitride film TNF formed on the bottom surface of the connection hole CNT1B. . Specifically, in the present embodiment, the film thickness of the tantalum nitride film TNF formed on the bottom surface of the connection hole CNT1A is, for example, 5 nm or more and 10 nm or less by devising film formation conditions in the sputtering method, and , the film thickness of the tantalum nitride film TNF formed on the bottom surface of the connection hole CNT1B is set to be greater than 0 nm and 3 nm or less. The details of film formation conditions in the sputtering method for forming this tantalum nitride film TNF will be described later (first feature of the manufacturing method).

Then, as shown in FIG. 13, a tantalum film TF is formed on the tantalum nitride film TNF by using, for example, a sputtering method. At this time, since the film thickness of the tantalum nitride film TNF is 5 nm or more and 10 nm or less at the bottom surface of the connection hole CNT1A, the crystal structure of the tantalum film TF formed on the tantalum nitride film TNF is α- A Ta structure is obtained. On the other hand, at the bottom surface of the connection hole CNT1B, the film thickness of the tantalum nitride film TNF is greater than 0 nm and equal to or less than 3 nm. -Ta structure. Here, in the present embodiment, the film formation conditions in the sputtering method for forming the tantalum film TF are also devised. The crystal structure of the film TF tends to be the α-Ta structure. The details of film forming conditions in the sputtering method for forming this tantalum film TF will be described later (second feature of the manufacturing method).

As described above, the tantalum nitride film TNF and the tantalum film TF are formed on the interlayer insulating film IL2 including the inner wall of the wiring trench WD2A and the inner wall of the contact hole CNT1A, and the inner wall of the wiring trench WD2B and the inner wall of the contact hole CNT1B. It is possible to form a barrier conductor film BCF having a

Next, as shown in FIG. 14, a seed film made of, for example, a thin copper film is formed on the barrier conductor film BCF including the inside of the wiring trench WD2A and the contact hole CNT1A, and the inside of the wiring trench WD2B and the contact hole CNT1B. Form SL. The seed film SL can be formed, for example, by using a sputtering method, but is not limited to this, and can also be formed by, for example, a CVD method, an ALD (Atomic Layer Deposition) method, or a plating method. .

Then, as shown in FIG. 15, for example, a copper film CF is formed by electroplating using the seed film SL as an electrode. This copper film CF is formed so as to fill the insides of the wiring trench WD2A and the contact hole CNT1A, and the insides of the wiring trench WD2B and the contact hole CNT1B. At this time, in the present embodiment, the barrier conductor film BCF formed on the inner wall of the wiring trench WD2B and the inner wall of the connection hole CNT1B, which are processed with a processing accuracy of about the minimum processing dimension, remains thin. It is possible to improve the embedding characteristics when embedding the copper film CF in the trench WD2B.

This copper film CF is formed of, for example, a film containing copper as its main component. Specifically, copper (Cu) or a copper alloy (copper (Cu) and aluminum (Al), magnesium (Mg), titanium (Ti), manganese (Mn), iron (Fe), zinc (Zn), zirconium ( Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), palladium (Pd), silver (Ag), gold (Au), In (indium), lanthanide metals, alloys such as actinide metals) It is formed. Moreover, the method of forming the copper film CF is not limited to the electroplating method, and may be, for example, the sputtering method or the CVD method.

Subsequently, as shown in FIG. 8, the unnecessary barrier conductor film BCF and copper film CF formed over the interlayer insulating film IL2 are removed by CMP (Chemical Mechanical Polishing). On the other hand, the copper film CF and the barrier conductor film BCF are left inside the wiring trench WD2A and the connection hole CNT1A, and the copper film CF and the barrier conductor film BCF are left inside the wiring trench WD2B and inside the connection hole CNT1B. Thus, according to the present embodiment, as shown in FIG. 8, a wide wiring WL2 in which the barrier conductor film BCF and the copper film CF are embedded in the wiring groove WD2A, and a barrier conductor film BCF and a copper film CF in the connection hole CNT1A are formed. can be formed with a plug PLG1A in which Similarly, according to the present embodiment, the narrow wiring NL2 in which the barrier conductor film BCF and the copper film CF are embedded in the wiring groove WD2B and the plug PLG1B in which the barrier conductor film BCF and the copper film CF are embedded in the connection hole CNT1B are provided. can be formed. Thus, in the present embodiment, the copper film CF included in the wide wiring WL2 (first copper wiring), the copper film CF included in the plug PLG1A (first copper plug), the narrow wiring NL2 (second The copper film CF included in the copper wiring) and the copper film CF included in the plug PLG1B (second copper plug) are integrally formed.

Subsequent steps will be omitted because they are substantially the same steps as those described above. As described above, the semiconductor device according to the present embodiment can be manufactured.

<Features of Manufacturing Method in Embodiment>
In the semiconductor device according to the present embodiment, the plug resistance (resistance value) of the plug PLG1A is equal to is lower than the plug resistance (resistance value) of Specifically, the resistivity of the tantalum film TF formed on the bottom of the plug PLG1A is lower than the resistivity of the tantalum film TF formed on the bottom of the plug PLG1B. That is, in the present embodiment, the crystal structure of the tantalum film TF formed at the bottom of the plug PLG1A is an α-Ta structure with low resistivity, and the crystal structure of the tantalum film TF formed at the bottom of the plug PLG1B is The structure is a β-Ta structure. Therefore, according to the manufacturing method of the present embodiment, for example, it is possible to suppress an increase in the plug resistance of the plug PLG1A connected to the wide wiring WL2 used as the power supply wiring, thereby improving the performance of the semiconductor device. be able to.

On the other hand, according to the manufacturing method of the semiconductor device in the present embodiment, the thickness of the barrier conductor film BCF formed on the inner wall of the wiring groove WD2B can be reduced, so that the barrier conductor film BCF can be formed with a processing accuracy equivalent to the minimum processing dimension. Therefore, it is possible to improve the embedding characteristics for forming the narrow wiring NL2. That is, by adopting the method of manufacturing a semiconductor device according to the present embodiment, for example, a wide wiring WL2 used as a power supply wiring through which a large current flows, and a narrow wiring NL2 formed with a processing accuracy of about the minimum processing dimension. are formed in the same layer, it is possible to reduce the plug resistance of the plug PLG1A connected to the wide wiring WL2 and improve the embedding characteristics for forming the narrow wiring NL2, which is a fine wiring. A remarkable effect can be obtained.

Below, the 1st characteristic point on a manufacturing method and the 2nd characteristic point on a manufacturing method are demonstrated. The first characteristic point and the second characteristic point of the manufacturing method in the present embodiment are realized, for example, in the tantalum nitride film forming process and the tantalum film forming process shown in FIGS. 12 and 13 . That is, the first characteristic point and the second characteristic point of the manufacturing method in the present embodiment are the inner wall of the wiring trench WD2A and the inner wall of the contact hole CNT1A, and the inner wall of the wiring trench WD2B and the inner wall of the contact hole CNT1B. It is realized by a step of forming a barrier conductor film BCF composed of a tantalum nitride film TNF and a tantalum film TF on the insulating film IL2. These steps are film forming steps by a sputtering method, and the first characteristic point and the second characteristic point in the manufacturing method relate to the film forming conditions in the sputtering method.

Therefore, first, the configuration of a sputtering apparatus for carrying out the film forming process by the sputtering method and a simple film forming operation will be described.

FIG. 16 is a diagram showing a schematic configuration of a sputtering apparatus used in this embodiment. In FIG. 16, the sputtering apparatus has a processing chamber CB, a stage ST is arranged inside the processing chamber CB, and a semiconductor substrate 1S is mounted on the stage ST. Specifically, the stage ST is provided with an electrostatic chuck (not shown), and the semiconductor substrate 1S is held by this electrostatic chuck. A center tap (not shown) is provided at the center of the electrostatic chuck, and the center tap is configured to come into direct contact with the semiconductor substrate. The center tap is electrically connected to a bias power supply BPS, and the bias power supply BPS applies a substrate pull-in bias to the semiconductor substrate 1S.

On the other hand, in the processing chamber CB, a target TAG made of a film forming material is arranged at a position facing the semiconductor substrate 1S placed on the stage. The target TAG is electrically connected to a DC power supply DCPS provided outside the processing chamber CB, and power (target DC power) is supplied from the DC power supply DCPS to the target TAG. Further, argon gas (Ar gas) is introduced into the processing chamber CB.

The sputtering apparatus used in this embodiment is configured as described above, and the film forming operation thereof will be briefly described below. In FIG. 16, first, the semiconductor substrate 1S is placed on the stage ST placed inside the processing chamber CB. Thereafter, argon gas (Ar gas) is introduced into the processing chamber CB, target DC power is supplied from the DC power supply DCPS to the target TAG, and a substrate pull-in bias is applied to the semiconductor substrate 1S from the bias power supply BPS. Then, a high electric field applied between the semiconductor substrate 1S and the target TAG initiates plasma discharge in the processing chamber CB. As a result, the argon gas introduced into the processing chamber CB is ionized, and the high-energy argon ions accelerated by the high electric field collide with the target TAG. As a result, target atoms fly out of the target TAG due to the recoil of the argon ions colliding with the target TAG, and the flung out target atoms adhere to the semiconductor substrate 1S. Thereby, a film is formed on the semiconductor substrate 1S. As described above, the film forming process is performed by the sputtering apparatus.

Specifically, in the method of manufacturing a semiconductor device according to the present embodiment, as shown in FIG. 12, the inner wall of the wiring trench WD2A and the inner wall of the contact hole CNT1A, the inner wall of the wiring trench WD2B and the inner wall of the contact hole CNT1B, A tantalum nitride film TNF is formed over the interlayer insulating film IL2 including, for example, a sputtering method using the sputtering apparatus described above. The process of forming this tantalum nitride film is performed by a sputtering method using tantalum as a target TAG and introducing nitrogen gas into the processing chamber CB. There is a first feature point.

FIG. 17 is a table showing film formation conditions in the film formation process of the tantalum nitride film. In FIG. 17, the conventional conditions in the deposition process of the tantalum nitride film are a target DC power of 20 kW, a substrate pull-in bias power of 650 W, and a deposition time of 4.6 seconds. On the other hand, the conditions of the present embodiment in the film forming process of the tantalum nitride film are a target DC power of 20 kW, a substrate pull-in bias power of 650 W, and a film forming time of 6.9 seconds. Therefore, the first feature of the manufacturing method in this embodiment is that the film formation time is increased from 4.6 seconds to 6.9 seconds. In other words, the first feature of the manufacturing method in this embodiment is that the film formation time is lengthened to increase the film thickness of the tantalum nitride film. Specifically, in the present embodiment, the film formation time is lengthened so that the film thickness of the tantalum nitride film TNF formed at the bottom of the connection hole CNT1A shown in FIG. 12 is within the range of 5 nm or more and 10 nm or less. . That is, in the film formation time under the conventional conditions, the film thickness of the tantalum nitride film TNF formed at the bottom of the connection hole CNT1A is less than 5 nm. This results in a β-Ta structure with high resistivity. On the other hand, under the film forming conditions of the present embodiment, the film forming time is longer than that under the conventional conditions, so that the thickness of the tantalum nitride film TNF formed at the bottom of the connection hole CNT1A is 5 nm or more and 10 nm or less. Become. Thus, according to the present embodiment, the crystal structure of the tantalum film TF formed on the tantalum nitride film TNF can be the α-Ta structure. In other words, when the film thickness of the tantalum nitride film TNF formed at the bottom of the connection hole CNT1A is 5 nm or more and 10 nm or less, the tantalum film TF formed on the tantalum nitride film TNF depends on the crystal structure of the tantalum nitride film TNF. The crystal structure of is the α-Ta structure.

Here, lengthening the film forming time in the step of forming the tantalum nitride film TNF means that the film thickness of the tantalum nitride film TNF formed at the bottom of the connection hole CNT1A becomes thicker than the film thickness under the conventional conditions. This also means that the thickness of the tantalum nitride film TNF formed at the bottom of the connection hole CNT1B is also increased. In this case, it is conceivable that the embedding characteristics for forming the narrow wiring NL2 are degraded. is 3 nm or less, it is considered that there is little effect on the embedding characteristics for forming the narrow wiring NL2.

Regarding this point, from the viewpoint of improving the embedding characteristics for forming the narrow wiring NL2, for example, while the film formation time in the film formation process of the tantalum nitride film TNF is lengthened, the This can be dealt with by shortening the film forming time in the film forming process of the tantalum film TF. In other words, if the thickness of the tantalum film TF is reduced by the thickness of the tantalum nitride film TNF, the thickness of the barrier conductor film BCF, which is the sum of the tantalum nitride film TNF and the tantalum film TF, does not change. Therefore, it is possible to suppress the deterioration of the embedding characteristics for forming the narrow wiring NL2. Specifically, for example, when the film thickness of the tantalum nitride film TNF is increased by 1 nm, the film formation time in the film formation process of the tantalum film TF may be shortened so that the film thickness of the tantalum film TF is reduced by 1 nm. Just do it. In this case, the thickness of the tantalum film TF formed on the tantalum nitride film TNF is further reduced not only at the bottom of the connection hole CNT1B and the inner wall of the wiring trench WD2B, but also at the bottom of the connection hole CNT1A. Therefore, the plug PLG1A connected to the wide wiring WL2 is connected to the wide wiring WL2 due to the fact that the crystal structure of the tantalum film TF becomes the α-Ta structure with low resistivity and the fact that the film thickness of the tantalum film TF itself becomes thin. of plug resistance can be reduced. That is, from the viewpoint of simultaneously reducing the plug resistance of the plug PLG1A connected to the wide wiring WL2 and improving the embedding characteristics for forming the narrow wiring NL2, which is a fine wiring, at a high level, the tantalum nitride film TNF is used. It is desirable to lengthen the film formation time in the film formation process and shorten the film formation time in the film formation process of the tantalum film TF formed on the tantalum nitride film TNF.

Next, in the method of manufacturing a semiconductor device according to the present embodiment, as shown in FIG. 13, a tantalum film TF is formed on the tantalum nitride film TNF by, for example, a sputtering method using the sputtering apparatus described above. After nitrogen gas is exhausted from the processing chamber CB, the tantalum film forming process is carried out by a sputtering method using tantalum as a target and applying a substrate pull-in bias to the semiconductor substrate. There is a second characteristic point in the manufacturing method in this embodiment.

FIG. 18 is a table showing film formation conditions in the film formation process of the tantalum film. In FIG. 18, the conventional conditions in the tantalum film formation process are a target DC power of 20 kW, a substrate pull-in bias power of 250 W, and a semiconductor substrate potential of -255V. On the other hand, the conditions of the present embodiment in the tantalum film deposition process are a target DC power of 20 kW, a substrate pull-in bias power of 400 W, and a potential of the semiconductor substrate 1S of −350 V. FIG. Therefore, the second feature of the manufacturing method in this embodiment is that the potential of the semiconductor substrate 1S is set from -255V to -350V. In other words, the second feature of the manufacturing method according to the present embodiment is that the absolute value of the potential of the semiconductor substrate 1S is made larger than the conventional condition. Thus, according to the present embodiment, the crystal structure of the tantalum film TF formed on the tantalum nitride film TNF can be easily changed to the α-Ta structure. For example, increasing the absolute value of the potential of the semiconductor substrate 1S means that tantalum atoms ejected from the target TAG are accelerated and attached onto the tantalum nitride film TNF. In this case, since the kinetic energy of the tantalum atoms is large, even after the tantalum atoms adhere to the tantalum nitride film TNF, the tantalum atoms tend to move so as to reflect the crystal structure of the tantalum nitride film. As a result, according to the present embodiment, the crystal structure of the tantalum film TF formed on the tantalum nitride film TNF tends to be the α-Ta structure with low resistivity.

Therefore, from the viewpoint of making the crystal structure of the tantalum film TF formed on the tantalum nitride film TNF an α-Ta structure with low resistivity, it is desirable to increase the absolute value of the potential of the semiconductor substrate 1S. It is desirable to apply the substrate pull-in bias so that the potential of the substrate 1S is in the range of -350V to -800V. This condition can be realized, for example, by applying a substrate pull-in bias with a power of 400 W or more and 1000 W or less to the semiconductor substrate 1S. However, since the electric power for setting the potential of the semiconductor substrate 1S within the range of −350 V to −800 V is considered to vary depending on the type of sputtering apparatus, the semiconductor substrate 1S is ultimately The electric power for applying the substrate pull-in bias may be supplied so that the potential of is within the range of -350V to -800V.

As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, the synergistic effect of the first characteristic point of the manufacturing method and the second characteristic point of the manufacturing method allows the plug PLG1A to be connected to the wide wiring WL2. It is possible to achieve both a reduction in plug resistance and an improvement in embedding characteristics for forming the narrow wiring NL2, which is a fine wiring. From the viewpoint of both reducing the plug resistance of the plug PLG1A connected to the wide wiring WL2 and improving the embedding characteristics for forming the narrow wiring NL2, which is a fine wiring, the first feature of the manufacturing method described above is considered. Although it is desirable to combine the point and the second characteristic point on the manufacturing method, it is not limited to this. may be adopted. In particular, the first characteristic point of the manufacturing method relates to the process of forming the tantalum nitride film, and the second characteristic point of the manufacturing method relates to the process of forming the tantalum film. be able to.

<Modification>
Next, a modified example of this embodiment will be described. This modification is a technical concept of making the introduction timing of the nitrogen gas introduced into the processing chamber CB of the sputtering apparatus earlier than in the prior art in the step of forming the tantalum nitride film TNF shown in FIG.

FIG. 19 is a diagram for explaining the introduction timing of nitrogen gas in the process of forming the tantalum nitride film TNF in this modification. In FIG. 19, in the sputtering apparatus, first, after performing an ignition step of starting plasma discharge of argon gas, a step of forming a tantalum nitride film TNF (a step of forming a TaN film) is performed, and then a step of forming a tantalum film TF is performed. A film process (Ta film forming process) is continuously performed. At this time, as shown in FIG. 19, plasma discharge is started by increasing the target DC power stepwise in the ignition process. The target DC power is kept constant throughout the TaN film formation process and the Ta film formation process. On the other hand, in FIG. 19, in the prior art, nitrogen gas is introduced after the ignition process is completed. In practice, sputtering occurs during the process of stepwise increasing the target DC power in the ignition process. Therefore, in the prior art, a tantalum film is formed in the ignition step, and then, when nitrogen gas is introduced in the TaN film forming step, formation of the tantalum nitride film begins. In contrast, as shown in FIG. 19, in this modified example, nitrogen gas is introduced into the processing chamber CB at the stage of starting the ignition process (the process prior to the TaN film forming process). Thus, according to this modification, the tantalum nitride film can be formed from the ignition step to the TaN film forming step. That is, in this modification, since nitrogen gas is introduced into the processing chamber CB at the stage of starting the ignition process, the tantalum nitride film can be formed even at the stage of the ignition process. As a result, according to this modified example, it is possible to substantially lengthen the deposition time of the tantalum nitride film TNF without lengthening the deposition time in the TaN deposition step. 1 feature point can be realized. Therefore, according to this modification, the thickness of the tantalum nitride film TNF formed at the bottom of the connection hole CNT1A can be set to 5 nm or more and 10 nm or less without lowering the throughput of the sputtering apparatus. As a result, according to this modification, the crystal structure of the tantalum film TF formed on the tantalum nitride film TNF can be the α-Ta structure.

<Effect of Embodiment>
According to this embodiment (including modifications), for example, the following effects can be obtained.

(1) According to the present embodiment, for example, a wide wiring WL2 used as a power supply wiring through which a large current flows and a narrow wiring NL2 formed with a processing accuracy of about the minimum processing dimension are formed in the same layer. In the semiconductor device, it is possible to obtain a remarkable effect that the embedding characteristics for forming the narrow wiring NL2, which is a fine wiring, can be improved while reducing the plug resistance of the plug PLG1A connected to the wide wiring WL2. can.

(2) According to the present embodiment, the plugs (PLG1A, PLG1B) are connected to the wide wiring WL2 and the narrow wiring NL2 having different wiring widths formed in the same wiring layer by, for example, one sputtering process. A tantalum nitride film TNF having a different film thickness can be formed on the bottom of the . Therefore, according to the present embodiment, the tantalum nitride film formed at the bottom of the plug PLG1A connected to the wide wiring WL2 and the tantalum nitride film formed at the bottom of the plug PLG1A connected to the narrow wiring NL2 are separated. Since there is no need to carry out the sputtering process in separate sputtering processes, the sputtering process for forming tantalum nitride films having different thicknesses can be simplified, thereby reducing the manufacturing cost of the semiconductor device.

Although the invention made by the present inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and can be variously modified without departing from the gist of the invention. Needless to say.

1S Semiconductor substrate BCF Barrier conductor film BIF1 Barrier insulating film BIF2 Barrier insulating film BIF3 Barrier insulating film BIF4 Barrier insulating film BPS Bias power supply CB Processing chamber CF Copper film CIL Contact interlayer insulating film CNT Connection hole CNT1A Connection hole CNT1B Connection hole DCPS DC power supply IL1 Interlayer insulating film IL2 Interlayer insulating film IL3 Interlayer insulating film L1 Wiring L2 Wiring L3 Wiring L4 Wiring L5 Wiring NL2 Narrow wiring PAS Surface protection film PD Pad PLG Plug PLG0 Plug PLG1A Plug PLG1B Plug PLG2 Plug PLG3 Plug PLG4 Plug Q MISFET
SL seed film ST stage TAG target TF tantalum film TNF tantalum nitride film WD wiring groove WD2A wiring groove WD2B wiring groove WL2 wide wiring

Claims (18)

a semiconductor substrate on which a semiconductor element is formed;
a contact interlayer insulating film formed on the semiconductor substrate and having a first connection hole reaching the semiconductor substrate and a second connection hole reaching the semiconductor substrate;
a first plug formed to fill the first connection hole;
a second plug formed to fill the second connection hole;
A first interlayer insulating film having a first wiring trench with the first plug exposed at its bottom and a second wiring trench with the second plug exposed at its bottom, and formed on the contact interlayer insulating film. and,
a first wiring formed to fill the first wiring trench;
a second wiring formed to fill the second wiring trench;
a third connection hole, a third wiring groove integrally formed with the third connection hole, a fourth connection hole, and a fourth wiring groove integrally formed with the fourth connection hole; a second interlayer insulating film formed on the first interlayer insulating film;
a first barrier conductor film formed to cover the inner wall of the third connection hole, the inner wall of the third wiring groove, and the first surface of the first wiring exposed in the third connection hole;
a second barrier conductor film formed to cover the inner wall of the fourth connection hole, the inner wall of the fourth wiring groove, and the second surface of the second wiring exposed in the fourth connection hole;
a first copper film formed on the first barrier conductor film so as to fill the third connection hole and the third wiring trench;
a second copper film formed on the second barrier conductor film so as to fill the fourth connection hole and the fourth wiring trench;
including
The width of the third wiring groove is larger than the width of the fourth wiring groove,
The size of the third connection hole is the same as the size of the fourth connection hole,
the first barrier conductor film has a first tantalum nitride film and a first tantalum film formed on the first tantalum nitride film;
the second barrier conductor film includes a second tantalum nitride film and a second tantalum film formed on the second tantalum nitride film;
a first portion of the first tantalum nitride film formed on the first surface of the first wiring has a first film thickness of 6 nm or more;
a second portion of the second tantalum nitride film formed on the second surface of the second wiring has a second film thickness of greater than 0 nm and equal to or less than 3 nm ;
A semiconductor device according to claim 1, wherein the wiring having the second barrier conductor film and the second copper film constitutes wiring having a half pitch of 60 nm or less. The semiconductor device according to claim 1,
In the first tantalum film, the crystal structure of the third portion formed on the first portion of the first tantalum nitride film includes an α-Ta structure,
In the semiconductor device, the crystal structure of the fourth portion of the second tantalum film formed on the second portion of the second tantalum nitride film includes a β-Ta structure. The semiconductor device according to claim 1,
The semiconductor device, wherein the first film thickness is 6 nm or more and 10 nm or less. In the semiconductor device according to any one of claims 1 to 3 ,
The semiconductor device according to claim 1, wherein the first interlayer insulating film is composed of a SiOC film, an HSQ film, or an MSQ film. In the semiconductor device according to any one of claims 1 to 4 ,
the wiring having the first barrier conductor film and the first copper film constitutes a power supply wiring,
A semiconductor device, wherein the wiring having the second barrier conductor film and the second copper film constitutes a signal wiring. In the semiconductor device according to any one of claims 1 to 5 ,
the first plug has a first tungsten film,
The semiconductor device, wherein the second plug has a second tungsten film. In the semiconductor device according to any one of claims 1 to 5 ,
The first plug is
a third barrier conductor film formed to cover the inner wall of the first connection hole;
a first tungsten film formed on the third barrier conductor film so as to fill the first connection hole;
has
The second plug is
a fourth barrier conductor film formed to cover the inner wall of the second connection hole;
a second tungsten film formed on the fourth barrier conductor film so as to fill the second contact hole;
A semiconductor device having In the semiconductor device according to claim 7 ,
the third barrier conductor film has a first titanium nitride film,
The semiconductor device, wherein the fourth barrier conductor film has a second titanium nitride film. In the semiconductor device according to claim 7 ,
The third barrier conductor film is
a first titanium film;
a first titanium nitride film formed on the first titanium film;
has
The fourth barrier conductor film is
a second titanium film;
a second titanium nitride film formed on the second titanium film;
A semiconductor device having In the semiconductor device according to any one of claims 1 to 9 ,
The semiconductor device, wherein the half pitch is 45 nm or more and 60 nm or less. In the semiconductor device according to any one of claims 1 to 10 ,
A semiconductor device further comprising a barrier insulating film formed between the first interlayer insulating film and the second interlayer insulating film. 12. The semiconductor device according to claim 11 ,
The barrier insulating film is
a SiCN film;
a SiCO film formed on the SiCN film;
A semiconductor device having 12. The semiconductor device according to claim 11 ,
The semiconductor device, wherein the barrier insulating film is a SiC film or a SiN film. In the semiconductor device according to any one of claims 1 to 13 ,
The semiconductor element is
a gate insulating film formed on the main surface of the semiconductor substrate;
a gate electrode formed on the gate insulating film;
a first sidewall formed on a first sidewall of the gate electrode;
a second sidewall formed on a second sidewall of the gate electrode;
a source region formed under the first sidewall in the semiconductor substrate;
a drain region formed under the second sidewall in the semiconductor substrate;
has
The semiconductor device, wherein the first plug reaches the source region or the drain region. 15. The semiconductor device according to claim 14 ,
The gate electrode is
a polysilicon film;
a silicide film formed on the polysilicon film;
A semiconductor device having In the semiconductor device according to any one of claims 1 to 15 ,
a surface protective film formed on the second interlayer insulating film;
a polyimide film formed on the surface protective film;
A semiconductor device, further comprising: 17. The semiconductor device according to claim 16 ,
The surface protective film is
a silicon oxide film;
a silicon nitride film formed on the silicon oxide film;
A semiconductor device having In the semiconductor device according to any one of claims 1 to 17 ,
The first wiring is
a fifth barrier conductor film formed to cover the inner wall of the first wiring trench and the first plug exposed in the first wiring trench;
a third copper film formed on the fifth barrier conductor film so as to fill the first wiring trench;
has
the second wiring,
a sixth barrier conductor film formed to cover the inner wall of the second wiring trench and the second plug exposed in the second wiring trench;
a fourth copper film formed on the sixth barrier conductor film so as to fill the second wiring trench;
A semiconductor device having

Images