CN117202773A - Capacitor structure and preparation method thereof - Google Patents
Capacitor structure and preparation method thereof Download PDFInfo
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- CN117202773A CN117202773A CN202311215716.9A CN202311215716A CN117202773A CN 117202773 A CN117202773 A CN 117202773A CN 202311215716 A CN202311215716 A CN 202311215716A CN 117202773 A CN117202773 A CN 117202773A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 65
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 239
- 150000004767 nitrides Chemical class 0.000 claims abstract description 167
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000007772 electrode material Substances 0.000 claims abstract description 22
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 76
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 48
- 229910000077 silane Inorganic materials 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 47
- 229910021529 ammonia Inorganic materials 0.000 claims description 29
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 20
- 238000002955 isolation Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 264
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 19
- 229910052757 nitrogen Inorganic materials 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910007991 Si-N Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910006294 Si—N Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- VSSLEOGOUUKTNN-UHFFFAOYSA-N tantalum titanium Chemical compound [Ti].[Ta] VSSLEOGOUUKTNN-UHFFFAOYSA-N 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
Abstract
The application relates to a capacitor structure and a preparation method thereof, wherein the preparation method of the capacitor structure comprises the following steps: providing a substrate, wherein a first polar plate material layer is formed on the substrate; forming a first nitride material layer on the first electrode plate material layer; forming an oxide material layer on the first nitride material layer; forming a second nitride material layer on the oxide material layer; a second layer of electrode material is formed over the second layer of nitride material. By arranging the capacitance dielectric layer of the N-O-N structure, the breakdown voltage of the capacitance structure is improved. According to the capacitor structure and the preparation method thereof, the capacitor dielectric layer comprises the first nitride material layer, the oxide material layer and the second nitride material layer, so that the isolation capability of the capacitor dielectric layer is improved, and the breakdown voltage of the capacitor structure is improved.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a capacitor structure and a preparation method thereof.
Background
The capacitor structure consists of a first polar plate, a second polar plate and a capacitor medium layer between the two polar plates. The maximum voltage that the capacitor structure can withstand under normal operating conditions is the breakdown voltage. When the voltage between the two polar plates of the capacitor structure exceeds the breakdown voltage, the capacitor structure cannot work normally. Therefore, the performance of the capacitor structure can be effectively improved by improving the breakdown voltage of the capacitor structure.
Disclosure of Invention
Based on the above, the application provides a capacitor structure for improving the breakdown voltage of the capacitor structure and a preparation method thereof.
In order to achieve the above object, in one aspect, the present application provides a method for manufacturing a capacitor structure, including:
providing a substrate, wherein the substrate is formed with a first polar plate material layer;
forming a first nitride material layer on the first electrode plate material layer;
forming an oxide material layer on the first nitride material layer;
forming a second nitride material layer on the oxide material layer;
and forming a second electrode material layer on the second nitride material layer.
In one embodiment, the forming a first nitride material layer on the first electrode plate material layer includes:
introducing silane and ammonia into the process chamber, wherein the silane and the ammonia are deposited on the first polar plate material layer to form the first nitride material layer, and the flow rate of the silane is smaller than or equal to a preset flow rate;
and/or the number of the groups of groups,
the forming a second nitride material layer on the oxide material layer includes:
and introducing silane and ammonia into the process chamber, wherein the silane and the ammonia are deposited on the oxide material layer to form the second nitride material layer, and the flow rate of the silane is smaller than or equal to a preset flow rate.
In one embodiment, the preset flow is 370Sccm.
In one embodiment, the silane flow rate is 230Sccm-370Sccm, and the first nitride material layer is formed on the first electrode plate material layer and/or the second nitride material layer is formed on the oxide material layer.
In one embodiment, the forming a first nitride material layer on the first electrode plate material layer includes:
introducing silane and ammonia into the process chamber, wherein the silane and the ammonia form the first nitride material layer on the first polar plate material layer;
and stopping introducing the silane and continuously introducing the ammonia when the thickness of the first nitride material layer reaches a first preset thickness, and keeping the flow rate of the ammonia unchanged.
In one embodiment, the forming a second nitride material layer on the oxide material layer includes:
introducing silane and ammonia into the process chamber, wherein the silane and the ammonia form the second nitride material layer on the oxide material layer;
and stopping introducing the silane and continuously introducing the ammonia when the thickness of the second nitride material layer reaches a second preset thickness, and keeping the flow rate of the ammonia unchanged.
In one embodiment, the thicknesses of the first nitride material layer, the oxide material layer, and the second nitride material layer are the same.
In one embodiment, after forming the second electrode material layer on the second nitride material layer, the method includes:
forming a patterned photoresist layer on the second electrode material layer;
and etching the second electrode plate material layer, the second nitride material layer, the oxide material layer, the first nitride material layer and the first electrode plate material layer based on the patterned photoresist layer to form a second electrode plate, a second nitride layer, an oxide layer, a first nitride layer and a first electrode plate.
In another aspect, the present application further provides a capacitor structure, including:
a substrate;
a first plate on the substrate;
the capacitor dielectric layer is positioned on the first polar plate and comprises a first nitride layer, an oxide layer and a second nitride layer which are sequentially arranged from the first polar plate;
and a second plate on the second nitride layer.
In one embodiment, the thicknesses of the first nitride layer, the oxide layer, and the second nitride layer are the same.
According to the capacitor structure and the preparation method thereof, the capacitor dielectric layer comprises the first nitride material layer, the oxide material layer and the second nitride material layer, so that the isolation capability of the capacitor dielectric layer is improved, and the breakdown voltage of the capacitor structure is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of a method for fabricating a capacitor structure according to an embodiment;
fig. 2 to fig. 4 are schematic views of intermediate structures obtained in the method for manufacturing a capacitor structure according to an embodiment.
Reference numerals illustrate: a capacitor structure-100; a base-110; a first layer of electrode material 120; first plate-1201; a layer of capacitive dielectric material-130; a capacitive dielectric layer-1301; a first nitride material layer-131; a first nitride layer-1311; oxide material layer-132; oxide layer-1321; a second nitride material layer-133; second nitride layer-1331; a second layer of electrode material-140; a second pole plate-1401; the photoresist layer-150 is patterned.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" another element or layer, it can be directly on, adjacent to, connected to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present embodiment.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the embodiments, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are expected. Thus, embodiments of the present embodiments should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present embodiments.
In one embodiment, referring to fig. 1, a method for manufacturing a capacitor structure 100 is provided, including the following steps:
step S100: a substrate 110 is provided, the substrate 110 being formed with a first layer 120 of pole plate material.
Step S200: a first nitride material layer 131 is formed on the first electrode material layer 120.
Step S300: an oxide material layer 132 is formed on the first nitride material layer 131.
Step S400: a second nitride material layer 133 is formed on the oxide material layer 132.
Step S500: a second plate material layer 140 is formed on the second nitride material layer 133.
In step S100, referring to fig. 2, the substrate 110 may be made of a semiconductor material, an insulating material, or any combination thereof. The substrate 110 may have a single-layer structure or a multi-layer structure. For example, the material of the substrate 110 may include silicon, silicon germanium carbon, silicon carbide, gallium arsenide, indium phosphide, and the like.
The base 110 may also be a silicon substrate on which a metal oxide semiconductor transistor has been formed, or may also be a substrate on which an underlying metal wiring structure has been formed.
The first pole piece material layer 120 may be formed using a deposition process. By way of example, the deposition process may include, but is not limited to, one or more of a chemical vapor deposition process, an atomic layer deposition process, a high density plasma deposition process, a plasma enhanced deposition process, and a spin-on dielectric layer, among others.
The material of the first electrode material layer 120 may include cobalt, nickel, titanium, tungsten, tantalum titanate, tungsten nitride, copper, aluminum, and other conductive materials.
In step S200, referring to fig. 2, a first nitride material layer 131 may be deposited over the first electrode plate material layer 120. As an example, the process of depositing the first nitride material layer 131 may be the same as the process of depositing the material layer of the first electrode plate material layer 120. Of course, the process of depositing the first nitride material layer 131 may be different from the process of depositing the material layer of the first electrode plate material layer 120.
The material of the first nitride material layer 131 may include silicon nitride or the like.
In step S300, referring to fig. 2, an oxide material layer 132 is formed on the first nitride material layer 131 by deposition. As an example, the material of the oxide material layer 132 may include silicon oxide or the like.
Illustratively, in step S300, the process temperature may be 400+ -20deg.C, siH 4 The flow rate of (C) can be 160+ -70 sccm, N 2 The O flow rate can be 8000+ -1000 Sccm, the pressure can be 3+ -1 Torr, and the HF can be 540+ -100 W Spacing may be 500+ -50 Mills.
In step S400, referring to fig. 2, a second nitride material layer 133 is continuously formed on the oxide material layer 132. As an example, the material of the first nitride material layer 131 may be the same as the material of the second nitride material layer 133. At this time, the material of the first nitride material layer 131 and the material of the second nitride material layer 133 may be silicon oxide.
The first nitride material layer 131, the oxide material layer 132, and the second nitride material layer 133 constitute the capacitance dielectric material layer 130.
In step S500, referring to fig. 2, a second plate material layer 140 is formed on the second nitride material layer 133. The second electrode material layer 140 may be formed in the same manner as the first electrode material layer 120.
As an example, the material of the second electrode plate material layer 140 may be the same as the material of the first electrode plate material layer 120. At this time, the material of the second electrode material layer 140 and the material of the first electrode material layer 120 may be one or more metals selected from copper, aluminum, gold, silver, tungsten, etc.
The inventors found in experiments that after the capacitor structure is subjected to wafer acceptability test (Wafer Acceptance Test, WAT), the breakdown voltage is low, and the capacitor structure is tested and has a Special edge Map. The inventors have studied that the breakdown voltage of the capacitor structure 100 is related to the compactness of the capacitor dielectric layer. The higher the compactness of the capacitive dielectric layer, the higher the breakdown voltage of the capacitive structure 100.
The compactness of the capacitance medium layer can be expressed as the content of main chemical bonds in the film layer of the capacitance medium layer. The inventors have found that, due to the longer Si-H bond length, the bond energy is lower, and that the higher the density of the capacitive dielectric layer, the higher the breakdown voltage of the capacitive structure 100, as the Si-H bond content in the capacitive dielectric layer film is lower.
Correspondingly, the bond length of Si-N is shorter, the bond energy is higher, and increasing the content of Si-N in the capacitance medium layer can increase the compactness of the capacitance medium layer.
In this embodiment, the capacitor dielectric material layer 130 includes the first nitride material layer 131, the oxide material layer 132 and the second nitride material layer 133, and by setting the oxide material layer 132, the si—h bond content in the capacitor dielectric material layer 130 is reduced, the compactness of the capacitor dielectric material layer 130 is improved, the capability of isolating the first electrode plate material layer 120 and the second electrode plate material layer 140 by the capacitor dielectric material layer 130 is increased, the breakdown voltage of the capacitor structure 100 is improved, and further the performance of the capacitor structure 100 is improved.
For example, the first nitride material layer 131 may be prepared by a plasma enhanced chemical vapor deposition (Plasma enhanced chemical vapor deposition, PECVD) method. Wherein, the silicon source gas adopts silane (SiH 4 ) The reaction gas is ammonia (NH) 3 ) And nitrogen (N) 2 ). Meanwhile, nitrogen can also be used as carrier gas.
The reaction equation for preparing the first nitride material layer 131 is:
3 SiH 4 （g）+2 N 2 （g）+2 NH 3 （g）→Si 3 N 4 （g）+9 H 2 （g）+ N 2 （g）
at this time, the content of si—n bonds in the first nitride material layer 131 may be increased by decreasing the content of si—h in the process of preparing the first nitride material layer 131. As an example, step S200 includes:
step S210: and introducing silane and ammonia into the process chamber, and depositing the silane and the ammonia on the first polar plate material layer 120 to form a first nitride material layer 131, wherein the flow rate of the silane is smaller than or equal to a preset flow rate.
As an example, the preset flow rate of silane may be 370Sccm. Further, to ensure the efficiency of preparing the first nitride material layer 131, the flow rate of silane may be between 230Sccm and 370Sccm.
While introducing silane and ammonia, nitrogen is also introduced. The silane, ammonia, and nitrogen react according to the above reaction equation to form the first nitride material layer 131.
By reducing the flow of silane, the content of Si-H in the reaction process is reduced, so that the content of Si-N generated in the reaction process is increased, and the content of silicon nitride in the finally formed first nitride material layer 131 is further increased, so that the compactness of the first nitride material layer 131 is improved, and finally the breakdown voltage of the capacitor structure 100 is increased.
Illustratively, in step S210, the process temperature may be 400+ -20deg.C, the flow rate of ammonia may be 160+ -40 Sccm, the flow rate of nitrogen may be 18000+ -2000 Sccm, the process chamber pressure may be 4.2+ -1 Torr, the High Frequency power (HF) may be 800+ -100W, and the plate Spacing (Spacing) may be 560+ -50 Mills.
The above data are merely examples, and in practical embodiments, the conditions for preparing the first nitride material layer 131 are not limited to the above data.
Meanwhile, the process of preparing the second nitride material layer 133 may be the same as the process of preparing the first nitride material layer 131. As an example, step S400 may include:
step S410: silane and ammonia gas are introduced into the process chamber, and the silane and ammonia gas form a second nitride material layer 133 on the first electrode plate material layer 120, wherein the flow rate of the silane is less than or equal to a preset flow rate.
At this time, the si—n content in the first nitride material layer 131 and the si—n content in the second nitride material layer 133 are both higher, further improving the breakdown voltage of the capacitor structure 100.
Other process conditions for preparing the second nitride material layer 133 may refer to process conditions for preparing the first nitride material layer 131. And will not be described in detail herein.
Of course, it should be understood by those skilled in the art that, in the capacitor structure 100, the si—n content in any one of the first nitride material layer 131 and the second nitride material layer 133 may be increased by the above method, and the si—n content in the first nitride material layer 131 and the second nitride material layer 133 may also be increased simultaneously by the above method.
In one embodiment, step S200 may include:
step S220: silane and ammonia gas are introduced into the process chamber, and the silane and ammonia gas form a first nitride material layer 131 on the first electrode material layer 120.
Step S221: when the thickness of the first nitride material layer 131 reaches the first preset thickness, the silane is stopped and the ammonia gas is continuously introduced and the flow rate of the ammonia gas is kept unchanged.
In step S220, as an example, silane and ammonia are used as reaction gases, and nitrogen is used as carrier gas. Based on the chemical reaction formula, silane, ammonia and nitrogen react to form silicon nitride. For example, the first preset thickness of the first nitride material layer 131 may be 300±200 a. The flow rate of nitrogen may be 18000.+ -.2000 Sccm.
Silicon nitride is deposited on the first electrode material layer to form a first nitride material layer 131. At this time, in the conventional technology, the surface of the first nitride material layer is uneven, and small holes often occur, which makes the first nitride material layer easily broken down at the holes to generate leakage current.
Then, in step S221, after the thickness of the first nitride material layer 131 reaches the first preset thickness, the silane may be stopped and the ammonia gas may be continuously introduced. In addition, the flow of the introduced ammonia gas is kept unchanged in the process. As an example, ammonia gas may be continuously introduced for 5 seconds.
The ammonia gas can be deposited on the surface of the first nitride material layer 131 to fill up the tiny holes on the surface of the first nitride material layer 131, so as to form a flat surface of the first nitride material layer 131, thereby improving the breakdown voltage of the first nitride material layer 131.
Meanwhile, in forming the second nitride material layer 133, a flat surface of the second nitride material layer 133 may be formed in the same manner. At this time, step S400 includes:
step S410: silane and ammonia are introduced into the process chamber, which form a second nitride material layer 133 over the oxide material layer 132.
Step S420: when the thickness of the second nitride material layer 133 reaches the second preset thickness, the introduction of silane is stopped and the ammonia gas is continuously introduced and the flow rate of the ammonia gas is kept unchanged.
In step S410, as an example, the second preset thickness of the second nitride material layer 133 may also be 300±200 a. The flow rate of nitrogen may be 18000.+ -.2000 Sccm.
In step S420, as an example, the nitrogen gas may be continuously introduced for 5 seconds.
In this embodiment, in order to fill the fine holes on the surface of the first nitride material layer 131 and/or the surface of the second nitride material layer 133, the silane is stopped from being introduced and the ammonia gas is continuously introduced into the surface of the first nitride material layer 131 and/or the surface of the second nitride material layer 133, so that the fine holes on the surface are filled, and a flat surface is formed, thereby improving the breakdown voltage of the capacitor structure 100.
In addition, the flow rate of the ammonia gas is not changed, and the silane is only stopped, so that the process is simple and easy to control.
It will be appreciated by those skilled in the art that the capacitor structure 100 may be fabricated by the method described above to obtain a first nitride material layer 131 having a planar surface, or alternatively, by the method described above to obtain a second nitride material layer 133 having a planar surface. Of course, the above method may be used to obtain the first nitride material layer 131 with a flat surface and the second nitride material layer 133 with a flat surface at the same time.
In one embodiment, the thicknesses of the first nitride material layer 131, the oxide material layer 132, and the second nitride material layer 133 are the same.
As an example, the thicknesses of the first nitride material layer 131, the oxide material layer 132, and the second nitride material layer 133 may be 300±200 a. The above data are merely examples, and in practical embodiments, the thicknesses of the first nitride material layer 131, the oxide material layer 132, and the second nitride material layer 133 are not limited to the above data.
In this embodiment, the thicknesses of the first nitride material layer 131, the oxide material layer 132 and the second nitride material layer 133 are the same, so that when the capacitor structure 100 has a voltage, the electric field is more uniformly distributed between different layers, which is helpful to avoid excessive concentration of the electric field in a thinner film layer, improve the overall breakdown voltage of the capacitor structure 100, and reduce the risk of breakdown of the capacitor structure 100.
In one embodiment, referring to fig. 3 and 4, after step S500, the method includes:
step S600: a patterned photoresist layer 150 is formed over the second photoresist layer 140.
Step S610: the second electrode plate 1401, the second nitride layer 1331, the oxide layer 1321, the first nitride layer 1311, and the first electrode plate 1201 are formed by etching the second electrode plate material layer 140, the second nitride material layer 133, the oxide material layer 132, the first nitride material layer 131, and the first electrode plate material layer 120 based on the patterned photoresist layer 150.
In step S600, the patterned photoresist layer 150 defines the locations of the capacitor structures 100.
In step S610, the second electrode material layer 140, the second nitride material layer 133, the oxide material layer 132, the first nitride material layer 131, and the first electrode material layer 120 are sequentially etched based on the patterned photoresist layer 150. The remaining second electrode material layer 140, second nitride material layer 133, oxide material layer 132, first nitride material layer 131, and first electrode material layer 120 constitute the capacitor structure 100.
At this time, the capacitor structure 100 includes a second plate 1401, a second nitride layer 1331, an oxide layer 1321, a first nitride layer 1311, and a first plate 1201. The second nitride layer 1331, the oxide layer 1321, and the first nitride layer 1311 constitute the capacitor dielectric layer 1301.
As an example, the etching process may include at least any one of reactive ion etching, inductively coupled plasma etching, or high concentration plasma etching.
After the capacitor structure 100 is formed, the first electrode plate 1201 and the second electrode plate 1401 can be connected to different electronic devices, and the capacitor dielectric layer 1301 formed by the first nitride layer 1311, the oxide layer 1321 and the second nitride layer 1331 can enable the capacitor structure 100 to have a higher breakdown voltage.
As an example, the capacitor structure 100 may be a Metal-Insulator-Metal (MIM) structure that is applied in devices with 0.11 μm line width.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.
Based on the same inventive concept, please continue to refer to fig. 4, in one embodiment, a capacitor structure 100 is further provided. The capacitor structure 100 includes: a substrate 110, a first plate 1201, a capacitive dielectric layer 1301 and a second plate 1401.
The substrate 110 may be formed of a semiconductor material, an insulating material, or any combination thereof. The substrate 110 may have a single-layer structure or a multi-layer structure. For example, the material of the substrate 110 may include silicon, silicon germanium carbon, silicon carbide, gallium arsenide, indium phosphide, and the like.
The base 110 may also be a silicon substrate on which a metal oxide semiconductor transistor has been formed, or may also be a substrate on which an underlying metal wiring structure has been formed.
The first plate 1201 is located on the substrate 110. The material of the first plate 1201 may include conductive materials such as cobalt, nickel, titanium, tungsten, tantalum, titanium tantalum, tungsten nitride, copper, and aluminum.
A capacitive dielectric layer 1301 is located on the first plate 1201. The capacitor dielectric layer 1301 includes a first nitride layer 1311, an oxide layer 1321, and a second nitride layer 1331 disposed in this order from the first plate 1201.
As an example, the material of the first nitride layer 1311 may include silicon nitride, the material of the oxide layer 1321 may include silicon oxide, and the material of the second nitride layer 1331 may include silicon nitride.
The second plate 1401 is located on the second nitride layer 1331. As an example, the material of the second plate 1401 may be the same as the material of the first plate 1201. As an example, the material of the second plate 1401 and the material of the first plate 1201 may be one or more of copper, aluminum, gold, silver, tungsten, and the like.
Of course, the material of the second plate 1401 may be different from the material of the first plate 1201.
In this embodiment, the capacitance dielectric layer 1301 includes the first nitride layer 1311, the oxide layer 1321 and the second nitride layer 1331, and by setting the oxide material layer 132, the si—h bond content in the capacitance dielectric material layer 130 is reduced, the compactness of the capacitance dielectric material layer 130 is improved, the capability of the capacitance dielectric layer 1301 to isolate the first polar plate 1201 and the second polar plate 1401 is increased, the breakdown voltage of the capacitance structure 100 is improved, and further the performance of the capacitance structure 100 is improved.
In one embodiment, the thicknesses of the first nitride material layer 131, the oxide material layer 132, and the second nitride material layer 133 are the same.
As an example, the thicknesses of the first nitride material layer 131, the oxide material layer 132, and the second nitride material layer 133 may be 300±200 a. The above data are merely examples, and in practical embodiments, the thicknesses of the first nitride material layer 131, the oxide material layer 132, and the second nitride material layer 133 are not limited to the above data.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. A method of making a capacitor structure, comprising:
providing a substrate, wherein the substrate is formed with a first polar plate material layer;
forming a first nitride material layer on the first electrode plate material layer;
forming an oxide material layer on the first nitride material layer;
forming a second nitride material layer on the oxide material layer;
and forming a second electrode material layer on the second nitride material layer.
2. The method of manufacturing a capacitor structure of claim 1,
the forming a first nitride material layer on the first electrode plate material layer includes:
introducing silane and ammonia into the process chamber, wherein the silane and the ammonia are deposited on the first polar plate material layer to form the first nitride material layer, and the flow rate of the silane is smaller than or equal to a preset flow rate;
and/or the number of the groups of groups,
the forming a second nitride material layer on the oxide material layer includes:
and introducing silane and ammonia into the process chamber, wherein the silane and the ammonia are deposited on the oxide material layer to form the second nitride material layer, and the flow rate of the silane is smaller than or equal to a preset flow rate.
3. The method of manufacturing a capacitor structure according to claim 2, wherein the predetermined flow rate is 370Sccm.
4. A method of fabricating a capacitor structure according to claim 3, wherein the silane flow rate is 230Sccm-370Sccm, and wherein the first nitride material layer is formed on the first electrode material layer and/or the second nitride material layer is formed on the oxide material layer.
5. The method of claim 1, wherein forming a first nitride material layer on the first electrode material layer, comprises:
introducing silane and ammonia into the process chamber, wherein the silane and the ammonia form the first nitride material layer on the first polar plate material layer;
and stopping introducing the silane and continuously introducing the ammonia when the thickness of the first nitride material layer reaches a first preset thickness, and keeping the flow of the ammonia unchanged.
6. The method of claim 1, wherein forming a second nitride material layer on the oxide material layer, comprises:
introducing silane and ammonia into the process chamber, wherein the silane and the ammonia form the second nitride material layer on the oxide material layer;
and stopping introducing the silane and continuously introducing the ammonia when the thickness of the second nitride material layer reaches a second preset thickness, and keeping the flow rate of the ammonia unchanged.
7. The method of claim 1, wherein the thicknesses of the first nitride material layer, the oxide material layer, and the second nitride material layer are the same.
8. The method of manufacturing a capacitor structure according to claim 1, wherein after forming a second electrode material layer on the second nitride material layer, the method comprises:
forming a patterned photoresist layer on the second electrode material layer;
and etching the second electrode plate material layer, the second nitride material layer, the oxide material layer, the first nitride material layer and the first electrode plate material layer based on the patterned photoresist layer to form a second electrode plate, a second nitride layer, an oxide layer, a first nitride layer and a first electrode plate.
9. A capacitor structure, comprising:
a substrate;
a first plate on the substrate;
the capacitor dielectric layer is positioned on the first polar plate and comprises a first nitride layer, an oxide layer and a second nitride layer which are sequentially arranged from the first polar plate;
and a second plate on the second nitride layer.
10. The capacitive structure of claim 9, wherein the thicknesses of the first nitride layer, the oxide layer, and the second nitride layer are the same.
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