CN101090099A - Solder lug and manufacturing method thereof - Google Patents
Solder lug and manufacturing method thereof Download PDFInfo
- Publication number
- CN101090099A CN101090099A CNA2006100275885A CN200610027588A CN101090099A CN 101090099 A CN101090099 A CN 101090099A CN A2006100275885 A CNA2006100275885 A CN A2006100275885A CN 200610027588 A CN200610027588 A CN 200610027588A CN 101090099 A CN101090099 A CN 101090099A
- Authority
- CN
- China
- Prior art keywords
- layer
- solder projection
- manufacture method
- pad
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
This inveention discloses a solder hump and its manufacturing method, which first of all coats a patttern photo resist layer on a wafer or UBM under salient points to form a figure area, in which, said UBM layer includes Cr/Cu, Cr/CrCu/Cu, Ti/Cu, TiW/Cu or Ta/Cu deposited layer by layer, then forms a Ni layer as the block layer in the figure, on the wafer or above the UBM layer and forms a Cu layer on the block layer as a welding layer and finally removes the photo resist layer on the un-figure region and etches the UBM layer covered by the un-figure region of the photo resist layer to form solder salient points on the welding layer to further realize connection of the wafer with outside by the welding way.
Description
Technical field
The present invention relates to integrated circuit and make field, the particularly encapsulation field of integrated circuit (IC) chip.
Background technology
One of three big industry pillars that the encapsulation technology of integrated circuit (IC) chip develops as integrated circuit, not only directly affect performance, reliability and the cost of integrated circuit itself, also determining the process of complete electronic set system to a great extent to small portable and multifunctional direction development.Therefore, industry is more and more paid attention to the optimization technology of integrated circuit (IC) chip encapsulation technology.
For the wafer-class encapsulation (WLP) of current main-stream, the first-selected direction of improvement WLP technology is for optimizing structure and the manufacture method thereof of wafer so as to the solder projection that links to each other with external circuitry.
Fig. 1 is existing solder tappet structure schematic diagram, and as shown in Figure 1, existing solder projection comprises pad 200, solder bump lower metal layer (UBM) 700 and the solder bump 800 that joins in turn; Pad 200 links to each other with the external lead wire of wafer 100, and is attached on the wafer 100; UBM layer 700 has sandwich construction, and the interlayer close proximity; The orlop of UBM layer 700 links to each other with pad 200, and the superiors link to each other with solder bump 800.
The manufacture method of existing solder projection mainly comprises:
1. wafer surface is carried out preliminary treatment, comprising: on wafer, form pad 200 and protective layer 300; Protective layer 300 has an open region 400, and open region 400 is in order to exposed pad 200 surfaces; Pad 200 materials are Al or Cu; Protective layer 300 materials are the silicon nitride (Si of deposition
3N
4), silica (SiO
2) and silicon oxynitride (SiON) etc.; Deposition process is sputter, plating or other method;
2. on pad 200, form a UBM layer 700 as the welding wetting surface; UBM layer 700 comprises Al/NiV/Cu or the Ti/NiV/Cu that successively forms; The formation method is sputter, plating or other method;
3. on UBM layer 700, form one deck solder bump 800, so as to realize being connected of wafer 100 and external circuitry by welding manner; Solder bump 800 materials are Sn and alloy thereof etc.
Be the solder projection manufacture method described in the Chinese patent application of " 200310104780.6 " as application number, utilize the method, about 5 microns of the Cu layer thickness in the described UBM layer 700; Form that blocked up Cu layer not only can cause the production time to prolong, production efficiency reduces, and can cause the increase of volume of the certain integrated circuit (IC) chip of integrated level and the increase of production cost; Simultaneously, in the UBM layer 700 of Al/NiV/Cu or Ti/NiV/Cu structure, NiV and Al or Ti bonding, matching degree is slightly poor, causes the stability of solder projection slightly poor, and then influences the reliability of integrated circuit (IC) chip encapsulation.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of solder projection and manufacture method thereof,, strengthen package reliability and also reduce cost simultaneously in order to optimize technology, reduce encapsulation volume, to enhance productivity.
For achieving the above object, a kind of solder projection provided by the invention comprises: the pad 200 that forms on wafer 100 surfaces; The UBM layer 700, barrier layer 710, the weld layer 720 that on described pad 200, form successively, and be formed at solder bump 800 on the described weld layer 720; Described UBM layer 700 has sandwich construction; The orlop of described UBM layer 700 links to each other with pad 200, and its superiors link to each other with barrier layer 710; Described pad 200 materials are AL or Cu; Described UBM layer 700 comprises Cr/Cu, Cr/CrCu/Cu, Ti/Cu, TiW/Cu or the Ta/Cu of layer by layer deposition; Described UBM layer 700 is formed on the pad 200; Described UBM layer 700 is connected by lead-in wire 730 with pad 200; Described lead-in wire 730 materials are Cu; Described UBM layer 700 thickness range are 0.3～0.5 micron; Described barrier layer 710 materials are Ni; Described barrier layer 710 thickness ranges are 1～2 micron; Described weld layer 720 materials are Cu; Described weld layer 720 thickness ranges are 0.5～3 micron; A kind of material in the lead-free alloy that described solder bump 800 materials are PbSn alloy, high lead alloy or tin.
A kind of solder projection provided by the invention comprises: the pad 200 that forms on wafer 100 surfaces; The barrier layer 710, weld layer 720 and the solder bump 800 that on described pad 200, form successively; Described pad 200 materials are Cu; Described barrier layer 710 materials are Ni; Described barrier layer 710 thickness ranges are 1～2 micron; Described weld layer 720 materials are Cu; Described weld layer 720 thickness ranges are 0.5～3 micron; A kind of material in the lead-free alloy that described solder bump 800 materials are PbSn alloy, high lead alloy or tin.
A kind of solder projection manufacture method provided by the invention comprises:
On wafer 100, form pad (200) and protective layer 300;
Go up formation one UBM layer 700 at described pad 200 and protective layer (300);
On described UBM layer 700, apply a photoresist layer 600, and the described photoresist layer 600 of patterning, in order to form and pad 200 corresponding opening districts 400;
In described graph area, on the UBM layer 700, form a barrier layer 710;
In described graph area, on the barrier layer 710, form a weld layer 720;
Remove described photoresist layer 600, and the described UBM layer 700 of etching;
On described weld layer 720, form solder bump 800.
Described protective layer 300 has an open region 400, and described open region 400 is in order to exposed pad 200 surfaces; Described UBM layer 700 is formed on the pad 200; Described UBM layer 700 is connected by lead-in wire 730 with pad 200, and described lead-in wire 730 adheres on described protective layer 300 or the resilient coating 500; Described lead-in wire 730 materials are Cu; Also be formed with first resilient coating 500 between described UBM layer 700 and the protective layer 300; Described UBM layer 700 is connected by lead-in wire 730 with pad 200, and described lead-in wire 730 adheres on the described protective layer 300 or first resilient coating 500; Described lead-in wire 730 is isolated in the external world by second resilient coating 510; Described first resilient coating 500 has the open region 400 identical with protective layer 300 and is covered in fully on the described protective layer 300; Described open region 400 forms by the etching mode; Described UBM layer 700 material are Cr/Cu or Ti/Cu; Described resilient coating 500 materials are insulating material; Described insulating material is the two oxazoles (PBO) of polyimides (Polyimide), benzocyclobutene (BCB) or polyparaphenylene's benzo etc.; Described UBM layer 700 forms by sputtering method; Described UBM layer 700 thickness range are 0.3～0.5 micron; Described photoresist layer 600 thickness are 5～10 microns; The local UBM layer 700 that the graph area of described photoresist layer 600 exposes is any zone on UBM layer 700 surface; Described barrier layer 710 materials are Ni; Described barrier layer 710 thickness ranges are 1～2 micron; Described barrier layer 710 forms by electro-plating method; Described weld layer 720 materials are Cu; Described weld layer 720 thickness ranges are 0.5～3 micron; Described weld layer 720 forms by electro-plating method; The method of the described UBM layer 700 of etching is the dry etching method; A kind of material in the lead-free alloy that described solder bump 800 materials are PbSn alloy, high lead alloy or tin.
A kind of solder projection manufacture method provided by the invention comprises:
On wafer 100, form pad 200 and protective layer 300;
On described pad 200 and protective layer 300, apply a photoresist layer 600 and a patterning, in order to form and pad 200 corresponding opening districts 400;
In described open region 400, on pad 200 and the protective layer 300, form a barrier layer 710;
In described open region 400, on the barrier layer 710, form a weld layer 720;
Remove described photoresist layer 600;
On described weld layer 720, form solder bump 800.
Described protective layer 300 has an open region 400, and described open region 400 is in order to exposed pad 200 surfaces; Be formed with a resilient coating 500 between described photoresist layer 600 and pad 200 and the protective layer 300; Described barrier layer 710 is connected by lead-in wire 730 with pad 200, and described lead-in wire 730 adheres on the described protective layer 300 or first resilient coating 500; Described lead-in wire 730 is isolated in the external world by second resilient coating 510; Described first resilient coating 500 has the open region 400 identical with protective layer 300 and is covered in fully on the described protective layer 300; Described open region 400 forms by the etching mode; Described resilient coating 500 materials are insulating material; Described insulating material is the two oxazoles (PBO) of polyimides (Polyimide), benzocyclobutene (BCB) or polyparaphenylene's benzo etc.; Described photoresist layer 600 thickness are 5～10 microns; Described barrier layer 710 materials are Ni; Described barrier layer 710 thickness ranges are 1～2 micron; Described barrier layer 710 forms by electro-plating method; Described weld layer 720 materials are Cu; Described weld layer 720 thickness ranges are 0.5～3 micron; Described weld layer 720 forms by electro-plating method; A kind of material in the lead-free alloy that described solder bump 800 materials are PbSn alloy, high lead alloy or tin.
Compared with prior art, the present invention has the following advantages:
1.UBM only about 5 microns of layer 700, barrier layer 710, weld layer 720 integral thickness only are equivalent to the thickness of Cu layer individual layer in the prior art UBM layer 700; The reducing of UBM layer 700 thickness causes reducing of integrated circuit (IC) chip volume, is convenient to the miniaturization of electronic system product and the development of portability; Simultaneously, the shortening that reduces to cause the production time of UBM layer 700 thickness had both improved production efficiency, had reduced cost again;
2. weld layer 720Cu and solder bump 800 have lower diffusion coefficient at the composite material compositions that when welding reaction generates in Ni, and it is not contaminated to select for use Ni to do barrier layer 710 wafer 100 that can adequately protect;
3. between described pad 200 and protective layer 720 and UBM layer 700, UBM layer 700 and the barrier layer 710, between barrier layer 710 and the weld layer 720 and all possess good physical property matching between weld layer 720 and the solder bump 800; can guarantee has good physical connection between layer and the layer, and then guarantees the reliability of encapsulation.
Description of drawings
Figure 1 shows that the solder projection schematic diagram of prior art;
Figure 2 shows that solder projection manufacturing flow chart of the present invention;
Fig. 3 is to the manufacture process profile that Figure 10 shows that explanation solder projection first execution mode of the present invention;
Figure 11 is to the manufacture process profile that Figure 20 shows that explanation solder projection second execution mode of the present invention;
Figure 21 is extremely shown in Figure 22 to be the structural representation of solder projection the 3rd execution mode of the present invention;
Shown in Figure 23 for the structural representation of solder projection the 4th execution mode of the present invention;
Shown in Figure 24 for the structural representation of solder projection the 5th execution mode of the present invention;
Figure 25 is extremely shown in Figure 26 to be the structural representation of solder projection the 6th execution mode of the present invention;
Shown in Figure 27 for after solder projection forms, the structural representation of barrier layer and weld layer intersection section.
Wherein:
100: wafer; 200: pad;
300: protective layer; 400: open region;
500: the first resilient coatings; 510: the second resilient coatings;
600: the photoresist layer; The 700:UBM layer;
710: the barrier layer; 720: weld layer;
730: lead-in wire; 800: solder bump;
810: duplex alloy; 820: triple-phase alloys.
Embodiment
For described purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Figure 2 shows that solder projection manufacturing flow chart of the present invention; As shown in Figure 2, the manufacturing process of solder projection comprises: the wafer 100 that comprises pad is carried out preliminary treatment; Sputter one UBM layer 700 on pretreated wafer 100; On UBM layer 700, apply a photo-induced etching agent layer 600, and this photo-induced etching agent layer 600 of patterning, the graph area of exposing local UBM layer 700 formed; Electro-cladding 720 and weld layer 720 successively in photo-induced etching agent layer 600 graph area, on the UBM layer 700; Remove photo-induced etching agent layer 600, and patterning UBM layer 700; And then on weld layer 720, form solder bump 800, so as to forming solder projection by welding manner.
Fig. 3 is to the manufacture process profile that Figure 10 shows that explanation solder projection first execution mode of the present invention; As shown in the figure:
At first, wafer surface is carried out preliminary treatment, on wafer, form pad 200 and protective layer 300; Described protective layer 300 has an open region 400, and described open region 400 is in order to exposed pad 200 surfaces; Described pad 200 materials are Al or Cu; Described protective layer 300 materials are the silicon nitride (Si of deposition
3N
4), silica (SiO
2) and silicon oxynitride (SiON) etc.; Described deposition process is sputter, plating or other method.
Then, forming UBM layer 700 through pretreated wafer 100 surfaces; Described UBM layer 700 is for setting up the multilayer conductive dielectric layer of physical connection between wafer 100 and succeeding layer; Described UBM layer 700 comprises Cr/Cu, Cr/CrCu/Cu, Ti/Cu, TiW/Cu or the Ta/Cu of layer by layer deposition; All has good physical property matching between each layering in the described UBM layer 700, comprise and have close thermal coefficient of expansion and conducting power etc., and no congruent melting phenomenon takes place between adjacent layer, forms firm physical connection to guarantee described UBM layer 700 between wafer 100 and succeeding layer; Described deposition process can be selected sputtering method for use.
The Cr/CrCu/Ti/TiW/Ta layer is the articulamentum that directly contacts with pad or trace layer on the wafer 100 in the UBM layer 700 in the described UBM layer, adheres on the pad 200 and protective layer 300 on the described wafer 100; The protective layer 300 that plays 100 effects of protection wafer around described Cr/CrCu/Ti/TiW/Ta layer and pad 200 and the pad all has good adhesion property, and has favorable mechanical performance and electric conductivity; By described Cr/CrCu/Ti/TiW/Ta layer, can between wafer 100 and succeeding layer, form firm physical connection, described connection is not become flexible, was lost efficacy in follow-up continuous productive process and in the use of final electronic system product, and can be applicable under the certain physical active force; Described Cr/CrCu/Ti/TiW/Ta layer also should have barrier effect, in order to stop between succeeding layer material and pad 200 materials counterdiffusion takes place; Described Cr/CrCu/Ti/TiW/Ta layer formation method can adopt sputtering method.
And then on described Cr/CrCu/Ti/TiW/Ta layer, form a Cu layer, as the Seed Layer of follow-up electroplating technology; Described Cu layer has the good matching that is connected with described Cr/CrCu/Ti/TiW/Ta layer, plays the physical connection effect between described Cr/CrCu/Ti/TiW/Ta and succeeding layer.Described Cu layer can adopt sputtering method to be deposited on the described Cr/CrCu/Ti/TiW/Ta layer, forms UBM layer 700 jointly; Described UBM layer 700 is covered on the wafer 100 fully; The thickness range of described UBM layer 700 is between 0.3～0.5 micron; As embodiments of the present invention, the thickness of described UBM layer 700 is 0.4 micron.
Subsequently, on described UBM layer 700, apply a photoresist layer 600, and with described photoresist layer 600 patterning to form graph area; Photoresist in the described graph area is removed through developing procedure, and then exposes local UBM layer 700; The local UBM layer 700 that exposes in the described graph area be in pad 200 directly over; Described photoresist layer 600 thickness are 5～10 microns.
Deposition one barrier layer 710 in described graph area, on the UBM layer 700, and in described graph area, on the barrier layer 710, deposit a weld layer 720 again; Described barrier layer 710 diffuses in the wafer 100 with the impurity form in order to stop the composite material compositions that follow-up when welding generate; Described weld layer 720 is in order to providing the wetting surface of the welding with satisfactory electrical conductivity and mechanical performance, and then improves soldering reliability; The deposition process of described barrier layer 710 and weld layer 720 is selected galvanoplastic for use; Described barrier layer 710 materials are Ni; Described weld layer 720 materials are Cu; The decision of the physical property of Ni itself, blocked up Ni layer easily cause stronger because different residual thermal stresses that cause of thermal coefficient of expansion when connecting with other material; Among the present invention, when described residual thermal stress surpass connected UBM layer 700 and weld layer 720 bear the limit time, easily cause between wafer 100 and the external circuitry to be connected fracture, therefore, the thickness range on barrier layer described in the present invention 710 is between 1～2 micron; For good welding wetting surface is provided, consider the influence of thermal stress simultaneously, the thickness range of described weld layer 720 is between 0.5～3 micron.As embodiments of the present invention, the thickness on described barrier layer 710 is 2 microns; The thickness of described weld layer 720 is 3 microns.
After the barrier layer 710 of patterning and weld layer 720 form, remove remaining photic resist layer 600; Subsequently, the UBM layer 700 of etching photoresist layer 600 non-graph area covering; Described lithographic method can be selected the dry etching method for use, for example reactive ion etching (RIE).
At last, on weld layer 720, form solder bump 800; Described weld layer 720 is with after solder bump 800 is connected by solder reflow, pad 200, UBM layer 700, barrier layer 710, weld layer 720 and the solder bump 800 common solder projections of forming; And then described wafer 100 can be connected with external circuitry by described solder projection; The manufacturing of solder bump 800 can be adopted methods such as plating, printing with paste, chemical plating and evaporation; Solder bump 800 materials can be selected the lead-free alloy of PbSn alloy, high lead alloy, tin etc. for use.
Figure 11 is to the manufacture process profile that Figure 20 shows that explanation solder projection second execution mode of the present invention; As shown in the figure, wafer 100 carried out preliminary treatment after, form pad 200 and protective layer 300 on the wafer; Described protective layer 300 has an open region 400, and described open region 400 is in order to exposed pad 200 surfaces; Because special size requires and rewiring etc. needs, and before deposit UBM layer 700, needs to apply in advance the resilient coating 500 of one deck on protective layer 300; Described resilient coating 500 is in order to discharge the unnecessary stress that occurs in the welding process and can satisfy that special size requires and the needs of rewiring; Described resilient coating 500 has identical open region 400 with protective layer 300; Then on described resilient coating 500, utilize execution mode one described method successively to form described UBM layer 700, barrier layer 710, weld layer 720 and solder bump 800; Described pad 200, UBM layer 700, barrier layer 710, weld layer 720 and the solder bump 800 common solder projections of forming; Described resilient coating 500 materials can be selected the two oxazole dielectric resin material such as (PBO) of polyimides (Polyimide), benzocyclobutene (BCB) or polyparaphenylene's benzo for use; Described resilient coating 500 can form open region by modes such as etchings; Described resilient coating 500 thickness are selected according to actual needs; Described resilient coating 500 can remain in the final electronic system product.
Figure 21 is extremely shown in Figure 22 to be the structural representation of solder projection the 3rd execution mode of the present invention; As shown in the figure, before forming barrier layer 710 and weld layer 720, need on described UBM layer 700, to apply a photoresist layer 600, and with these photoresist layer 600 patternings, the graph area of local UBM layer 700 is exposed in formation, the local UBM layer 700 that the graph area of described photoresist layer 600 exposes can be any zone on UBM layer 700 surface, is not limited only to the area just above of pad 200; The graph area of the local UBM layer 700 of described non-pad 200 area just above of exposing links to each other by lead-in wire 730 with pad 200; Described lead-in wire 730 materials are Cu; Handle through non-proliferation between described lead-in wire 730 and the pad 200; Described lead-in wire 730 adheres on described protective layer 300 or the resilient coating 500; Then in the graph area of described photoresist layer 600, electroplate barrier layer 710 and weld layer 720 on the UBM layer 700; After removing photoresist layer 600, apply one deck cushioning layer material in non-graph area lead-in wire is isolated from the outside; Then can form solder projection according to embodiment one and embodiment two described methods, and so as between wafer 100 and external circuitry, forming firm physical connection.
Shown in Figure 23 for the structural representation of solder projection the 4th execution mode of the present invention; As shown in figure 23, described solder projection comprises pad 200, barrier layer 710, weld layer 720 and the solder bump 800 that joins in turn; Described pad 200 is attached on the described wafer 100; On the described wafer 100, deposit protective layer 300 around the pad 200; Described protective layer 300 has an open region 400, and described open region 400 is in order to exposed pad 200 surfaces; Described pad 200 materials are Cu; Described protective layer 300 materials are the silicon nitride (Si of deposition
3N
4), silica (SiO
2) and silicon oxynitride (SiON) etc.; Described deposition process is sputter, plating or other method.
On the wafer 100 that has pad 200 and protective layer 300, apply a photoresist layer 600, and with described photoresist layer 600 patterning to form graph area; Described graph area is positioned at pad 200 area just above; Photoresist in the graph area that described photoresist layer 600 patterning form is removed through developing procedure, and exposed region is pad 200 surfaces in the described graph area; Deposition one barrier layer 710 in described graph area, on pad 200 surfaces; And then in described graph area, on the barrier layer 710 deposition one weld layer 720; The thickness range of described photoresist layer 600 is between 5～10 microns; Described barrier layer 710 materials are Ni; Described weld layer 720 materials are Cu; The thickness range on described barrier layer 710 is between 1～2 micron; The thickness range of described weld layer 720 is between 0.5～3 micron; Described deposition process is selected galvanoplastic for use.As embodiments of the present invention, the thickness on described barrier layer 710 is 2 microns; The thickness of described weld layer 720 is 3 microns.After the barrier layer 710 of patterning and weld layer 720 form, remove remaining photic resist layer 600; Subsequently, the UBM layer 700 of etching photoresist layer 600 non-graph area covering; Described lithographic method can be selected the dry etching method for use.
At last, on weld layer 720, form solder bump 800; Described weld layer 720 is with after solder bump 800 is connected by solder reflow, pad 200, barrier layer 710, weld layer 720 and the solder bump 800 common solder projections of forming; And then described wafer 100 can be connected with external circuitry by described solder projection; The manufacturing of solder bump 800 can be adopted methods such as plating, printing with paste, chemical plating and evaporation; Solder bump 800 materials can be selected the lead-free alloy of PbSn alloy, high lead alloy, tin etc. for use.
Shown in Figure 24 for the structural representation of solder projection the 5th execution mode of the present invention; As shown in figure 24, wafer 100 carried out preliminary treatment after, form pad 200 and protective layer 300 on the wafer; Described protective layer 300 has an open region 400, and described open region 400 is in order to exposed pad 200 surfaces; Because special size requires and rewiring etc. needs, and before barrier layer 710, needs to apply in advance the resilient coating 500 of one deck on protective layer 300; Described resilient coating 500 is in order to discharge the unnecessary stress that occurs in the welding process and can satisfy that special size requires and the needs of rewiring; Described resilient coating 500 has identical open region 400 with protective layer 300; Then on described resilient coating 500, utilize execution mode four described methods successively to form described barrier layer 710, weld layer 720 and solder bump 800; Described pad 200, barrier layer 710, weld layer 720 and the solder bump 800 common solder projections of forming; Described resilient coating 500 materials can be selected the two oxazole dielectric resin material such as (PBO) of polyimides (Polyimide), benzocyclobutene (BCB) or polyparaphenylene's benzo for use; Described resilient coating 500 can form open region by modes such as etchings; Described resilient coating 500 thickness are pressed actual needs and are selected; Described resilient coating 500 can remain in the final electronic system product.
Figure 25 is extremely shown in Figure 26 to be the structural representation of solder projection the 6th execution mode of the present invention; As shown in the figure, before forming barrier layer 710 and weld layer 720, need on described pad 200 and protective layer 300, to apply a photoresist layer 600, and with these photoresist layer 600 patternings to form graph area, the regional area that the graph area of described photoresist layer 600 exposes can be any zone on pad 200 and protective layer 300 surfaces, is not limited only to the area just above of pad 200; The graph area of described non-pad 200 area just above of exposing links to each other by lead-in wire 730 with pad 200; Described lead-in wire 730 materials are Cu; Described lead-in wire 730 adheres on described protective layer 300 or the resilient coating 500; Then in the graph area of described photoresist layer 600, electroplate barrier layer 710 and weld layer 720 on pad 200 and the protective layer 300; After removing photoresist layer 600, apply one deck cushioning layer material in non-graph area lead-in wire is isolated from the outside; Then can form solder projection according to embodiment four and embodiment five described methods, and so as between wafer 100 and external circuitry, forming firm physical connection.
After described solder bump 800 is connected with welding manner and weld layer 720 formation, because the high temperature action during welding, easy and the weld layer 720 material generation chemical reactions generation duplex alloy of solder bump 800 materials, described duplex alloy has stronger diffusivity in weld layer 720, when diffusing to the intersection on weld layer 720 and barrier layer 710, generate triple-phase alloys with barrier layer 710 reactions then; Described duplex alloy and the triple-phase alloys diffusivity in barrier layer 710 a little less than, promptly described barrier layer 710 has protected described duplex alloy and triple-phase alloys can not continue to spread to lower floor with the impurity form.
Shown in Figure 27 for after solder projection forms, the structural representation of barrier layer 710 and weld layer 720 intersection sections; As shown in figure 27, in weld layer 720, gathered certain thickness duplex alloy 810,, had 820 layers of one deck triple-phase alloys at the intersection of weld layer 720 with barrier layer 710 near 710 zones, barrier layer; Described duplex alloy 810 is Cu
6Sn
5, described triple-phase alloys 820 is (CuNi)
6Sn
5
Adopt solder projection disclosed by the invention and manufacture method thereof, UBM layer gross thickness reduces to some extent in the solder projection, the physical property matching is good between Cr/Cu/Ni/Cu, Cr/CrCu/Cu/Ni/Cu, Ti/Cu/Ni/Cu, TiW/Cu/Ni/Cu and Ta/Cu/Ni/Cu multilayer material and between described multilayer material and connector, and the requirement that the volume that has guaranteed described solder projection satisfies overall package guarantees that simultaneously described solder projection can provide reliable physical connection between wafer 100 and external circuitry.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (60)
1. a solder projection is characterized in that, comprising: the pad (200) that forms on wafer (100) surface; The UBM layer (700), barrier layer (710), the weld layer (720) that on described pad (200), form successively; And be formed at solder bump (800) on the described weld layer (720); Described UBM layer (700) has sandwich construction; The orlop of described UBM layer (700) links to each other with pad (200), and its superiors link to each other with barrier layer (710).
2. solder projection according to claim 1 is characterized in that: described pad (200) material is AL or Cu.
3. solder projection according to claim 1 is characterized in that: described UBM layer (700) comprises Cr/Cu, Cr/CrCu/Cu, Ti/Cu, TiW/Cu or the Ta/Cu of layer by layer deposition.
4. solder projection according to claim 2 is characterized in that: described UBM layer (700) is formed on the pad (200).
5. solder projection according to claim 2 is characterized in that: described UBM layer (700) is connected by lead-in wire (730) with pad (200).
6. solder projection according to claim 5 is characterized in that: described lead-in wire (730) material is Cu.
7. according to claim 4 or 5 described solder projections, it is characterized in that: described UBM layer (700) thickness range is 0.3～0.5 micron.
8. solder projection according to claim 1 is characterized in that: described barrier layer (710) material is Ni.
9. solder projection according to claim 8 is characterized in that: described barrier layer (710) thickness range is 1～2 micron.
10. solder projection according to claim 1 is characterized in that: described weld layer (720) material is Cu.
11. solder projection according to claim 10 is characterized in that: described weld layer (720) thickness range is 0.5～3 micron.
12. solder projection according to claim 1 is characterized in that: described solder bump (800) material is a kind of material in the lead-free alloy of PbSn alloy, high lead alloy or tin.
13. a solder projection is characterized in that, comprising: the pad (200) that forms on wafer (100) surface; The barrier layer (710), weld layer (720) and the solder bump (800) that on described pad (200), form successively.
14. solder projection according to claim 13 is characterized in that: described pad (200) material is Cu.
15. solder projection according to claim 13 is characterized in that: described barrier layer (710) material is Ni.
16. solder projection according to claim 15 is characterized in that: described barrier layer (710) thickness range is 1～2 micron.
17. solder projection according to claim 13 is characterized in that: described weld layer (720) material is Cu.
18. solder projection according to claim 17 is characterized in that: described weld layer (720) thickness range is 0.5～3 micron.
19. solder projection according to claim 13 is characterized in that: described solder bump (800) material is a kind of material in the lead-free alloy of PbSn alloy, high lead alloy or tin.
20. a solder projection manufacture method is characterized in that, comprising:
A. go up at wafer (100) and form pad (200) and protective layer (300);
B. go up formation one UBM layer (700) at described pad (200) and protective layer (300);
C. go up at described UBM layer (700) and apply a photoresist layer (600), and the described photoresist layer of patterning (600), in order to form and pad 200 corresponding opening districts (400);
D. in described graph area, UBM layer (700) go up to form a barrier layer (710);
E. in described graph area, barrier layer (710) go up to form weld layer (720);
F. remove described photoresist layer (600), and the described UBM layer of etching (700);
G. go up at described weld layer (720) and form solder bump (800).
21. solder projection manufacture method according to claim 20 is characterized in that: described protective layer (300) has an open region (400), and described open region (400) is in order to exposed pad (200) surface.
22. solder projection manufacture method according to claim 20 is characterized in that: described UBM layer (700) is formed on the pad (200).
23. solder projection manufacture method according to claim 20 is characterized in that: be formed with first resilient coating (500) between described UBM layer (700) and the protective layer (300).
24. solder projection manufacture method according to claim 23 is characterized in that: described UBM layer (700) is connected by lead-in wire (730) with pad (200), and described lead-in wire (730) adheres on described protective layer (300) or first resilient coating (500); Described lead-in wire (730) is isolated in the external world by second resilient coating (500).
25. solder projection manufacture method according to claim 24 is characterized in that: described lead-in wire (730) material is Cu.
26. solder projection manufacture method according to claim 25 is characterized in that: described first resilient coating (500) has the open region (400) identical with protective layer (300) and is covered in fully on the described protective layer (300).
27. solder projection manufacture method according to claim 21 is characterized in that: described open region (400) forms by the etching mode.
28. solder projection manufacture method according to claim 24 is characterized in that: described UBM layer (700) material is Cr/Cu, Cr/CrCu/Cu, Ti/Cu, TiW/Cu or Ta/Cu.
29. solder projection manufacture method according to claim 25 is characterized in that: described resilient coating (500) material is an insulating material.
30. solder projection manufacture method according to claim 29 is characterized in that: described insulating material is the two oxazoles (PBO) of polyimides (Polyimide), benzocyclobutene (BCB) or polyparaphenylene's benzo etc.
31. solder projection manufacture method according to claim 28 is characterized in that: described UBM layer (700) forms by sputtering method.
32. solder projection manufacture method according to claim 31 is characterized in that: described UBM layer (700) thickness range is 0.3～0.5 micron.
33. solder projection manufacture method according to claim 20 is characterized in that: described photoresist layer (600) thickness is 5～10 microns.
34. solder projection manufacture method according to claim 20 is characterized in that: the local UBM layer (700) that the graph area of described photoresist layer (600) exposes is any zone on UBM layer (700) surface.
35. solder projection manufacture method according to claim 20 is characterized in that: the local UBM layer (700) that the graph area of described photoresist layer (600) exposes is the area just above of pad (200).
36. solder projection manufacture method according to claim 20 is characterized in that: described barrier layer (710) material is Ni.
37. solder projection manufacture method according to claim 36 is characterized in that: described barrier layer (710) thickness range is 1～2 micron.
38. according to the described solder projection manufacture method of claim 37, it is characterized in that: described barrier layer (710) form by electro-plating method.
39. solder projection manufacture method according to claim 20 is characterized in that: described weld layer (720) material is Cu.
40. according to the described solder projection manufacture method of claim 39, it is characterized in that: described weld layer (720) thickness range is 0.5～3 micron.
41. according to the described solder projection manufacture method of claim 40, it is characterized in that: described weld layer (720) forms by electro-plating method.
42. solder projection manufacture method according to claim 20 is characterized in that: the method for the described UBM layer of etching (700) is the dry etching method.
43. solder projection manufacture method according to claim 20 is characterized in that: described solder bump (800) material is a kind of material in the lead-free alloy of PbSn alloy, high lead alloy or tin.
44. a solder projection manufacture method is characterized in that, comprising:
A. go up at wafer (100) and form pad (200) and protective layer (300);
B. go up coating one photoresist layer (600) and patterning at described pad (200) and protective layer (300), in order to form and pad (200) corresponding opening district (400);
C. in described open region (400), pad (200) and protective layer (300) go up and form a barrier layer (710);
D. in described open region (400), barrier layer (710) go up to form weld layer (720);
E. remove described photoresist layer (600);
F. go up at described weld layer (720) and form solder bump (800).
45. according to the described solder projection manufacture method of claim 44, it is characterized in that: described protective layer (300) has an open region (400), described open region (400) is in order to exposed pad (200) surface.
46., it is characterized in that: be formed with first resilient coating (500) between described photoresist layer (600) and pad (200) and the protective layer (300) according to the described solder projection manufacture method of claim 44.
47. according to the described solder projection manufacture method of claim 46, it is characterized in that: described barrier layer (710) are connected by lead-in wire (730) with pad (200), and described lead-in wire (730) adheres on described protective layer (300) or first resilient coating (500); Described lead-in wire (730) is isolated in the external world by second resilient coating (500).
48. according to the described solder projection manufacture method of claim 47, it is characterized in that: described lead-in wire (730) material is Cu.
49. according to the described solder projection manufacture method of claim 46, it is characterized in that: described first resilient coating (500) has the open region (400) identical with protective layer (300) and is covered in fully on the described protective layer (300).
50. according to the described solder projection manufacture method of claim 45, it is characterized in that: described open region (400) forms by the etching mode.
51. according to the described solder projection manufacture method of claim 47, it is characterized in that: described resilient coating (500) material is an insulating material.
52. according to the described solder projection manufacture method of claim 51, it is characterized in that: described insulating material is the two oxazoles (PBO) of polyimides (Polyimide), benzocyclobutene (BCB) or polyparaphenylene's benzo etc.
53. according to the described solder projection manufacture method of claim 44, it is characterized in that: described photoresist layer (600) thickness is 5～10 microns.
54. according to the described solder projection manufacture method of claim 44, it is characterized in that: described barrier layer (710) material is Ni.
55. according to the described solder projection manufacture method of claim 52, it is characterized in that: described barrier layer (710) thickness range is 1～2 micron.
56. according to the described solder projection manufacture method of claim 55, it is characterized in that: described barrier layer (710) form by electro-plating method.
57. according to the described solder projection manufacture method of claim 44, it is characterized in that: described weld layer (720) material is Cu.
58. according to the described solder projection manufacture method of claim 52, it is characterized in that: described weld layer (720) thickness range is 0.5～3 micron.
59. according to the described solder projection manufacture method of claim 58, it is characterized in that: described weld layer (720) forms by electro-plating method.
60. according to the described solder projection manufacture method of claim 44, it is characterized in that: described solder bump (800) material is a kind of material in the lead-free alloy of PbSn alloy, high lead alloy or tin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100275885A CN100517671C (en) | 2006-06-12 | 2006-06-12 | Solder lug and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100275885A CN100517671C (en) | 2006-06-12 | 2006-06-12 | Solder lug and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101090099A true CN101090099A (en) | 2007-12-19 |
| CN100517671C CN100517671C (en) | 2009-07-22 |
Family
ID=38943356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100275885A Expired - Fee Related CN100517671C (en) | 2006-06-12 | 2006-06-12 | Solder lug and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100517671C (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102218577A (en) * | 2011-05-09 | 2011-10-19 | 三星半导体(中国)研究开发有限公司 | Magnetic columnar welding pan structure of induction heating soldering and welding method |
| CN102403290A (en) * | 2010-09-10 | 2012-04-04 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for fabricating semiconductor device |
| CN102437065A (en) * | 2011-12-19 | 2012-05-02 | 南通富士通微电子股份有限公司 | High-reliability chip scale packaging method |
| CN102437066A (en) * | 2011-12-19 | 2012-05-02 | 南通富士通微电子股份有限公司 | High-reliability wafer-level columnar bump packaging method |
| CN102446780A (en) * | 2011-12-19 | 2012-05-09 | 南通富士通微电子股份有限公司 | Wafer-level packaging method |
| CN101894766B (en) * | 2009-05-22 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing solder lug |
| CN102496605A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Wafer level packaging structure |
| CN102496584A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Method for forming solder bump |
| CN102496585A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Novel wafer level packaging method |
| CN102496606A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | High-reliability wafer level cylindrical bump packaging structure |
| CN102496580A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Method for forming solder bump |
| CN102005396B (en) * | 2009-08-28 | 2012-12-05 | 中芯国际集成电路制造(上海)有限公司 | Bump making method and bump structure |
| CN103258805A (en) * | 2013-04-17 | 2013-08-21 | 南通富士通微电子股份有限公司 | Semiconductor device chip scale package structure |
| CN103681558A (en) * | 2012-09-03 | 2014-03-26 | 矽品精密工业股份有限公司 | Connection structure in semiconductor package |
| CN104201118A (en) * | 2014-08-26 | 2014-12-10 | 南通富士通微电子股份有限公司 | Chip level packaging method |
| CN104332418A (en) * | 2014-08-26 | 2015-02-04 | 南通富士通微电子股份有限公司 | Chip-level packaging method |
| CN104465574A (en) * | 2013-09-12 | 2015-03-25 | 中国科学院金属研究所 | Bump packaging structure with FeP alloy acting as soldering layer |
| CN106129038A (en) * | 2016-07-14 | 2016-11-16 | 成都芯源系统有限公司 | Integrated circuit chip and manufacturing method thereof |
| CN118412389A (en) * | 2024-07-01 | 2024-07-30 | 陕西迪泰克新材料有限公司 | Welding electrode structure for tellurium-zinc-cadmium crystal/cadmium telluride crystal and preparation method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102496603A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Chip level packaging structure |
-
2006
- 2006-06-12 CN CNB2006100275885A patent/CN100517671C/en not_active Expired - Fee Related
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101894766B (en) * | 2009-05-22 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing solder lug |
| CN102005396B (en) * | 2009-08-28 | 2012-12-05 | 中芯国际集成电路制造(上海)有限公司 | Bump making method and bump structure |
| CN102403290A (en) * | 2010-09-10 | 2012-04-04 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for fabricating semiconductor device |
| CN102218577B (en) * | 2011-05-09 | 2016-08-03 | 三星半导体(中国)研究开发有限公司 | The magnetic column pad structure of induction brazing and welding method |
| CN102218577A (en) * | 2011-05-09 | 2011-10-19 | 三星半导体(中国)研究开发有限公司 | Magnetic columnar welding pan structure of induction heating soldering and welding method |
| CN102496580B (en) * | 2011-12-19 | 2016-02-03 | 南通富士通微电子股份有限公司 | A kind of formation method of solder bump |
| CN102437066A (en) * | 2011-12-19 | 2012-05-02 | 南通富士通微电子股份有限公司 | High-reliability wafer-level columnar bump packaging method |
| CN102496584A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Method for forming solder bump |
| CN102496585A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Novel wafer level packaging method |
| CN102496606A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | High-reliability wafer level cylindrical bump packaging structure |
| CN102496580A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Method for forming solder bump |
| CN102446780A (en) * | 2011-12-19 | 2012-05-09 | 南通富士通微电子股份有限公司 | Wafer-level packaging method |
| CN102437065A (en) * | 2011-12-19 | 2012-05-02 | 南通富士通微电子股份有限公司 | High-reliability chip scale packaging method |
| CN102496605A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Wafer level packaging structure |
| CN103681558A (en) * | 2012-09-03 | 2014-03-26 | 矽品精密工业股份有限公司 | Connection structure in semiconductor package |
| CN103258805B (en) * | 2013-04-17 | 2015-11-25 | 南通富士通微电子股份有限公司 | semiconductor device chip scale package structure |
| CN103258805A (en) * | 2013-04-17 | 2013-08-21 | 南通富士通微电子股份有限公司 | Semiconductor device chip scale package structure |
| CN104465574A (en) * | 2013-09-12 | 2015-03-25 | 中国科学院金属研究所 | Bump packaging structure with FeP alloy acting as soldering layer |
| CN104465574B (en) * | 2013-09-12 | 2017-09-26 | 中国科学院金属研究所 | It is a kind of that the bump packaging structure for connecing layer is used as using FeP alloys |
| CN104201118A (en) * | 2014-08-26 | 2014-12-10 | 南通富士通微电子股份有限公司 | Chip level packaging method |
| CN104332418A (en) * | 2014-08-26 | 2015-02-04 | 南通富士通微电子股份有限公司 | Chip-level packaging method |
| CN104332418B (en) * | 2014-08-26 | 2017-05-24 | 通富微电子股份有限公司 | Chip-level packaging method |
| CN106129038A (en) * | 2016-07-14 | 2016-11-16 | 成都芯源系统有限公司 | Integrated circuit chip and manufacturing method thereof |
| CN118412389A (en) * | 2024-07-01 | 2024-07-30 | 陕西迪泰克新材料有限公司 | Welding electrode structure for tellurium-zinc-cadmium crystal/cadmium telluride crystal and preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100517671C (en) | 2009-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100517671C (en) | Solder lug and manufacturing method thereof | |
| JP3210547B2 (en) | Electroplating solder terminal and method of manufacturing the same | |
| CN101138084B (en) | Semiconductor device package with bump overlying a polymer layer | |
| US8742580B2 (en) | Method of wire bonding over active area of a semiconductor circuit | |
| KR100339190B1 (en) | Barrier layers for electroplated snpb eutectic solder joints | |
| CN102148201B (en) | Semiconductor element, packaging structure and forming method of semiconductor element | |
| KR100772920B1 (en) | Semiconductor chip with solder bump and fabrication method thereof | |
| US20080169539A1 (en) | Under bump metallurgy structure of a package and method of making same | |
| US7906425B2 (en) | Fluxless bumping process | |
| US20080050905A1 (en) | Method of manufacturing semiconductor device | |
| US20080251927A1 (en) | Electromigration-Resistant Flip-Chip Solder Joints | |
| US9373596B2 (en) | Passivated copper chip pads | |
| CN105390473A (en) | Integrated circuit device and packaging assembly | |
| KR20040012877A (en) | Semiconductor device and its production method | |
| CN102237317A (en) | Integrated circuit element and packaging component | |
| CN102222647A (en) | Semiconductor die and method of manufacturing semiconductor feature | |
| US8367543B2 (en) | Structure and method to improve current-carrying capabilities of C4 joints | |
| US20080251916A1 (en) | UBM structure for strengthening solder bumps | |
| US9711472B2 (en) | Solder bump for ball grid array | |
| US6774026B1 (en) | Structure and method for low-stress concentration solder bumps | |
| CN100474542C (en) | Method for forming conduction protruding block and structure of the conduction protruding block | |
| CN105097746A (en) | Nano twin copper-based under bump metal layer and preparation method thereof | |
| CN101194361A (en) | Layer sequence and method of manufacturing a layer sequence | |
| CN100541751C (en) | Crystal circle structure and forming method thereof | |
| CN102496603A (en) | Chip level packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111109 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation Effective date of registration: 20111109 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090722 Termination date: 20190612 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |