CN102496606A - High-reliability wafer level cylindrical bump packaging structure - Google Patents
High-reliability wafer level cylindrical bump packaging structure Download PDFInfo
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- CN102496606A CN102496606A CN201110428864XA CN201110428864A CN102496606A CN 102496606 A CN102496606 A CN 102496606A CN 201110428864X A CN201110428864X A CN 201110428864XA CN 201110428864 A CN201110428864 A CN 201110428864A CN 102496606 A CN102496606 A CN 102496606A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
Abstract
The invention discloses a high-reliability wafer level cylindrical bump packaging structure which comprises a chip, a cylinder, a protection glue and a solder bump, wherein a bonding pad and a passivation layer are arranged on the upper surface of the chip; the passivation layer is coated on the upper surface, beyond the chip, of the bonding pad; the cylinder is arranged on the bonding pad and comprises a heat-resistant metal layer, a metal infiltration layer, an attachment layer and a connecting layer in turn from bottom to top; the protection glue is coated on the surface, at which the bonding pad is positioned, of the chip and is filled in the cylinder; the upper surface of the protection glue is level with the top of the cylinder; and the solder bump is arranged on the top of the cylinder, namely the upper surface of the blocking layer. According to the invention, the electrical performance and reliability of a product are improved, and the structure is suitable for the wafer level package with close bonding pad distance and multiple output functions.
Description
Technical field
The present invention relates to the semiconductor packages field, relate in particular to disc grade chip size encapsulation (Wafer Level chip Scale Package, encapsulating structure WLCSP).
Background technology
In recent years, because the microcircuit of chip is made towards the high integration development, therefore, its Chip Packaging also needs to develop to high power, high density, direction frivolous and microminiaturization.Chip Packaging is exactly after chip manufacturing is accomplished, with materials such as plastic cement or Tao Ci, chip to be wrapped in wherein, to reach the protection chip, makes chip not damaged by extraneous steam and mechanicalness.The main function of Chip Packaging has electric energy to transmit (Power Distribution) respectively, signal transmits (Signal Distribution), heat abstraction (Heat Dissipation) and protection support (Protection and Support).
Because the requirement of electronic product now is compact and high integration, therefore can makes and the production of integrated circuits miniaturization cause the logic that comprises in the chip to increase; And further make chip I/O (input/output) pin number increase; And be to cooperate these demands, produced many different packaged types, for example; BGA Package (Ball grid array; BGA), chip size packages (Chip Scale Package, CSP), multi-chip module encapsulation (Multi Chip Module package, MCM package), flip-over type encapsulation (Flip Chip Package), coil type encapsulation (Tape Carrier Package; TCP) and wafer level packaging (Wafer Level Package, WLP) etc.
No matter with the method for packing of which kind of form, most method for packing all is disk to be separated into independently accomplish the program that encapsulates again behind the chip.And wafer level packaging is a trend in the method for packaging semiconductor; Wafer level packaging is an encapsulated object with the full wafer disk; Thereby packaging and testing all need do not cutting the preceding completion of disk as yet; Be the encapsulation technology that a kind of height is integrated, so can save making such as filler, assembling, glutinous crystalline substance and routing, therefore can reduce cost of labor in a large number and shorten manufacturing time.
The existing technology that forms the disc grade chip size encapsulation is shown in Fig. 1 to 5.At first please, on disk 10, has at least one chip 100 with reference to Figure 1A.
Shown in Figure 1B, on chip 100, dispose metal bed course 104 and passivation layer 102 in order to protect chip 100 surfaces and metal bed course 104 is exposed; On passivation layer 102 and metal bed course 104, form the first metal layer 106 through sputter or evaporation process; The effect of the first metal layer 106 is protection metal bed courses 104 in follow-up reflux technique, and the first metal layer 106 can be constituting of a kind of among Al, Ni, Cu, Ti, Cr, Au, the Pd or they.
Then please with reference to Fig. 1 C; On the first metal layer 106, form photoresist layer 107; Define metal bed course 104 shapes through existing photoetching technique, make public then, developing process, in photoresist layer 107, form the first metal layer 106 on the metal bed course 104 that opening exposes lower floor; With photoresist layer 107 is mask, and shape second metal level 108 on the first metal layer 106 in opening, the material of said second metal level 108 are that Cu, Ni or its constitute, and the method for said formation second metal level 108 is galvanoplastic.
With reference to figure 1D, wet method is removed photoresist layer 107; Etching the first metal layer 106 is to exposing passivation layer 102, makes the first metal layer 106a and second metal level 108 after the etching constitute ubm layer 108a; On second metal level 108, form scaling powder 109 with the steel mesh print process.
Shown in Fig. 1 E, on scaling powder 109, place prefabricated solder ball, insulation refluxes in reflow ovens then, forms salient point 110.
Carry out the singulation cutting step at last, with each chip 100 singulation on the disk 10.
, application number also announced more heterogeneous pass information in being 200510015208.1 one Chinese patent application.
Prior art forms in the disc grade chip size encapsulation process, because the solder bump material directly contacts with metal infiltrating layer, the copper-base of metal infiltrating layer is prone to be diffused in the tin of solder bump and forms signal bronze, influences welding quality.Simultaneously, before forming scolder on the metal infiltrating layer, the exposed easy oxidation of soakage layer and the solder bump performance of follow-up formation and reliability are reduced.On the other hand, in the forming process of solder bump, easy drippage and influence reliability of products between scolder especially for the intensive product of metal gasket, problem of short-circuit between solder bump occurs more easily.
Summary of the invention
The problem that the present invention solves provides a kind of highly reliable wafer level column salient point encapsulating structure, prevents that chip electrical property and reliability from reducing.
For addressing the above problem, the present invention provides a kind of highly reliable wafer level column salient point encapsulating structure, comprises chip, cylinder, protection glue and solder bump; The upper surface of said chip is provided with pad and passivation layer, and said passivation layer is overlying on the upper surface beyond the chip bonding pad opening; Said pad is provided with cylinder, and said cylinder up comprises heat resistant metal layer, metal infiltrating layer, adhesion layer and barrier layer successively by the bottom; Said protection glue is overlying on the chip surface at pad place and is filled between cylinder, and the upper surface of protection glue flushes with the top of cylinder; The top of said cylinder is that the upper surface on barrier layer is provided with solder bump.
Alternatively, the material of said heat resistant metal layer is titanium, chromium, tantalum or their combination.
Alternatively, the material of said metal infiltrating layer is copper, aluminium, nickel or their combination.
Alternatively, the material of said adhesion layer is a copper.
Alternatively, the thickness of said copper adhesion layer is 50～100 μ m.
Alternatively, the material on said barrier layer is a nickel.
Alternatively, the thickness on said nickel barrier layer is 1.5～3 μ m.
Alternatively, the material of said protection glue is an epoxy resin.
Alternatively, the material of said solder bump is pure tin or ashbury metal.
Alternatively, the thickness of said solder bump is 10～70 μ m.
Compared with prior art, in the encapsulating structure that the present invention forms:
Adhesion layer (Cu) spatially provides enough material space, solder bump can be placed on the adhesion layer securely and can not depart from; Also just because of the column structure that metal levels such as adhesion layer constitute makes the size of solder bump be able to dwindle; In guaranteeing the final products welding process under the prerequisite of physical connection reliability; Promote the function number outbound port number in the unit space, more can satisfy the close spacing of chip bonding pad, the many package requirements of function output.
Can avoid self disappearing because of diffusion effect on the one hand in the suitable barrier layer (Ni) of thickness, and then the hole that stops between scolder and the adhesion layer formation because of intermetallic compound to produce effectively; Be unlikely to simultaneously to cause resistivity to rise again and influence the electric heating property of product because of the nickel barrier layer is blocked up.
Protection glue is partly built the cylinder that metal levels such as adhesion layer in this encapsulating structure constitute, and has not only strengthened the physical structure of cylinder, and main is avoids the drippage of scolder in the follow-up formation solder bump process and cause the short circuit between cylinder.
Description of drawings
Figure 1A to Fig. 1 E is the process sketch map of existing wafer-level encapsulation method;
Fig. 2 is the sketch map of the highly reliable wafer level column of the present invention salient point encapsulating structure;
Fig. 3 is the embodiment flow chart that the present invention forms highly reliable wafer level column salient point encapsulating structure;
Fig. 4 A to Fig. 4 H is the process schematic representation that the present invention forms the embodiment of highly reliable wafer level column salient point packaging mechanism.
Embodiment
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Fig. 2 is the sketch map of the highly reliable wafer level column of the present invention salient point encapsulating structure, and said encapsulating structure comprises: chip 300, cylinder, protection glue 307 and solder bump 308; The upper surface of said chip 300 is provided with pad 301 and passivation layer 302, and said passivation layer 302 is overlying on the upper surface beyond chip 300 pads 301 openings; Said pad 301 is provided with cylinder; Said cylinder up comprises heat resistant metal layer 303, metal infiltrating layer 304, adhesion layer 306a and barrier layer 306b successively by the bottom; Wherein the material of heat resistant metal layer 303 is titanium, chromium, tantalum or their combination; The material of metal infiltrating layer 304 is copper, aluminium, nickel or their combination, and adhesion layer 306a is that thickness is the copper layer of 50～100 μ m, and barrier layer 306b is that thickness is the nickel dam of 1.5 μ m～3 μ m; Said protection glue 307 is overlying on chip 300 surfaces at pad 301 places and is filled between cylinder, and the upper surface of protection glue 307 flushes with the top of cylinder, and the material of protection glue 307 is an epoxy resin; The top of said cylinder is that the upper surface of barrier layer 306b is provided with solder bump 308, and said solder bump 308 is that thickness is 10～70 μ m, and corresponding material is pure tin or ashbury metal, like sn-ag alloy, gun-metal, SAC alloy etc.
In the above-mentioned encapsulating structure, cylinder spatially provides enough material space, solder bump can be placed on the cylinder securely and can not depart from; Also just because of the column structure that is made up of metal levels such as articulamentums makes the size of solder bump be able to dwindle; In guaranteeing the final products welding process under the prerequisite of physical connection reliability; Promote the function number outbound port number in the unit space, more can satisfy the close spacing of chip bonding pad, the many package requirements of function output.
In the cylinder then can avoid self disappearing because of diffusion effect in the suitable nickel barrier layer of thickness, and then the hole that stops between scolder and the adhesion layer formation because of intermetallic compound to produce effectively; Be unlikely to simultaneously to cause resistivity to rise again and influence the electric heating property of product because of the nickel barrier layer is blocked up.
Protection glue is built cylinder and is filled between cylinder, has not only strengthened the physical structure of cylinder, and main is avoids the drippage of scolder in the follow-up formation solder bump process and cause the electrical short circuit between cylinder.
For further specifying the advantage of encapsulating structure of the present invention, encapsulating structure of the present invention is done further to introduce below in conjunction with a concrete method for packing embodiment.
Fig. 3 is the embodiment flow chart that the present invention forms highly reliable wafer level column salient point encapsulation, comprises step:
S101 forms heat resistant metal layer and metal infiltrating layer successively on bonding pads and passivation layer;
S102 forms photoresist on metal infiltrating layer, said photoresist is provided with the metal infiltrating layer that opening exposes the chip bonding pad top;
S103 forms articulamentum on the metal infiltrating layer in above-mentioned opening, and said articulamentum comprises adhesion layer and the barrier layer that forms successively;
S104 removes photoresist;
S105, heat resistant metal layer on the etch passivation layer and metal infiltrating layer to passivation layer is exposed;
S106 forms the protection glue-line on chip, said protection glue covers articulamentum;
S107 grinds the protection glue-line, makes the barrier layer in the articulamentum exposed;
S108 forms solder bump and backflow on the barrier layer.
At first execution in step S101 forms heat resistant metal layer and metal infiltrating layer successively on bonding pads and passivation layer, forms the structure shown in Fig. 4 A.
In this step, chip 300 is provided with pad 301 and passivation layer 302, and pad 301 is function lead-out terminals of chip 300, and finally realizes the conduction transition of electrical functionality through the solder bump 308 of follow-up formation; The material of passivation layer 302 comprises dielectric material or their mixtures such as silica, silicon nitride, silicon oxynitride, polyimides, benzene three polybutene, is used for protecting the circuit of chip 300.
Need to prove that said bonding pads and passivation layer can be the initial pad and the initial passivation of chip, also can be transition pad, the passivation layer that forms according to circuit layout-design needs; The mode that forms transition pad, passivation layer mainly is to adopt the Wiring technique technology again, connects up through one or more layers again initial pad, passivation layer are reprinted on transition pad, the passivation layer.The said technology of Wiring technique again has been well known to those skilled in the art for existing maturation process, repeats no more at this.
In the present embodiment, the material of said heat resistant metal layer 303 can be constituting of titanium Ti, chromium Cr, tantalum Ta or they, and the present invention is preferably Ti.The material of said metal infiltrating layer 304 can be constituting of a kind of in copper Cu, aluminium Al, the nickel or they, and wherein more excellent metal infiltrating layer 304 is Cu.Heat resistant metal layer 303 constitutes the Seed Layer of final structure with metal infiltrating layer 304.The method of said heat resistant metal layer 303 and metal infiltrating layer 304 can adopt the method for existing evaporation or sputter or physical vapour deposition (PVD) equally, and wherein more excellent method is sputter.Certainly; Common practise according to those skilled in the art; The method that forms is not limited only to sputtering method, and other methods that are suitable for all can be applicable to the present invention, and the thickness of heat resistant metal layer 303 that forms and metal infiltrating layer 304 also is to decide according to the process requirements of reality.
Implementation step S102 forms photoresist on metal infiltrating layer then, and said photoresist is provided with the metal infiltrating layer that opening exposes the chip bonding pad top, forms the structure shown in Fig. 4 B.
In this step, the method that forms photoresist 305 can be a rotary coating, and the concrete steps of these methods are well known to those skilled in the art, repeat no more at this.After forming photoresist 305, specifically can define the shape of pad 301, make to form opening in the photoresist 305 to expose the metal infiltrating layer 304 on the pad 301 through existing photoetching development technology.
Implementation step S103 forms articulamentum on the metal infiltrating layer in above-mentioned opening then, and said articulamentum comprises adhesion layer and the barrier layer that forms successively, forms the structure shown in Fig. 4 C.
In this step; With remaining photoresist 305 on the chip 300 is mask; In the opening of the photoresist 305 that in last step, formed, metal infiltrating layer 304 above, form adhesion layer 306a and barrier layer 306b successively, the material of said adhesion layer 306a is copper Cu; The material of barrier layer 306b is a nickel, and adhesion layer 306a and barrier layer 306b have constituted articulamentum 306.The concrete technology that forms articulamentum 306 can be through with the mode of electroplating, and certain, according to those skilled in the art's common practise, the method for formation is not limited only to electroplate, and other methods that are suitable for all can be applicable to the present invention.
In the present embodiment, the thickness of adhesion layer 306a copper is 50～100 μ m, and concrete thickness is 50 μ m, 55 μ m, 60 μ m, 65 μ m, 70 μ m, 75 μ m, 80 μ m, 85 μ m, 90 μ m, 95 μ m or 100 μ m etc.Adhesion layer 306a is the column structure main body of column salient point for final electrically lead-out terminal.Adhesion layer 306a spatially provides enough material space, has guaranteed that follow-up solder bump 308 can place adhesion layer 306a to go up securely and can not depart from, and has also improved simultaneously and the adhesion of 308 of solder bumps.
In the present embodiment, the thickness of barrier layer 306b nickel is 1.5 μ m～3 μ m, and concrete thickness is 1.5 μ m, 2 μ m, 2.5 μ m or 3 μ m etc.Barrier layer 306b act as among diffuse to the copper adhesion layer 306a that prevents follow-up formation solder bump 308, and when Ni layer thickness during less than 1.5 μ m, Ni finally can disappear because of the diffusion effect between adjacent metal, and then can't play barrier effect; When Ni layer thickness during, can cause the resistivity rising because of the electric heating property of Ni metal itself is relatively poor, and then influence the electric heating property of final products greater than 3 μ m.
Implementation step S104 removes photoresist then, forms the structure shown in Fig. 4 D.
After accomplishing above-mentioned operation, photoresist 305 can have been removed, and can use wet method or the mode peeled off is removed, and the concrete steps of these methods are well known to those skilled in the art, repeat no more at this.
Follow implementation step S105, heat resistant metal layer on the etch passivation layer and metal infiltrating layer to passivation layer is exposed, forms the structure shown in Fig. 4 E.
In this step, specifically can be through spraying acid solution or wafer the method in the acid solution of being soaked in being removed the metal infiltrating layer 304 and heat resistant metal layer 303 on chip 300 surfaces beyond the articulamentum 306.
Implementation step S106 forms the protection glue-line on chip then, and said protection glue covers articulamentum, forms the structure shown in Fig. 4 F.
In this step, the method that forms protection glue 307 can be modes such as printing, spin coating, and the concrete steps of these methods have been well known to those skilled in the art, repeat no more at this.After forming protection glue 307, can solidify 307 layers in protection glue through the mode of baking.
In the present embodiment, chip 300 surfaces and articulamentum 306 are all covered by protection glue 307, have both protected passivation layer 302, the firm again physical structure of column articulamentum 306; Simultaneously, the material of protection glue 307 is an epoxy resin, can releasing chips 300 and the multiple layer metal interlayer because of thermal dilation difference cause stress-retained, and then promoted the reliability of whole encapsulating structure; In addition, filled by protection glue 307 between each column structure, can avoid that the drippage because of scolder causes the short circuit between cylinder in follow-up solder bump 308 forming processes.
Implementation step S107 grinds the protection glue-line then, makes the barrier layer in the articulamentum exposed, forms the structure shown in Fig. 4 G.
In this step, in order to make articulamentum 306 ports exposed, grind 307 layers in protection glue with electrical transfer function, make the 306b surface, barrier layer in the articulamentum 306 be able to expose.
In the present embodiment, be beneficial to the solder bond of 308 of follow-up and solder bumps, after grinding 307 layers in protection glue, exposed 306b surface, barrier layer carried out microetch is handled or plasma cleans in order to make barrier layer 306b surface cleaning.
At last, implementation step S108 forms solder bump and refluxes the structure of formation shown in Fig. 4 H on the barrier layer.
In this step; The method that on the 306b of barrier layer, forms solder bump 308 can be printing soldering paste or will the direct implantation of prefabricated solder ball etc. mode; Form final solder bump 308 through the humidifying reflux technique again; The concrete steps of these methods are known by those skilled in the art of the present technique, repeat no more at this.
In the present embodiment, the thickness of solder bump 308 is 10～70 μ m, and concrete thickness is 10 μ m, 15 μ m, 20 μ m, 25 μ m, 30 μ m, 35 μ m, 40 μ m, 45 μ m, 50 μ m, 55 μ m, 60 μ m, 65 μ m or 70 μ m etc.The material of solder bump 308 is pure tin or ashbury metal, like sn-ag alloy, gun-metal, SAC alloy etc.By the column structure characteristic in above-mentioned the encapsulating structure, solder bump 308 sizes of formation are less, practiced thrift material cost on the one hand, the more important thing is the application demand that can satisfy greater functionality output point in pad 301 close spacings or the same space.
So far, that is to say, up form from pad 301 bottoms and comprise heat resistant metal layer 303, metal infiltrating layer 304, adhesion layer 306a, barrier layer 306b and solder bump 308; Between the column that wherein constitutes by heat resistant metal layer 303, metal infiltrating layer 304, adhesion layer 306a and barrier layer 306b by protection glue 307 fill with improve the product whole reliability can, finally realized by pad 301 to 308 encapsulation transition of electrically transmitting of solder bump.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. a highly reliable wafer level column salient point encapsulating structure is characterized in that: comprise chip, cylinder, protection glue and solder bump; The upper surface of said chip is provided with pad and passivation layer, and said passivation layer is overlying on the upper surface beyond the chip bonding pad opening; Said pad is provided with cylinder, and said cylinder up comprises heat resistant metal layer, metal infiltrating layer, adhesion layer and barrier layer successively by the bottom; Said protection glue is overlying on the chip surface at pad place and is filled between cylinder, and the upper surface of protection glue flushes with the top of cylinder; The top of said cylinder is that the upper surface on barrier layer is provided with solder bump.
2. a kind of highly reliable wafer level column salient point encapsulating structure according to claim 1 is characterized in that the material of said heat resistant metal layer is titanium, chromium, tantalum or their combination.
3. a kind of highly reliable wafer level column salient point encapsulating structure according to claim 1 is characterized in that the material of said metal infiltrating layer is copper, aluminium, nickel or their combination.
4. a kind of highly reliable wafer level column salient point encapsulating structure according to claim 1 is characterized in that the material of said adhesion layer is a copper.
5. a kind of highly reliable wafer level column salient point encapsulating structure according to claim 4 is characterized in that the thickness of said copper adhesion layer is 50～100 μ m.
6. a kind of highly reliable wafer level column salient point encapsulating structure according to claim 1 is characterized in that the material on said barrier layer is a nickel.
7. a kind of highly reliable wafer level column salient point encapsulating structure according to claim 6 is characterized in that the thickness on said nickel barrier layer is 1.5～3 μ m.
8. a kind of highly reliable wafer level column salient point encapsulating structure according to claim 1 is characterized in that the material of said protection glue is an epoxy resin.
9. a kind of highly reliable wafer level column salient point encapsulating structure according to claim 1 is characterized in that the material of said solder bump is pure tin or ashbury metal.
10. a kind of highly reliable wafer level column salient point encapsulating structure according to claim 9 is characterized in that the thickness of said solder bump is 10～70 μ m.
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| US9559044B2 (en) | 2013-06-25 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with solder regions aligned to recesses |
| CN104465573A (en) * | 2013-09-12 | 2015-03-25 | 中国科学院金属研究所 | Columnar bump packaging structure with FeNi alloy or FeNiP alloy acting as reaction interface layer |
| US9515010B2 (en) | 2014-02-24 | 2016-12-06 | Nantong Fujitsu Microelectronics., Ltd. | Semiconductor packaging structure and forming method therefor |
| WO2015123952A1 (en) * | 2014-02-24 | 2015-08-27 | 南通富士通微电子股份有限公司 | Semiconductor packaging structure and forming method therefor |
| CN103903989A (en) * | 2014-02-24 | 2014-07-02 | 南通富士通微电子股份有限公司 | Method for forming semiconductor packaging structure |
| CN103943583A (en) * | 2014-04-14 | 2014-07-23 | 宁波芯健半导体有限公司 | Wafer level packaging structure for wafer level convex blocks of laminated chips |
| CN104201121A (en) * | 2014-09-17 | 2014-12-10 | 北京理工大学 | Method for forming copper pillar and bump package structure |
| CN104992936A (en) * | 2015-05-19 | 2015-10-21 | 南通富士通微电子股份有限公司 | Wafer level chip packaging structure |
| CN105609484A (en) * | 2015-12-24 | 2016-05-25 | 南通富士通微电子股份有限公司 | Semiconductor device fan-out packaging structure |
| CN105609484B (en) * | 2015-12-24 | 2019-03-22 | 通富微电子股份有限公司 | Semiconductor devices fan-out packaging structure |
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