CN201859866U

CN201859866U - Semiconductor packaging device

Info

Publication number: CN201859866U
Application number: CN 201020579215
Authority: CN
Inventors: 胡迪群
Original assignee: Individual
Current assignee: Individual
Priority date: 2010-10-27
Filing date: 2010-10-27
Publication date: 2011-06-08
Anticipated expiration: 2020-10-27

Abstract

A semiconductor packaging device comprises a semiconductor device, a metal layer, a second dielectric layer and a solder bump. The metal layer mainly includes an adhesion layer, a conductive layer and a protective layer, wherein the adhesion layer is capable of adhering substrates and a subsequent metal layer, and the protective layer is capable of protecting a solder-ability surface and preventing the conductive layer from being oxidized. Accordingly, the equipment cost for additionally assembling under bump metal structural layer can be saved, the metal layer in the structure can be directly used as an under bump metal structural layer, and the structure of the semiconductor packaging device is also simpler. Compared with the prior art, the semiconductor packaging device has the advantages that the more simplified X/Cu/Sn metal layer structure can be provided, no extra barrier layer is needed, the number of layers is decreased, a better circuit structure is obtained, manufacture procedures can be simplified, productivity is improved, and cost is reduced effectively.

Description

Semiconductor encapsulation device

Technical field

The utility model relates to a kind of semiconductor encapsulation device, especially refer to a kind of directly the use as structured metal layer under the projection and the tool number of plies is few and be the structure of X/Cu/Sn metal level with the metal level in the structure, be meant to have preferable circuit structure especially, and reach the purpose that effectively reduces cost when can improve productivity ratio in simplifying processing procedure.

Background technology

In recent years, along with the continuous maturation and the development of manufacture of semiconductor technology, various dynamical electronic products are constantly weeded out the old and bring forth the new, and integrated circuit (Integrated Circuit, IC) integration of assembly (Integration) also improves constantly.In the encapsulation procedure of integrated circuit package, considerable role is being played the part of in integrated circuit encapsulation (IC Packaging), and integrated circuit encapsulation kenel can roughly be divided into routing bond package (Wire Bonding Package, WB), automatic bond package (Tape Automatic Bonding is with in subsides, TAB) and chip bonding (Flip Chip, pattern such as FC), and every kind of packing forms all has its particularity and application.Wherein, for the chip and substrate of circuitry lines design, when machine path, Electricity Federation is long, can cause inductance (Inductance) to increase with high density output/input (I ∕ O).In addition, the reliability of the required cost of manufacture costliness of manually operated routing joining technique, processing procedure quality is low and productivity ratio is also relatively low.In order to improve the problems referred to above, develop in addition a kind of have dwindle package area and shorten crystalline substance (Flip-Chip) technology of covering of signal transmission path or be referred to as control collapse chip join (Controlled Collapse Chip Connection, C4).See also Fig. 3, projection in its integrated circuit package structure 500 on the integrated circuit (IC) chip 50 is generally tin ball 60, desire is tied 60 welderings of this tin ball when this integrated circuit (IC) chip 50, at first must have Jin Shu Ceng ﹝ Under Bump Metallization under the projection of one to multiple layer of metal-layer structure in formation one on the metal pad 541 of this integrated circuit (IC) chip 50, UBM ﹞ 70, comprising an adhesion layer (Adhesion layer) 71 that is formed on this metal pad 541 by this integrated circuit (IC) chip 50 to these tin ball 60 directions, for example is titanium coating; The conductive layer of one tool conductivity (Conductor Layer) 72 for example is aluminium (Al), copper (Cu), gold (Au) or silver (Ag) metal; One prevent that this tin ball 60 from penetrating and with the barrier layer (Barrier Layer) 73 of these conductive layer 72 reactions, for example nickel (Ni), chromium (Cr) or platinum (Pt) metal; And one in order to provide the wettable layer (Wettable Layer) 74 of these tin ball 60 wetabilitys and protection below metal level, for example gold, silver, copper, tin (Sn) or other organic compound.Its feature utilize this projection lower metal layer 70 to provide to connect put tin ball, diffusion barrier (Diffusion Barrier) and suitably function such as tackness in 541 of the metal pads of this tin ball 60 and this integrated circuit (IC) chip 50, be able to scolder is applied on this projection lower metal layer 70, form required tin ball 60 through reflow program (Reflow) with the scolder that will be applied again.The general method that adopts of this projection lower metal layer processing procedure comprises sputter technology (Sputtering), evaporation coating technique (Evaporation) and electroplating technology (Plating) etc.

See also Fig. 4 a to Fig. 4 f, for being known in the processing procedure figure that forms the projection lower metal layer on the integrated circuit (IC) chip.Shown in Fig. 4 a; the integrated circuit (IC) chip 50 that at first provides a surface to have several electrical connection pads 51; the surface of this integrated circuit (IC) chip 50 is formed with a protective layer (Passivation Layer) 52; and expose electrical connection pad 51 on this integrated circuit (IC) chip 50 to the open air; be formed with one first dielectric layer 53 and one second dielectric layer 55 on this protective layer 52 in addition; and in being formed with a metal level (Trace Metal) 54 between this first dielectric layer 53 and this second dielectric layer 55 on this electrical connection pad 51, this second dielectric layer 55 also exposes metal pad 541 on this metal level 54 to the open air.Shown in Fig. 4 b, then on this second dielectric layer 55 and this metal pad 541, utilize sputtering way to form a titanium layer, reach one first bronze medal layer 72a, wherein this titanium layer is as adhesion layer 71.Shown in Fig. 4 c and Fig. 4 d, go up coating one photoresist layer 75 in this first bronze medal layer 72a, behind exposure (Expose) and develop (Develop), form one second bronze medal layer 72b, a nickel dam and a gold medal layer with plating mode successively on this first bronze medal layer 72a, wherein this first bronze medal layer 72a and the second bronze medal layer 72b are as conductive layer 72; This nickel dam is as barrier layer 73; And should the gold layer as wettable layer 74.Shown in Fig. 4 e and Fig. 4 f, peel off this photoresist layer 75 at last, and be etched in the adhesion layer 71 and the first bronze medal layer 72a that appears under this photoresist layer 75.So far, finish a projection lower metal layer 70 that possesses titanium/copper/nickel/gold (Ti/Cu/Ni/Au) four-layer structure.

Yet, said structure is when covering brilliant welding block, when its tin ball 60 runs into the scolder that contains gold, understand golden tin Jie metallic compound (the Intermetallic Compound Layer that produces eutectic reaction and produce fragility, IMC), even the generation hole, cause and follow-uply chap in tin ball and 70 of this projection lower metal layers, have a strong impact on the processing procedure reliability.

Because above-mentioned be known on the integrated circuit (IC) chip forms projection lower metal layer technology and need use multiple material, and need through multiprogramming, not only improve process complexity and cost, also follow simultaneously the increase of reliability risk in the processing procedure, and this soldering tin material is behind the high temperature back welding process, cause the reliable in quality degree of formed scolding tin structure to reduce, and then the electric connection quality that causes final products reduces and the anxiety of electrical short circuit is arranged, therefore, to relatively increase the processing procedure cost and the benefit that reduces cost, and still can't solve the low excessively problem of productive rate.So it is required when reality is used generally can't to meet the user.

Summary of the invention

Technical problem to be solved in the utility model is: at above-mentioned the deficiencies in the prior art, a kind of semiconductor encapsulation device is provided, it directly uses as structured metal layer under the projection with the metal level in the structure, can save the cost of equipment of structured metal layer under the extra assembling projection, and can provide an X/Cu/Sn metal-layer structure of comparatively simplifying, and need not additionally to be provided with barrier layer, not only be able to the number of plies and reduce and can have preferable circuit structure, and when can improve productivity ratio in simplifying processing procedure and effectively reduce cost.

In order to solve the problems of the technologies described above, the technical scheme that the utility model adopted is: a kind of semiconductor encapsulation device, comprise semiconductor device, metal level, second dielectric layer, reach solder bump, this semiconductor device surface is provided with several electrical connection pads, and covering surfaces protective layer, the position of corresponding those electrical connection pads has several perforates and appears those electrical connection pads with the part in this sealer, wherein, this sealer is provided with first dielectric layer, and it has several first openings and appears those electrical connection pads with part at least; Be characterized in: described metal level is arranged on this first dielectric layer and is electrically connected to the electrical connection pad of this semiconductor device via this first opening, this metal level comprises adhesion layer, conductive layer, reaches protective layer, this adhesion layer is arranged on this first dielectric layer, this conductive layer is arranged on this adhesion layer, and this protective layer is arranged on this conductive layer;

This second dielectric layer is arranged on the protective layer of this first dielectric layer and this metal level, and it has several second openings with the local at least end that appears this metal level; This solder bump is arranged on the end that this metal level part appears, and second opening of this second dielectric layer is contained in its overlay area; Wherein, the end of this metal level is put this solder bump as structured metal layer under the projection to connect thereon, and connects the protective layer of putting with this solder bump be made up of first protective layer and second protective layer in this metal level.

So, this device directly uses as structured metal layer under the projection with the metal level in the structure, can save the cost of equipment of structured metal layer under the extra assembling projection, and its structure is simple relatively, can provide an X/Cu/Sn metal-layer structure of comparatively simplifying compared to known technology, and need not additionally setting with the barrier layer (Barrier Layer) of expensive material such as nickel, chromium or platinum, not only be able to the number of plies and reduce and have preferable circuit structure, and when can improve productivity ratio in simplifying processing procedure and effectively reduce cost.

Description of drawings:

Fig. 1 is a semiconductor encapsulation device schematic diagram of the present utility model.

Fig. 2 a is the semiconductor chip structure schematic diagram of the utility model preferred embodiment.

Fig. 2 b is that the utility model is made the titanium/copper/structural representation of tin layer on the semiconductor chip of Fig. 2 a.

Fig. 2 c is the structural representation of the utility model coating photoresist layer on titanium/copper/tin layer of Fig. 2 b.

Fig. 2 d is the structural representation of titanium/copper/tin layer of the utility model local etching Fig. 2 c.

Fig. 2 e is the structural representation of the utility model stripping resistance layer on local titanium/copper/tin layer of Fig. 2 d.

Fig. 2 f is the structural representation of the utility model immersion tin layer on local titanium/copper/tin layer of Fig. 2 e.

Fig. 3 is known integrated circuit package structure schematic diagram.

Fig. 4 a is a known semiconductor chip structure schematic diagram.

Fig. 4 b is the known sputter titanium/structural representation of copper layer on the semiconductor chip of Fig. 4 a.

Fig. 4 c is the structural representation of known coating photoresist layer on titanium/copper layer of Fig. 4 b.

Fig. 4 d is known electric copper facing/nickel/gold layer in the structural representation on titanium/copper layer of appearing of Fig. 4 c.

Fig. 4 e is the structural representation of stripping resistance layer on the titanium/copper layer that is known in Fig. 4 d.

Fig. 4 f is the structural representation of the titanium/copper layer under the stripping resistance layer of known local etching Fig. 4 e.

Label declaration:

Semiconductor encapsulation device 100 semiconductor devices 10

Electrical connection pad 11 sealers 12

Perforate 13 first dielectric layers 14

First opening, 15 metal levels 20

End 201 adhesion layers 21

Conductive layer 22 protective layers 23

The first protective layer 23a, the second protective layer 23b

Photoresist layer 24 second dielectric layers 30

Second opening, 31 solder bumps 40

Integrated circuit package structure 500 semiconductor chips 50

Electrical connection pad 51 protective layers 52

First dielectric layer, 53 metal levels 54

Metal pad 541 second dielectric layers 55

Tin ball 60 projection lower metal layers 70

Adhesion layer 71 conductive layers 72

The first bronze medal layer 72a, the second bronze medal layer 72b

Barrier layer 73 wettable layer 74

Photoresist layer 75

Embodiment:

See also shown in Fig. 1 and Fig. 2 a to Fig. 2 f, be respectively semiconductor encapsulation device schematic diagram of the present utility model, the semiconductor chip structure schematic diagram of the utility model preferred embodiment, the utility model is made the titanium/copper/structural representation of tin layer on the semiconductor chip of Fig. 2 a, the structural representation of the utility model coating photoresist layer on titanium/copper/tin layer of Fig. 2 b, the structural representation of titanium/copper/tin layer of the utility model local etching Fig. 2 c, the structural representation of the utility model stripping resistance layer on local titanium/copper/tin layer of Fig. 2 d, and the structural representation of the utility model immersion tin layer on local titanium/copper/tin layer of Fig. 2 e.As shown in the figure: the utility model is a kind of semiconductor encapsulation device 100, mainly comprises semiconductor device 10, a metal level (Trace Metal) 20,1 second dielectric layer 30 and a solder bump (Solder Bump) 40.

This semiconductor device 10 is the wherein a kind of of semiconductor chip (Chip), wafer (Wafer), conductor package substrate or circuit board; its surface is provided with several electrical connection pads 11; and cover a sealer (Passivation Layer) 12; the position of corresponding those electrical connection pads 11 has several perforates 13 and appears those electrical connection pads 11 with the part in this sealer 12; wherein; this sealer 12 is provided with one first dielectric layer 14, and it has several first openings 15 and appears those electrical connection pads 11 with part at least.

This metal level 20 is arranged on this first dielectric layer 14 and is electrically connected to the electrical connection pad 11 of this semiconductor device 10 via this first opening 15, this metal level 20 mainly comprises an adhesion layer (Adhesion layer) 21, be arranged on this first dielectric layer 14, can adhere to base material and can supply subsequent metal layer adhere to, one conductive layer (Conductor Layer) 22, be arranged on this adhesion layer 21, an and protective layer 23, be arranged on this conductive layer 22, but for solderability (Solder-ability) surface and prevent that this conductive layer 22 is oxidized, wherein, this protective layer 23 is made up of one first protective layer 23a and one second protective layer 23b; This metal level 20 is X/ copper/tin (X/Cu/Sn), and X is selected from the metallic element of titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), palladium (Pd), platinum (Pt) or titanium tungsten (Ti/W) that its mixture is formed, chromium nickel (Cr/Ni) alloy etc. for one or more.

This second dielectric layer 30 is arranged on the first protective layer 23a of this first dielectric layer 14 and this metal level 20, and it has several second openings 31 with the local at least end 201 that appears this metal level 20.

This solder bump 40 is a tin ball, is arranged on the end 201 that these metal level 20 parts appear, and second opening 31 of this second dielectric layer 30 is contained in its overlay area.Wherein, the end 201 of above-mentioned metal level 20 is as (the Under Bump Metallization of structured metal layer under the projection; UBM); put this solder bump 40 to connect thereon; and in this metal level 20, connect in the protective layer of putting 23 with this solder bump 40; this second protective layer 23b is electro-less plating Sn (Electroless Tin) layer or immersion tin (Immersion Tin) layer of a visual increase in demand thickness, for the engaging force of reinforcement with this solder bump 40.The above constitutes a brand-new semiconductor encapsulation device 100.

During utilization, above-mentioned semiconductor device 10 is semiconductor chip (Chip), and electrical connection pad 11 is an aluminium connection pad (Al Pad) on it.In a preferred embodiment; the metal level 20 of this semiconductor encapsulation device 100; system is by successively forming a titanium (Ti) layer as above-mentioned adhesion layer 21 on these first dielectric layer, 14 surfaces with sputter (Sputtering) or other thin film-forming method; one bronze medal layer is as above-mentioned conductive layer 22, and a tin layer is as the above-mentioned first protective layer 23a.Then, coating (Coat) photoresist layer 24 on this tin layer part, behind exposure (Expose) and develop (Develop), etching is revealed in titanium layer, copper layer and the tin layer outside this photoresist layer 24.At last, peel off this photoresist layer 24, and on this first dielectric layer 14 and this first protective layer 23a, be formed with second dielectric layer 30 that exposes outside these metal level 20 ends 201, and impose the immersion plating mode on the tin layer of this end 201, form a thickness between the immersion tin (Immersion Tin) of 0.1～1 micron (μ m) layer as the above-mentioned second protective layer 23b, and then form above-mentioned protective layer 23; So far, make this metal level 20 form one titanium/copper/tin (Ti/Cu/Sn) structure sheaf, the end 201 that formation the utility model utilizes this metal level 20 is put this solder bump 40 as structured metal layer under the projection to connect on the second protective layer 23b thereon.In present embodiment, this adhesion layer 21 also can be selected from the element of tungsten, chromium, nickel, palladium, platinum or titanium tungsten, the chrome-nickel that its mixture is formed.By this, the utility model also need not additionally to be provided with structured metal layer under the projection, the wetability that can provide the back continued access to place solder bump 40 and this copper layer on these metal level 20 ends is so that it engages good and avoid producing the copper oxidation, to strengthen the engaging force with this solder bump 40.

In this way, the utility model can be saved the cost of equipment of structured metal layer under the extra assembling projection, can directly use as structured metal layer under the projection with the metal level in the structure, and its structure is also simple relatively, can provide an X/Cu/Sn metal-layer structure of comparatively simplifying compared to known technology, and need not additionally setting with the barrier layer (Barrier Layer) of expensive material such as nickel, chromium or platinum, not only be able to the number of plies and reduce and have preferable circuit structure, and when can improve productivity ratio in simplifying processing procedure and effectively reduce cost.

In sum, the utility model is a kind of semiconductor encapsulation device, can effectively improve the various shortcoming of prior art, can save the cost of equipment of structured metal layer under the extra assembling projection, can directly use as structured metal layer under the projection with the metal level in the structure, and its structure is also simple relatively, can provide an X/Cu/Sn metal-layer structure of comparatively simplifying compared to known technology, and need not additionally to be provided with barrier layer, not only be able to number of plies minimizing and have preferable circuit structure, and when can improve productivity ratio and effectively reduce cost in simplifying processing procedure, and then can produce more progressive, more practical, the institute that more meets the user must, really meet the important document of utility application, proposed patent application in accordance with the law.

Claims

1. semiconductor encapsulation device, comprise semiconductor device, metal level, second dielectric layer, reach solder bump, this semiconductor device surface is provided with several electrical connection pads, and covering surfaces protective layer, the position of corresponding those electrical connection pads has several perforates and appears those electrical connection pads with the part in this sealer, wherein, this sealer is provided with first dielectric layer, and it has several first openings and appears those electrical connection pads with part at least; It is characterized in that:

Described metal level is arranged on this first dielectric layer and is electrically connected to the electrical connection pad of this semiconductor device via this first opening, this metal level comprises adhesion layer, conductive layer, reaches protective layer, this adhesion layer is arranged on this first dielectric layer, this conductive layer is arranged on this adhesion layer, and this protective layer is arranged on this conductive layer;

This second dielectric layer is arranged on the protective layer of this first dielectric layer and this metal level, and it has several second openings with the local at least end that appears this metal level;

This solder bump is arranged on the end that this metal level part appears, and second opening of this second dielectric layer is contained in its overlay area;

Wherein, the end of this metal level is put this solder bump as structured metal layer under the projection to connect thereon, and connects the protective layer of putting with this solder bump be made up of first protective layer and second protective layer in this metal level.

2. semiconductor encapsulation device as claimed in claim 1 is characterized in that: described semiconductor device is changed to semiconductor chip, wafer, conductor package substrate or circuit board.

3. semiconductor encapsulation device as claimed in claim 1 is characterized in that: described conductive layer is the copper layer.

4. semiconductor encapsulation device as claimed in claim 1 is characterized in that: described protective layer is the tin layer.

5. semiconductor encapsulation device as claimed in claim 1 is characterized in that: described second protective layer is electro-less plating Sn layer or immersion tin layer.

6. semiconductor encapsulation device as claimed in claim 1 is characterized in that: described solder bump is the tin ball.

7. semiconductor encapsulation device as claimed in claim 1 is characterized in that: described electrical connection pad is the aluminium connection pad.

8. semiconductor encapsulation device as claimed in claim 1 is characterized in that: the thickness of described second protective layer is 0.1～1 micron.