CN103903989A - Method for forming semiconductor packaging structure - Google Patents
Method for forming semiconductor packaging structure Download PDFInfo
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- CN103903989A CN103903989A CN201410061267.1A CN201410061267A CN103903989A CN 103903989 A CN103903989 A CN 103903989A CN 201410061267 A CN201410061267 A CN 201410061267A CN 103903989 A CN103903989 A CN 103903989A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
A method for forming a semiconductor packaging structure includes the steps of firstly, providing a semiconductor chip, sequentially forming a heat-resistant metal layer and a metal infiltration layer on a welding disc of the chip, sequentially forming an adhesive layer and a blocking layer on the metal infiltration layer, and enabling solders to be formed on the blocking layer and to flow back so as to form columnar protruding points; secondly, providing a lead frame, reversedly arranging the chip with the columnar protruding points on the lead frame, and enabling the columnar protruding points to be electrically connected with inner pins of the lead frame; thirdly, forming a plastic sealing layer for sealing the chip, the columnar protruding points and the lead frame and exposing outer pins. By means of the method, the transverse area occupied by the packaging structure is narrowed, the size of the whole packaging structure is accordingly decreased, and the integrity of the packaging structure is improved.
Description
Technical field
The present invention relates to semiconductor packages field, relate in particular to a kind of semiconductor package, formation method.
Background technology
Along with electronic product is if mobile phone, notebook computer etc. are towards miniaturization, portable, ultrathin, multimedization and meet the low cost future development of public demand, high density, high-performance, high reliability and cheaply packing forms and packaging technology thereof have obtained development fast.With expensive BGA(Ball Grid Array) etc. compared with packing forms, fast-developing novel encapsulated technology in recent years, as four limit flat non-pin QFN(Quad Flat No-leadPackage) encapsulation, because it has advantages of good hot property and electrical property, size is little, cost is low and high production rate etc. is numerous, cause a new revolution in microelectronic packaging technology field.
Fig. 1 is the structural representation of existing QFN encapsulating structure, and described QFN encapsulating structure comprises: semiconductor chip 14, has pad 2 on described semiconductor chip 1; Pin 3(lead frame), described pin 3 is arranged around the surrounding of described semiconductor chip 1; Plain conductor 4, plain conductor 4 is electrically connected the pad of semiconductor chip 12 with the pin 3 around described semiconductor chip 1; Capsulation material 5, described capsulation material 5 seals semiconductor chip 1, metal wire 4 and pin 3, and the surface exposure of pin 3 is in the bottom surface of capsulation material, realizes being electrically connected of semiconductor chip 1 and external circuit by pin 3.
The volume that existing encapsulating structure occupies is larger, is unfavorable for the raising of encapsulating structure integrated level.
Summary of the invention
The problem that the present invention solves is how to improve the integrated level of encapsulating structure.
For addressing the above problem, the invention provides a kind of formation method of semiconductor package, comprising: semiconductor chip is provided, and the surface of described chip is provided with pad and passivation layer, described passivation layer is provided with the first opening of exposed described pad; On the pad of chip and passivation layer, form successively heat resistant metal layer and metal infiltrating layer; In metal infiltrating layer, form photoresist, described photoresist is provided with the second opening that exposes chip bonding pad upper metal soakage layer; In metal infiltrating layer in the second opening, form successively adhesion layer and barrier layer; On barrier layer, form scolder; Remove photoresist; Heat resistant metal layer on etch passivation layer and metal infiltrating layer are exposed to passivation layer; Reflux solder, forms columnar bump; Lead frame is provided, and described lead frame is provided with some discrete pins, and interior pin and outer pin are located at the relative two sides of pin; By the flip-chip that is formed with columnar bump, on lead frame, described columnar bump is electrically connected with described interior pin; Form sealing described chip, columnar bump and lead frame, and expose the plastic packaging layer of described outer pin.
Compared with prior art, technical scheme of the present invention has the following advantages:
The formation method of encapsulating structure of the present invention by semiconductor chip upside-down mounting above pin, by columnar bump, the pad on semiconductor chip is electrically connected with interior pin, the horizontal area that the encapsulating structure forming is occupied reduces, the small volume of whole encapsulating structure, has improved the integrated level of encapsulating structure.
Brief description of the drawings
Fig. 1 is the structural representation of prior art encapsulating structure;
Fig. 2～Figure 11 is the cross-sectional view of the forming process of embodiment of the present invention encapsulating structure.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
First, with reference to figure 2, provide semiconductor chip 200, the surface of described semiconductor chip 200 is provided with pad 201 and passivation layer 202, and described passivation layer 202 is provided with the first opening of exposed described pad 201.
The fuction output terminal that described pad 201 is chips 200, and the final conduction transition that realizes electrical functionality by the columnar bump 206 of follow-up formation; The material of passivation layer 202 comprises dielectric material or their mixtures such as silica, silicon nitride, silicon oxynitride, polyimides, benzene three polybutene, for the protection of the circuit in chip 200.
It should be noted that, the pad of described chip and passivation layer can be initial pad and the initial passivation of chip, and can be also needs according to circuit layout-design the transition pad, the passivation layer that form; The mode that forms transition pad, passivation layer is mainly to adopt Wiring technique technology again, is connected up initial pad, passivation layer are reprinted on transition pad, passivation layer by one or more layers.The described technology of Wiring technique is again existing maturation process, is well known to those skilled in the art, and does not repeat them here.
Then,, with reference to figure 3, on the pad 201 of chip 200 and passivation layer 202, form successively heat resistant metal layer 203 and metal infiltrating layer 204.
The material of described heat resistant metal layer 203 can be constituting of titanium Ti, chromium Cr, tantalum Ta or they, and the present invention is preferably Ti.The material of described metal infiltrating layer 204 can be constituting of a kind of in copper Cu, aluminium Al, nickel or they, and wherein preferably metal infiltrating layer 204 is Cu.Heat resistant metal layer 203 forms the Seed Layer of final structure together with metal infiltrating layer 204.The method of described heat resistant metal layer 203 and metal infiltrating layer 204 can adopt the method for existing evaporation or sputter or physical vapour deposition (PVD) equally, and wherein preferably method is sputter.Certainly, according to those skilled in the art's common practise, form method be not limited only to sputtering method, other applicable methods all can be applicable to the present invention, and form heat resistant metal layer 203 and the thickness of metal infiltrating layer 204 be also to determine according to actual process requirements.
Then, with reference to figure 4, form photoresist 205 in metal infiltrating layer 204, described photoresist 205 is provided with the second opening that exposes chip 200 pad 201 upper metal soakage layers 204.
The method that forms photoresist 205 can be rotary coating, and the concrete steps of these methods are well known to those skilled in the art, do not repeat them here.Form after photoresist 205, specifically can define by existing photoetching development technology the shape of pad 201, make to form opening to expose the metal infiltrating layer 204 on pad 201 in photoresist 205.
In other embodiments of the invention, described the second opening is less than described the first opening, and the opening size of photoresist 205 is less than the passivation layer opening size of chip 200; Object is that the columnar bump 206 of follow-up formation can be dropped in the first opening, avoids making columnar bump 206 to be formed on passivation layer 202 and causes that stress is excessive, the integrity problem of pad 201 easy embrittlement.
Then,, with reference to figure 5, in the metal infiltrating layer 204 in the second opening, form successively adhesion layer 206a and barrier layer 206b.
In this step, taking remaining photoresist 205 on chip 200 as mask, in the second opening forming in upper step, metal infiltrating layer 204 above, form successively adhesion layer 206a and barrier layer 206b, the mode that concrete technology can be electroplated by use.Certainly, according to those skilled in the art's common practise, the method for formation is not limited only to electroplate, and other applicable methods all can be applicable to the present invention.The material of described adhesion layer 206a is copper Cu, and the material of barrier layer 206b is nickel.
The thickness of described adhesion layer 206a copper is 5～50 μ m, and concrete thickness is 5 μ m, 10 μ m, 15 μ m, 20 μ m, 25 μ m, 30 μ m, 35 μ m, 40 μ m, 45 μ m or 50 μ m etc.Adhesion layer 206a is that final electrically lead-out terminal is the column structure main body of columnar bump 206.Adhesion layer 206a spatially provides enough material space, and the scolder 206c that has ensured follow-up formation can be placed in securely on adhesion layer 206a and can not depart from after backflow, has also improved the adhesion between scolder 206c simultaneously; Simultaneously, also just because of the column structure of adhesion layer 206a is dwindled the size of scolder 206c, ensureing, under the prerequisite of physical connection reliability in final products welding process, to have promoted the fuction output port number in unit space, more can meet close spacing, fuction output package requirements how.
The thickness of described barrier layer 206b nickel is 1.5 μ m～3 μ m, and concrete thickness is 1.5 μ m, 2 μ m, 2.5 μ m or 3 μ m etc.Acting as of barrier layer 206b prevents that the material of follow-up formation solder bump from diffusing in metal infiltrating layer 204, in the time that Ni layer thickness is less than 1.5 μ m, Ni finally can disappear because of the diffusion effect between adjacent metal, and then cannot effectively stop that follow-up solder bump is diffused in metal infiltrating layer 204; In the time that Ni layer thickness is greater than 3 μ m, can causes resistivity to rise because the electric heating property of Ni metal itself is poor, and then affect the electric heating property of final products.Therefore, can avoid self disappearing because of diffusion effect on the one hand in the suitable barrier layer (Ni) of thickness, and then effectively stop the hole that between scolder and metal infiltrating layer, the formation because of intermetallic compound produces; Be unlikely to again to cause because nickel barrier layer is blocked up resistivity to rise and affect the electric heating property of product simultaneously.
Then,, with reference to figure 6, on the 206b of barrier layer, form scolder 206c.
In this step, still taking photoresist 205 as mask, on the 206b of barrier layer, form scolder 206c, the material that forms described scolder 206c is pure tin or ashbury metal, as sn-ag alloy, gun-metal, SAC alloy etc.The method that forms scolder 206c can be metallide, sputter, screen painting or directly implant the modes such as prefabricated solder ball, and the concrete steps of these methods have been well known to those skilled in the art, do not repeat them here.
In the present embodiment, the thickness of scolder 206c is 5 μ m～70 μ m, concrete thickness for example 5 μ m, 10 μ m, 15 μ m, 20 μ m, 25 μ m, 30 μ m, 35 μ m, 40 μ m, 45 μ m, 50 μ m, 55 μ m, 60 μ m, 65 μ m or 70 μ m etc.The column structure being formed by above-mentioned steps, can greatly reduce the use amount of scolder 308a, save material cost on the one hand, the more important thing is that the size after a small amount of scolder 206c refluxes is less, can meet the application demand of greater functionality output point in the close spacing of pad 201 or same space.
Then,, with reference to figure 7, remove photoresist 205; Taking adhesion layer 206a as mask, heat resistant metal layer 203 and metal infiltrating layer 204 on etch passivation layer 202 are exposed to passivation layer.
Complete after above-mentioned operation, photoresist 205 can have been removed, and can use wet method or the mode peeled off is removed, and the concrete steps of these methods are well known to those skilled in the art, do not repeat them here.
In the present embodiment, specifically can remove metal infiltrating layer 204 and the heat resistant metal layer 203 on chip 200 surfaces beyond scolder 206c by the method for spraying acid solution or wafer is soaked in acid solution, thereby expose passivation layer 202.
Then,, with reference to figure 8, reflux solder, forms columnar bump 206.
In the present embodiment, become hemispherical by reflux heating melting solder 206c, form the columnar bump 206 being formed by adhesion layer 206a, barrier layer 206b and scolder 206c, now, the fuction output terminal of chip 200 is transitioned on columnar bump 206 by pad 201, and columnar bump 206 becomes the electrical output of chip 200.
Then, with reference to figure 9, provide lead frame 300, described lead frame 300 is provided with some discrete pins, and interior pin 301 and outer pin 302 are located at the relative two sides of pin.
Described lead frame 300 adopts die-cut or etch process to form, and interior pin 301 is connected with active device or passive device as the electrical input of pin, and outer pin encapsulates and interconnects as printed substrate etc. as electrical output and next stage.
Then,, with reference to Figure 10, by chip 200 upside-down mountings that are formed with columnar bump 206, on lead frame 300, described columnar bump 206 is electrically connected with described interior pin 301.
By columnar bump 206, the pad on chip 200 201 is electrically connected with interior pin 301, the horizontal area that occupies of encapsulating structure forming is reduced, the small volume of whole encapsulating structure, has improved the integrated level of encapsulating structure.Simultaneously, compared with the mode by metal lead wire, pad 201 being interconnected with interior pin 301 with tradition, inverted structure of the present invention has shortened the transmission range between chip 200 and interior pin 201 greatly, resistance, thermal resistance be corresponding reduction also, thereby promote the performance of whole product, also more can meet the requirement of high-power product as the columnar bump 206 of chip 200 outputs.
Then, please refer to Figure 11, form sealing described chip 200, columnar bump 206 and lead frame 300, and expose the plastic packaging layer 400 of outer pin 302.
Described plastic packaging layer 400 surrounds described chip 200, fills the region between chip 200 and interior pin 301, and plastic packaging layer 400 is also filled the opening of expiring between pin, the bottom-exposed of plastic packaging layer 400 pin 302 of going out.While filling plastic packaging layer 400, because the space between the space between the opening between pin and chip 200 and chip 200 and interior pin 301 communicates, improve the mobility of capsulation material, thereby prevented from producing the defects such as space in plastic packaging layer 400.
Described plastic packaging layer 400 for the protection of with insulation package structure, the material of described plastic packaging layer 400 is resin, described resin can be epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; Described resin also can be for being polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol; Described plastic packaging layer 400 can also be other suitable capsulation materials.
The formation technique of described plastic packaging layer 400 is Shooting Technique or turns and mould technique (transfer molding).The formation technique of described plastic packaging layer 400 can also be other suitable techniques.
Form after plastic packaging layer 400, also comprise, adopt cutting technique to cut apart plastic packaging layer 400, form multiple discrete semiconductor encapsulation units.
The encapsulating structure that said method forms, please refer to Figure 11, comprising:
Described chip 200 upside-down mountings are on lead frame 300, and described columnar bump 206 is connected with described interior pin 301;
Plastic packaging layer 400, described plastic packaging layer 400 seals described chip 200, columnar bump 206 and lead frame 300, and exposes described outer pin 302;
Described columnar bump 206 is from bottom to top successively by adhesion layer 206a, barrier layer 206b with scolder 206c is stacking forms, and described adhesion layer 206a is connected with Seed Layer, and it is upper that barrier layer 206b is stacked in adhesion layer 206a, and scolder 206c is stacked on the 206b of barrier layer.
Concrete, described Seed Layer is by heat resistant metal layer 203 and metal infiltrating layer 204 is stacking forms, and described heat resistant metal layer 203 is connected with pad 201, and described metal infiltrating layer 204 is stacked on described heat resistant metal layer 203.
Described columnar bump 206 is located in described the first opening.
The material of described heat resistant metal layer 203 is titanium, chromium, tantalum or their combination.
The material of described metal infiltrating layer 204 is copper, aluminium, nickel or their combination.
The material of described adhesion layer 206a is copper, and the thickness of copper is 5～50 μ m.
The material of described barrier layer 206b is nickel, and the thickness of nickel is 1.5～3 μ m.
The material of described scolder 206c is pure tin or ashbury metal, and the thickness of scolder 206c is 5～70 μ m.
To sum up, the formation method of the encapsulating structure of the embodiment of the present invention and encapsulating structure thereof, by semiconductor chip upside-down mounting on interior pin, the syndeton consisting of Seed Layer and columnar bump piece is electrically connected the pad on semiconductor chip with pin, make the small volume of whole encapsulating structure, and the formation method of this encapsulating structure can realize the chip scale encapsulation of lead frame structure, improve the integrated level of encapsulating structure.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for semiconductor package, is characterized in that, comprising:
Semiconductor chip is provided, and the surface of described chip is provided with pad and passivation layer, and described passivation layer is provided with the first opening of exposed described pad;
On the pad of chip and passivation layer, form successively heat resistant metal layer and metal infiltrating layer;
In metal infiltrating layer, form photoresist, described photoresist is provided with the second opening that exposes chip bonding pad upper metal soakage layer;
In metal infiltrating layer in the second opening, form successively adhesion layer and barrier layer;
On barrier layer, form scolder;
Remove photoresist;
Heat resistant metal layer on etch passivation layer and metal infiltrating layer are exposed to passivation layer;
Reflux solder, forms columnar bump;
Lead frame is provided, and described lead frame is provided with some discrete pins, and interior pin and outer pin are located at the relative two sides of pin;
By the flip-chip that is formed with columnar bump, on lead frame, described columnar bump is electrically connected with described interior pin;
Form sealing described chip, columnar bump and lead frame, and expose the plastic packaging layer of described outer pin.
2. the formation method of a kind of semiconductor package according to claim 1, is characterized in that, described the second opening is less than described the first opening.
3. the formation method of a kind of semiconductor package according to claim 1, is characterized in that, the material of described heat resistant metal layer is titanium, chromium, tantalum or their combination.
4. the formation method of a kind of semiconductor package according to claim 1, is characterized in that, the material of described metal infiltrating layer is copper, aluminium, nickel or their combination.
5. the formation method of a kind of semiconductor package according to claim 1, is characterized in that, the material of described adhesion layer is copper.
6. the formation method of a kind of semiconductor package according to claim 5, is characterized in that, the thickness of described copper adhesion layer is 5～50 μ m.
7. the formation method of a kind of semiconductor package according to claim 1, is characterized in that, the material on described barrier layer is nickel.
8. the formation method of a kind of semiconductor package according to claim 7, is characterized in that, the thickness on described nickel barrier layer is 1.5～3 μ m.
9. the formation method of a kind of semiconductor package according to claim 1, is characterized in that, the material of described scolder is pure tin or ashbury metal.
10. the formation method of a kind of semiconductor package according to claim 9, is characterized in that, the thickness of described scolder is 5～70 μ m.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410061267.1A CN103903989A (en) | 2014-02-24 | 2014-02-24 | Method for forming semiconductor packaging structure |
| US14/780,233 US9515010B2 (en) | 2014-02-24 | 2014-06-26 | Semiconductor packaging structure and forming method therefor |
| PCT/CN2014/080839 WO2015123952A1 (en) | 2014-02-24 | 2014-06-26 | Semiconductor packaging structure and forming method therefor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410061267.1A CN103903989A (en) | 2014-02-24 | 2014-02-24 | Method for forming semiconductor packaging structure |
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| CN103903989A true CN103903989A (en) | 2014-07-02 |
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| CN201410061267.1A Pending CN103903989A (en) | 2014-02-24 | 2014-02-24 | Method for forming semiconductor packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104465585A (en) * | 2014-12-26 | 2015-03-25 | 江苏长电科技股份有限公司 | Wafer level package structure and technological method thereof |
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| CN102820276A (en) * | 2011-06-10 | 2012-12-12 | 南茂科技股份有限公司 | QFN package and manufacturing process thereof |
| CN102231376A (en) * | 2011-06-30 | 2011-11-02 | 天水华天科技股份有限公司 | Multi-cycle arrangement carrier-free double-integrated chip (IC) package and production method |
| CN102496606A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | High-reliability wafer level cylindrical bump packaging structure |
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