CN106898625A - The encapsulating structure and method for packing of image sensor chip - Google Patents
The encapsulating structure and method for packing of image sensor chip Download PDFInfo
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- CN106898625A CN106898625A CN201510960949.0A CN201510960949A CN106898625A CN 106898625 A CN106898625 A CN 106898625A CN 201510960949 A CN201510960949 A CN 201510960949A CN 106898625 A CN106898625 A CN 106898625A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of encapsulating structure and method for packing of image sensor chip, avoid using silicon perforation technique using the substrate trenches etching technics of chip back, the neighboring of channel bottom is exposed pad simultaneously is modified to step structure, thus the filling difficulty of interconnection metal layer is reduced, increase the interconnection metal layer of follow-up filling and the contact area of pad, improve the connection reliability of interconnection metal layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of image sensor chip encapsulation knot
Structure and method for packing.
Background technology
Cmos image sensor (CMOS Image Sensor, CIS) is the important composition portion of digital camera
Point, its imaging principle be carried out by light-sensitive device it is photosensitive, so as to convert optical signals to electric signal, so
Output image afterwards.
At present, the CIS chip encapsulation technologies of main flow include：CSP(Chip Scale Package)、
COB (Chip On Board) and FC (Flip Chip).Wherein CSP refers to chip size packages and chip core
The essentially identical chip encapsulation technology of size, be commonly utilized at present low and middle-end, low pixel (2M pixels or with
Under) Wafer level (wafer scale) encapsulation of imageing sensor aspect.CSP encapsulation technologies are usually by image sensing
Device chip front side is tied up using wafer scale glass (euphotic cover plate of chip front side) as photosensitive window with wafer
It is fixed, and separated using enclosure wall between the image sensor chip of wafer, the then weldering of wafer after grinding
Disk area, by (or ring metal in pad face endoporus side the connect) silicon perforation for making that bond pad surface connects
(Through Silicon Via, TSV) or cutting after pad side T-shaped metal come contact the image on wafer pass
Sensor chip, and solder ball grid array (Ball Grid Array, BGA) is made after wafer rear extended link,
So as to the pad of chip front side is redistributed into chip back by certain mode, realize mutual with the external world
Connection, to form the image sensor cell of single sealing cavity, rear end passes through surface mount to last cutting crystal wafer
Technology (Surface Mount Technology, SMT) forms module assembled structure.In CSP long term voyage with
The ratio of package area is about 1:1.1, every encapsulation for meeting this standard can be referred to as CSP.So
Packing forms substantially increase integrated level on printed circuit board (PCB) (PCB), reduce electronic device volume and
Weight, improves the performance of product.
Above-mentioned silicon perforation technology, usually first on the silicon body of chip back using the method for dry etching
Silicon hole is formed, insulating treatment then is carried out to the silicon in the chip substrate silicon for exposing and hole, and in hole
Bottom is outputed interconnection window and is contacted so that follow-up filling metal is formed with pad, and metal is then filled in hole,
And redistribution metallic circuit layer.However, this wafer level image sensor packaged type is due to introducing
Silicon hole is interconnected so that encapsulating structure is complicated；And silicon hole interconnection technique is also immature, often due to hole
The problems such as interior insulation is bad, interconnection window is imperfect and metal filled unreal causes failure or reliability bad,
So that this kind of wafer level image sensor encapsulation carried out using silicon hole interconnection is present, technology difficulty is big, interconnection
The low problem of reliability.Meanwhile, the complexity of silicon hole interconnection technology also causes using the wafer scale of the technology
Image sensor package price is costly.
The content of the invention
It is an object of the invention to provide the encapsulating structure and method of a kind of image sensor chip, can simplify
Encapsulating structure, reduction technology difficulty and process costs.
To solve the above problems, the present invention proposes a kind of method for packing of image sensor chip, including following
Step：
Package substrate and image sensor chip are provided, the package substrate has transparent area, and described image is passed
Sensor chip is formed on the front of semi-conductive substrate, and described image sensor chip circumference semiconductor
Multiple pads are formed with substrate face, each pad is the metal structure interconnected by more metal layers；
The front of the package substrate and the Semiconductor substrate is bonded, wherein, the transparent area correspondence is described
The photosensitive area of image sensor chip；
The back side to the Semiconductor substrate is performed etching to form groove, and the groove exposes the pad
Bottom metal level；
The pad is etched so that the more metal layers of the pad form step structure, and are partly led described
The back side of body substrate forms insulating barrier, each ledge surface of step structure described in the insulating layer exposing；
Interconnection metal layer, the interconnection metal layer are formed in the insulating barrier and the step structure surface
Contacted with every layer of metal level of the step structure；
Protective layer is formed in the wiring metal layer surface, and etches the protective layer formation and expose the cloth
Multiple openings of line metal level；And
Salient point is set in said opening.
Further, there is provided include the step of described image sensor chip：
The Semiconductor substrate is provided；
At least one image sensing cell is formed on the front of the Semiconductor substrate, described image sensing is single
First region is the photosensitive area；
Multiple pads are formed around each image sensing cell.
Further, described image sensing unit and each pad are partly formed in the Semiconductor substrate
In positive passivation layer.
Further, by the way of dispensing, drawing glue, printing rubber, plastic roll or photoetching process patterning glue,
Bond the front of the package substrate and the Semiconductor substrate.
Further, after the groove is formed, the first pad etched to some extent at the groove
Then each layer metal level form insulating barrier to form step structure at the back side of the Semiconductor substrate.
Further, after the groove is formed, insulating barrier first is formed at the back side of the Semiconductor substrate,
Then each layer metal level of pad at the groove is etched to some extent to form step structure.
Further, when forming the step structure, the gold from the bottom metal level of pad to its top
The etching degree for belonging to layer is uniformly successively decreased successively, to cause the bottom metal level to the top metal level
Uniformly lengthened successively in the development length of trenched side-wall.
Further, when each layer metal level for etching the pad at the groove is to form step structure,
At least retain its top metal level in each layer metal level of the pad to be not etched.
Further, the insulating barrier is including in silica, silicon nitride, silicon oxynitride and organic polymer
It is at least one.
Further, by the welding method that flows back, plant ball, evaporation, electroless plating method, galvanoplastic, Place method,
Soldering paste template method for printing or Printing Paste method form salient point in aperture position.
Further, the material of the salient point includes aluminium, tin, silver, lead, copper, zinc, bismuth, indium, Jin He
One or more in antimony.
The present invention also provides a kind of encapsulating structure of image sensor chip, including：
Semiconductor substrate；
Image sensor chip, is formed on the front of the Semiconductor substrate；
Groove, is formed at the Semiconductor substrate back side；
Multiple pads, are distributed in the Semiconductor substrate of described image sensor chip circumference, and the groove
The pad at place is the step structure interconnected by more metal layers；
Insulating barrier, covers the back side of the Semiconductor substrate, and exposes the step structure each
Rank surface；
Interconnection metal layer, covers the step table of the insulating barrier and the step structure for exposing
Face, and contacted with the metal level of each step of the step structure；
Protective layer, covers the wiring metal layer surface, and open with the multiple for exposing the interconnection metal layer
Mouthful；And
Salient point, set in said opening, and with the interconnection metal layer conductive contact.
Further, described image sensor chip is located on a wafer, is served as a contrast including semiconductor on the wafer
Bottom and at least one image sensor chip being formed on the Semiconductor substrate front.
Further, the front of the wafer is also covered with passivation layer, the image of described image sensor chip
Sensing unit and each pad being distributed in around described image sensing unit are partly formed in the passivation
In layer.
Further, in the step structure, bottom metal level to top metal level is in trenched side-wall
Development length uniformly lengthen successively.
Further, the material of the salient point includes aluminium, tin, silver, lead, copper, zinc, bismuth, indium, Jin He
One or more in antimony.
Compared with prior art, the encapsulating structure and method of the image sensor chip that the present invention is provided, have
Following beneficial effect：
(1) present invention first forms groove, and groove in the Semiconductor substrate position of the pad bottom of chip circumference
Bottom-exposed goes out the back surfaces of pad；Then each layer metal level of each pad is repaired, pad edge is repaiied
It is changed to step structure；Finally by the wiring metal for forming step structure described in conductive contact in the trench
Layer, so as to realize that chip electric signal is transferred to chip back from chip front side；Compared with silicon perforation is interconnected, knot
Structure is relatively easy；
(2) because the channel bottom size of present invention formation is larger, the filling wiring metal in follow-up groove
Layer process difficulty reduces, it is to avoid due to the metal filled unreal problem for causing reliability bad in silicon perforation；
(3) contact area of interconnection metal layer and pad is increased due to step structure of the invention, it is to avoid
The interconnection metal layer filled in the prior art only with the top layer on surface of metal or bottom metal watch of pad
The adverse effect of face contact, so as to avoid due to interconnection metal layer in silicon perforation and pad connection reliability not
Good problem；
(4) because the present invention is avoided using silicon perforation interconnection technique, encapsulating structure and technique simplify, are packaged into
This reduction.
Brief description of the drawings
Fig. 1 is the method for packing flow chart of the image sensor chip of the specific embodiment of the invention；
Fig. 2A to 2F is the device profile structural representation in method for packing shown in Fig. 1.
Specific embodiment
Core concept of the invention is, there is provided a kind of imageing sensor without silicon perforation, low cost falls encapsulation
Technique, avoids using silicon perforation (TSV) technique using the substrate trenches etching technics of chip back, while
The neighboring of the pad that channel bottom is exposed is modified to step structure, thus reduces wiring metal
The filling difficulty of layer, increases the interconnection metal layer of follow-up filling and the contact area of pad, improves wiring metal
The connection reliability of layer.
To become apparent the purpose of the present invention, feature, below in conjunction with the accompanying drawings to specific implementation of the invention
Mode is further described, however, the present invention can be realized with different forms, should not be to be confined to
Described embodiment.
The present invention proposes a kind of method for packing of image sensor chip, comprises the following steps：
S1, there is provided package substrate and image sensor chip, the package substrate has transparent area, the figure
As sensor chip is formed on the front of semi-conductive substrate, and described image sensor chip circumference half
Multiple pads are formed with conductor substrate face, each pad is the metal knot interconnected by more metal layers
Structure；
S2, bonds the front of the package substrate and the Semiconductor substrate, wherein, the transparent area correspondence
The photosensitive area of described image sensor chip；
S3, the back side to the Semiconductor substrate is performed etching to form groove, and the groove exposes the weldering
The bottom metal level of disk；
S4, etches the pad so that the more metal layers of the pad form step structure, and described
The back side of Semiconductor substrate forms insulating barrier, each step table of step structure described in the insulating layer exposing
Face；
S5, interconnection metal layer, the wiring gold are formed in the insulating barrier and the step structure surface
Category layer is contacted with every layer of metal level of the step structure；
S6, protective layer is formed in the wiring metal layer surface, and is etched the protective layer and formed and expose institute
State multiple openings of interconnection metal layer；And
S7, sets salient point in said opening.
With reference to shown in Fig. 2A, the starting point of the method for packing of the present embodiment is imageing sensor wafer, the wafer bag
Include Semiconductor substrate 10, positioned at the positive image sensor semiconductor substrate 10 of Semiconductor substrate 10, partly lead
The inside where pad 14 and image sensor semiconductor substrate 10 and pad 14 around body substrate 10 is blunt
Change layer 13, therefore in step sl, there is provided during described image sensor chip, following processing procedure can be previously-completed：
First, there is provided the Semiconductor substrate 10, Semiconductor substrate can be body silicon substrate or silicon-on-insulator substrate
(SOI) etc.；
Then, at least one image sensing cell is formed on the front of Semiconductor substrate 10, described image is passed
Sense unit region is the photosensitive area 101 of image sensor chip；
Then, multiple pads 14 are formed around each image sensing cell.
Wherein, formed on the front of Semiconductor substrate 10 by one layer of passivation layer 13, passivation layer 13 be silica,
Silicon nitride, epoxy radicals, polyimides, resin, FR4 or any other suitable dielectric material.Image is passed
In the passivation layer 13 that is located at of part-structure of sense unit and pad 14, and image sensing cell (including
Photodiode) together with the multiple pads 14, passivation layer 13, lower section being distributed in around the image sensing cell
Semiconductor substrate 10 and the image sensing cell around other related devices (such as image sensing cell
Peripheral MOS transistor circuit) image sensor chip (or image sensor chip region) is constituted,
The usual part-structure of described image sensing unit is located in Semiconductor substrate 10, and part-structure is served as a contrast positioned at semiconductor
In the front face surface of bottom 10, its region is the photosensitive area 101 of image sensor chip, and each pad 14 encloses
Described image sensing unit is wound on around image sensing cell and electrically connects, wherein the passivation layer 13 is usually
The laminated construction that multilayer dielectricity layer stacking is formed, it is possible thereby to form the metal of more metal layers interconnection wherein
Interconnection structure, for the outer of the image sensing cell in connection image sensor chip and image sensing cell
MOS transistor circuit is enclosed, the top metal level of metal interconnection structure is finally formed on the surface of passivation layer 13
Discrete multiple connection gaskets.Therefore each pad 14 is the metal structure of more metal layers interconnection stack,
The pad back side is exactly connected the backside surface of Semiconductor substrate 10 by the reverse packaging process of image sensor chip.
Involved technique is known to the skilled person technology in step S1, including oxidation, pattern transfer,
The technique such as photoetching, doping, polysilicon deposition and metal deposit, etching, will not be repeated here.
Please continue to refer to Fig. 2A, in step s 2, can the surface of pad 14 by dispensing, draw glue,
The mode of printing rubber, plastic roll or photoetching process patterning glue forms adhesion layer 12, and the thickness of adhesion layer 12 is 200
Angstrom to 3000 angstroms, composition is chemical adhesive；Then package substrate 11 is glued with the front of Semiconductor substrate 10
It is combined.Can also be before the front adhesive of package substrate 11 and Semiconductor substrate 10, in pad 14
Surface forms supporting layer or forms supporting layer (not shown) on the surface of package substrate 11, with to image sensing
The photosensitive area 101 of device chip provides rational space, while for follow-up encapsulation step is provided a supporting role, keeping away
Exempt from package substrate and produce extruding with chip front side, damage image sensor chip.Adhesion layer 12 is formed in support
Between layer and pad 14.Preferably, package substrate 11 is more than 10 microns with the distance of the photosensitive area 101.
Please continue to refer to Fig. 2 B, in step s3, the method pair of wafer grinding or etching can be first passed through
The back side of Semiconductor substrate 10 carries out thinning, obtains the target thickness of Semiconductor substrate 10, and for example, 100 is micro-
Rice is to 200 microns；Then the method that etching is combined by photoetching forms groove at the back side of Semiconductor substrate 10
(not shown), etching groove stops at the bottom metal level backside surface of the bottom of pad 14.Wherein, it is brilliant
Round back reduction process can reduce the depth-to-width ratio of etching groove and follow-up filling, improve etching groove with
And the follow-up performance filled.
Fig. 2 C are refer to, in step s 4, is deposited in flute surfaces and the back surfaces of Semiconductor substrate 10
Insulating barrier 15 (i.e. the part of insulating barrier 15 is filled in the trench, the unfilled groove of thickness of insulating barrier),
And by photoetching, the method for etching, enable insulating barrier partly cover the back surfaces of Semiconductor substrate 10 with
And the bottom metal level of the pad 14 in covering groove is near the part surface of Semiconductor substrate 10.It is described
The material of insulating barrier 15 can be one or more combination in silica, silicon nitride, silicon oxynitride.
Fig. 2 D are refer to, in step s 4, after insulating barrier 15 is formed, is carved upwards successively in the trench
The outer peripheral each layer metal level of pad 14 that erosion insulating barrier 15 exposes, finally causes the outer of each pad 14
The metal level at edge is stepped.When forming the step structure, to the bottom metal level of pad 14 extremely
The etching degree of the top metal level of the pad 14 can uniformly successively decrease successively, to cause its bottom metal
Development length of the layer to its top metal level in trenched side-wall is uniformly lengthened successively.Such as pad at groove
14 are mainly formed by 3 layers of metal level, are successively bottom metal levels from the back side of Semiconductor substrate 10 to front
M1, metallic intermediate layer layer M2 and top metal level M3, in the trench successively to M1, M2, M3
Away from photosensitive area 101 outward flange etched in various degree after formed step structure in, M1 steps side
Edge is most short, M3 step edges are most long, and the surface and side of each step are metal, for it is rear
The continuous interconnection metal layer contact for being formed.In order to farthest avoid to package substrate 11 and imageing sensor half
The influence of the bond properties of conductor substrate 10, etches each layer metal level of pad 14 to form rank in the trench
During ladder-shaper structure, the top metal level at least retaining pad is not etched, and such as pad 14 is from Semiconductor substrate
10 back side to front is followed successively by M1, M2, M3 three-layer metal layer, retains M3 and does not etch, then for example welds
When disk has more than 4 layers of metal level, top metal level can be retained and secondary top layer metallic layer is not etched.
In other embodiments of the invention, in step S4 insulating barrier and the shape of the step structure of pad
Can be exchanged into order, i.e., after the etching groove of step S3 is completed, continue to etch weldering in step s 4
Each layer metal level in disk and form step structure, then in flute surfaces and Semiconductor substrate back table
Face depositing insulating layer 15 is simultaneously etched, and exposes each step of step structure.
Fig. 2 E are refer to, in step s 5, by the method for sputtering, plating or chemical plating in surface of insulating layer
Interconnection metal layer 16 is formed, and photoetching and etching are carried out to interconnection metal layer 16, form pre-designed figure
Case.The interconnection metal layer 16 is preferably the laminated construction that TiW and Cu is constituted, and wherein TiW is adhesion layer,
Cu is wiring layer.Interconnection metal layer 16 is on the position of pad 14 and exposed each surface of step structure
Contact, contact area is relatively more, and connection reliability is high.The depth-to-width ratio of groove is smaller simultaneously, metal wiring layer
16 filling capacity when being filled in the groove that pad 14 goes out is good, so that metal wiring layer 16 itself
Performance comparision reliability.
Please continue to refer to Fig. 2 E, in step s 6, formed on the surface of metal wiring layer 16 by depositing operation
Protective layer 17, to protect interconnection metal layer 16.And further photoetching, etch-protecting layer 17, with to be formed
The position of scolding tin salient point forms the opening (not shown) for exposing interconnection metal layer 16.
Refer to Fig. 2 F, in the step s 7, by the welding method that flows back, plant ball, evaporation, electroless plating method,
Galvanoplastic, Place method, soldering paste template method for printing or Printing Paste method form salient point 18 in aperture position, convex
Point 18 and the conductive contact of metal wiring layer 16.In the present embodiment, can be using reflow soldering process on weld pad
Salient point 18 is formed, reflow soldering process includes：First pass through plating or depositing operation forms solder layer, solder layer
Material can include aluminium, tin, silver, lead, copper, zinc, bismuth, indium, gold and antimony in one or more,
For example, tin, Xi Yin, tin-lead, SAC, tin silver-colored zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper,
Tin zinc indium or tin silver antimony etc., and activating agent is included in solder layer, then can employ nitrogen as to protect
Shield gas, taking the mode of heating of intensification-constant temperature-backflow (RSS) carries out Reflow Soldering, and salient point is formed in the opening
18.Specifically, the reflow soldering process carries out warming temperature first, from room temperature to 100 DEG C or so, with 1 DEG C
The heating rate of/s~2 DEG C/s steadily heats up；Then constant temperature method is carried out, the temperature range in constant temperature stage is
150 DEG C~250 DEG C, constant temperature time scope is 50s~100s；Finally carry out reflux operation, return time scope
It is 30s~60s, temperature range is 225 DEG C~250 DEG C.It should be noted that in other implementations of the invention
In example, can be printed by planting ball, evaporation, electroless plating method, galvanoplastic, Place method, soldering paste template
Method or Printing Paste method form solder bump, and this is not limited by the present invention.
Therefore, the method for packing of image sensor chip of the invention, first in the weldering of chip edge
The Semiconductor substrate position of tray bottom forms groove, and channel bottom exposes the back surfaces of pad；Then
Each layer metal level of each pad is repaired, pad edge is revised as step structure；Then shape in the trench
Into the interconnection metal layer of step structure described in conductive contact and on the interconnection metal layer of chip back surfaces
Scolding tin salient point is formed, so as to chip electric signal is transferred into chip back from chip front side；Interconnected with silicon perforation
Compare, because the channel bottom size for being formed is larger, the filling wiring metal layer process in follow-up groove is difficult
Degree reduces, it is to avoid due to the metal filled unreal problem for causing reliability bad in silicon perforation；Simultaneously because
Step structure increased the contact area of interconnection metal layer and pad, it is to avoid the cloth filled in the prior art
The unfavorable shadow that line metal level is only contacted with a top layer on surface of metal of pad or bottom metal surface
Ring, it is to avoid due to interconnection metal layer in silicon perforation and pad connection reliability bad problem；And due to
Avoid using silicon perforation interconnection technique, packaging technology simplifies, packaging cost reduction.
Fig. 2 F are refer to, the present invention also provides a kind of encapsulating structure of image sensor chip, including：
Semiconductor substrate 10；
Image sensor chip, is formed on the front of the Semiconductor substrate 10；
Groove, is formed at the back side of the Semiconductor substrate 10；
Multiple pads 14, are distributed in the Semiconductor substrate 10 of described image sensor chip circumference, and described
Pad 14 at groove is the step structure interconnected by more metal layers；
Insulating barrier 15, covers the back side of the Semiconductor substrate 10, and exposes each of the step structure
Individual ledge surface；
Interconnection metal layer 16, covers the platform of the insulating barrier 15 and the step structure for exposing
Rank surface, and contacted with the metal level of each step of the step structure；
Protective layer 17, covers the surface of interconnection metal layer 16, and with the exposure interconnection metal layer 16
Multiple openings；And
Salient point 18, set in said opening, and with the conductive contact of the interconnection metal layer 16.
Further, described image sensor chip is located on a wafer, is partly led including described on the wafer
Body substrate 10 and it is formed in positive at least one image sensor chip of Semiconductor substrate 10.
Further, the front of the wafer is also covered with passivation layer 13, the figure of described image sensor chip
As sensing unit (i.e. photosensitive area 101) and each pad 14 being distributed in around described image sensing unit
Partly it is formed in the passivation layer 13.
Further, in the step structure, bottom metal level to top metal level is in trenched side-wall
Development length uniformly lengthen successively.
Therefore, the encapsulating structure of the image sensor chip that the present invention is provided, by groove, stepped
Chip electric signal is transferred to chip by pad structure, interconnection metal layer, the structure of scolding tin salient point from chip front side
The back side, compared with silicon perforation is interconnected, structure is relatively easy, packaging cost reduction；And interconnection metal layer is filled out
The performance filled than being filled in traditional silicon perforation in the groove of depth-to-width ratio is high, stepped pad structure and cloth
The contact area of line metal level is big, thus avoid because interconnection metal layer is connected reliable with pad in silicon perforation
The bad problem of property.
Obviously, those skilled in the art can carry out various changes and modification without deviating from the present invention to invention
Spirit and scope.So, if it is of the invention these modification and modification belong to the claims in the present invention and its
Within the scope of equivalent technologies, then the present invention is also intended to comprising these changes and modification.
Claims (16)
1. a kind of method for packing of image sensor chip, it is characterised in that comprise the following steps：
Package substrate and image sensor chip are provided, the package substrate has transparent area, and described image is passed
Sensor chip is formed on the front of semi-conductive substrate, and described image sensor chip circumference semiconductor
Multiple pads are formed with substrate face, each pad is the metal structure interconnected by more metal layers；
The front of the package substrate and the Semiconductor substrate is bonded, wherein, the transparent area correspondence is described
The photosensitive area of image sensor chip；
The back side to the Semiconductor substrate is performed etching to form groove, and the groove exposes the pad
Bottom metal level；
The pad is etched so that the more metal layers of the pad form step structure, and are partly led described
The back side of body substrate forms insulating barrier, each ledge surface of step structure described in the insulating layer exposing；
Interconnection metal layer, the interconnection metal layer are formed in the insulating barrier and the step structure surface
Contacted with every layer of metal level of the step structure；
Protective layer is formed in the wiring metal layer surface, and etches the protective layer formation and expose the cloth
Multiple openings of line metal level；And
Salient point is set in said opening.
2. method for packing as claimed in claim 1, it is characterised in that described image sensor chip is provided
The step of include：
The Semiconductor substrate is provided；
At least one image sensing cell is formed on the front of the Semiconductor substrate, described image sensing is single
First region is the photosensitive area；
Multiple pads are formed around each image sensing cell.
3. method for packing as claimed in claim 2, it is characterised in that described image sensing unit and each
Individual pad is partly formed in the positive passivation layer of the Semiconductor substrate.
4. method for packing as claimed in claim 1, it is characterised in that using dispensing, draw glue, printing
Glue, plastic roll or photoetching process pattern the mode of glue, bond the package substrate and the Semiconductor substrate
Front.
5. method for packing as claimed in claim 1, it is characterised in that after the groove is formed, first
Each layer metal level of the pad at the groove is etched to some extent to form step structure, then in institute
The back side for stating Semiconductor substrate forms insulating barrier.
6. method for packing as claimed in claim 1, it is characterised in that after the groove is formed, first
Insulating barrier is formed at the back side of the Semiconductor substrate, the pad at the groove is then etched to some extent
Each layer metal level forming step structure.
7. the method for packing as described in claim 1 or 5 or 6, it is characterised in that formed described stepped
During structure, uniformly successively decrease successively from the bottom metal level of pad to the etching degree of its top metal level,
To cause the bottom metal level uniform successively in the development length of trenched side-wall to the top metal level
Lengthen.
8. method for packing as claimed in claim 7, it is characterised in that etching the pad at the groove
Each layer metal level at least retain it to be formed during step structure, in each layer metal level of the pad and most push up
Layer metal level is not etched.
9. method for packing as claimed in claim 1, it is characterised in that the insulating barrier include silica,
At least one in silicon nitride, silicon oxynitride and organic polymer.
10. method for packing as claimed in claim 1, it is characterised in that by the welding method that flows back, plant ball,
Evaporation, electroless plating method, galvanoplastic, Place method, soldering paste template method for printing or Printing Paste method are in opening
Position forms salient point.
11. method for packing as described in claim 1 or 10, it is characterised in that the material bag of the salient point
Include one or more in aluminium, tin, silver, lead, copper, zinc, bismuth, indium, gold and antimony.
A kind of 12. encapsulating structures of image sensor chip, it is characterised in that including：
Semiconductor substrate；
Image sensor chip, is formed on the front of the Semiconductor substrate；
Groove, is formed at the Semiconductor substrate back side；
Multiple pads, are distributed in the Semiconductor substrate of described image sensor chip circumference, and the groove
The pad at place is the step structure interconnected by more metal layers；
Insulating barrier, covers the back side of the Semiconductor substrate, and exposes the step structure each
Rank surface；
Interconnection metal layer, covers the step table of the insulating barrier and the step structure for exposing
Face, and contacted with the metal level of each step of the step structure；
Protective layer, covers the wiring metal layer surface, and open with the multiple for exposing the interconnection metal layer
Mouthful；And
Salient point, set in said opening, and with the interconnection metal layer conductive contact.
13. encapsulating structures as claimed in claim 12, it is characterised in that described image sensor chip position
Include Semiconductor substrate on a wafer, on the wafer and be formed on the Semiconductor substrate front
At least one image sensor chip.
14. encapsulating structures as claimed in claim 13, it is characterised in that the front of the wafer also covers
There is a passivation layer, the image sensing cell of described image sensor chip and be distributed in described image sensing unit
Each pad of surrounding is partly formed in the passivation layer.
15. encapsulating structures as claimed in claim 12, it is characterised in that in the step structure, most
Development length of the bottom metal layer to top metal level in trenched side-wall is uniformly lengthened successively.
16. encapsulating structures as claimed in claim 12, it is characterised in that the material of the salient point include aluminium,
One or more in tin, silver, lead, copper, zinc, bismuth, indium, gold and antimony.
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