CN113540069B - Chip stack packaging structure and chip stack packaging method - Google Patents
Chip stack packaging structure and chip stack packaging method Download PDFInfo
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- CN113540069B CN113540069B CN202110819499.9A CN202110819499A CN113540069B CN 113540069 B CN113540069 B CN 113540069B CN 202110819499 A CN202110819499 A CN 202110819499A CN 113540069 B CN113540069 B CN 113540069B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 321
- 230000001681 protective effect Effects 0.000 claims description 65
- 238000009429 electrical wiring Methods 0.000 claims description 56
- 239000003292 glue Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 19
- 229920001169 thermoplastic Polymers 0.000 claims description 11
- 239000004416 thermosoftening plastic Substances 0.000 claims description 11
- 238000003466 welding Methods 0.000 claims description 10
- 238000005538 encapsulation Methods 0.000 claims description 8
- 239000011253 protective coating Substances 0.000 claims description 7
- 239000011247 coating layer Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 7
- 239000012790 adhesive layer Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- -1 polyethylene Polymers 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 229920001155 polypropylene Polymers 0.000 description 2
- 229920000915 polyvinyl chloride Polymers 0.000 description 2
- 239000004800 polyvinyl chloride Substances 0.000 description 2
- 238000009504 vacuum film coating Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The embodiment of the invention provides a chip stack packaging structure and a chip stack packaging method, which relate to the technical field of semiconductor packaging.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip stack packaging structure and a chip stack packaging method.
Background
In the field of chip packaging, along with the development of technology, a structure of stacking a plurality of chips appears, and to current stacking technology, it generally adopts simple repeated stacking, and is higher to the overall arrangement requirement of a plurality of chips, and causes the interference each other easily when routing or welding, has undoubtedly improved the encapsulation degree of difficulty, and can't effectively utilize three-dimensional space to stack, causes product storage chip quantity not enough, and then leads to the product performance low.
Disclosure of Invention
The invention aims at providing a chip stack packaging structure and a chip stack packaging method, which can realize stacking of a plurality of chips, avoid mutual interference during wire bonding or welding among the chips, reduce packaging difficulty, improve the number of memory chips and improve product performance.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a chip stack package structure, including:
a base circuit board;
a first chip mounted on the base circuit board;
the protective covering glue layer is arranged on the base circuit board and coated outside the first chip;
the second chip is arranged on the protective covering layer;
the circuit connecting layer is arranged on the base circuit board and coated outside the protective coating layer;
the third chip is arranged on the circuit connection layer;
the encapsulating layer is arranged on the base circuit board and is coated outside the circuit connecting layer and the third chip;
the circuit connecting layer is provided with a first electric column, two ends of the first electric column penetrate through two side surfaces of the circuit connecting layer respectively, a third chip and a second chip are connected with two ends of the first electric column respectively, the third chip, the second chip and the circuit connecting layer are connected into a whole through the first electric column, and the circuit connecting layer is electrically connected with the base circuit board.
In an optional embodiment, the circuit connection layer includes an electrical wiring layer and a first dielectric layer, the electrical wiring layer is coated outside the protective covering layer, the first dielectric layer is coated outside the electrical wiring layer, the third chip is disposed on the first dielectric layer, the second chip is electrically connected with the electrical wiring layer, the third chip is electrically connected with the second chip through the first electrical column, and the electrical wiring layer is electrically connected with the base circuit board.
In an optional embodiment, the circuit connection layer further includes a second dielectric layer, the second dielectric layer is coated outside the protective covering layer, the electrical wiring layer is coated outside the second dielectric layer, and the second chip is attached to the second dielectric layer.
In an optional embodiment, a second electrical pillar is further disposed on the first dielectric layer, the second electrical pillar penetrates through the first dielectric layer and is connected with the electrical wiring layer, and the third chip is connected with the second electrical pillar and is electrically connected with the electrical wiring layer through the second electrical pillar.
In an alternative embodiment, the second chips and the third chips are multiple, the second chips and the third chips are in one-to-one correspondence, the first electrical column is disposed between each second chip and the corresponding third chip, the electrical wiring layer includes a first electrical layer and a second electrical layer, the first electrical layer and the second electrical layer are staggered, at least one first electrical column is disposed on the first electrical layer, and at least one first electrical column is disposed on the second electrical layer.
In an alternative embodiment, a base pad is disposed on the base circuit board, the base pad is disposed around the first chip, and the line connection layer is connected to the base pad and electrically connected to the base circuit board through the base pad.
In an alternative embodiment, the second chip is embedded on the protective covering layer, and the surface of the second chip is flush with the surface of the protective covering layer.
In an optional embodiment, the shape of the circuit connection layer is adapted to the protective covering layer, the protective covering layer includes a boss portion and a first surrounding portion, the first surrounding portion is annularly disposed around the boss portion, and the height of the boss portion relative to the base circuit board is greater than the height of the first surrounding portion relative to the base circuit board, so that the boss portion is disposed protruding relative to the first surrounding portion, at least one second chip is disposed on the boss portion, and at least one second chip is disposed on the first surrounding portion.
In an optional embodiment, the protective covering layer further includes a second surrounding portion, the second surrounding portion is disposed around the first surrounding portion in a surrounding manner, and a height of the second surrounding portion relative to the base circuit board is smaller than a height of the first surrounding portion relative to the base circuit board, so that the second surrounding portion and the first surrounding portion form a stepped structure, and at least one second chip is disposed on the second surrounding portion.
In a second aspect, the present invention provides a chip stack packaging method for preparing a chip stack packaging structure according to the foregoing embodiment, including:
attaching a first chip on a base circuit board;
a protective glue coating layer coated outside the first chip is arranged on the base circuit board;
a second chip is thermally pressed and attached on the protective covering glue layer;
a circuit connecting layer coated outside the protective coating layer and the second chip is arranged on the base circuit board;
a third chip is attached to the circuit connecting layer;
an encapsulation layer which is coated outside the circuit connection layer and the third chip is arranged on the base circuit board;
the circuit connecting layer is provided with a first electric column, two ends of the first electric column penetrate through two side surfaces of the circuit connecting layer respectively, a third chip and a second chip are connected with two ends of the first electric column respectively, the third chip, the second chip and the circuit connecting layer are connected into a whole through the first electric column, and the circuit connecting layer is electrically connected with the base circuit board.
The beneficial effects of the embodiment of the invention include, for example:
according to the chip laminated packaging structure provided by the invention, the first chip is mounted on the base circuit board, the second chip is arranged on the protective coating layer coated outside the first chip, the third chip is arranged on the circuit connecting layer coated outside the protective coating layer, the first electric column is further arranged on the circuit connecting layer, the third chip, the second chip and the circuit connecting layer are electrically connected into a whole through the first electric column, and the circuit connecting layer is electrically connected with the base circuit board, so that the electric connection among the third chip, the second chip and the base circuit board is realized. Compared with the prior art, the stacking structure has the advantages that the first chip is mounted, the second chip and the third chip are respectively arranged on the upper side and the lower side of the circuit connecting layer, the chips are stacked, mutual interference among the chips is avoided, wire bonding is not needed, the packaging difficulty is reduced, the number of memory chips is increased, and the product performance is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is an overall schematic diagram of a chip stack package structure according to a first embodiment of the present invention;
fig. 2 is a schematic partial view of a chip stack package structure according to a first embodiment of the present invention at a first viewing angle;
fig. 3 is a schematic partial view of a chip stack package structure according to a first embodiment of the present invention under a second view angle;
fig. 4 is an overall schematic diagram of a chip stack package structure according to a second embodiment of the present invention;
FIG. 5 is a schematic diagram of a portion of a chip stack package structure according to a second embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a portion of a stacked chip package structure according to a third embodiment of the present invention;
FIG. 7 is a schematic diagram of a portion of a chip stack package structure according to a fourth embodiment of the present invention;
FIG. 8 is a block diagram illustrating steps of a chip stack package method according to a fifth embodiment of the present invention;
fig. 9 to 14 are process flow diagrams of a chip stack package method according to a fifth embodiment of the invention.
Icon: 100-chip stack package structure; 110-a base circuit board; 111-substrate pads; 120-a first chip; 130-protecting the covering glue layer; 131-a boss portion; 133-a first surrounding portion; 135-a second surrounding portion; 140-a second chip; 150-a line connection layer; 151-an electrical wiring layer; 153-a first dielectric layer; 155-a second dielectric layer; 157-a first electrical layer; 159-a second electrical layer; 160-a third chip; 170-an encapsulation layer; 180-a first electrical pillar; 190-second electrical pillar.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
As disclosed in the background art, in the existing packaging structure, the chips are often stacked together directly and then are subjected to plastic packaging, and the structure is unstable and easy to collapse during packaging, and as the chips are required to be electrically connected with the substrate, no matter wire bonding or conductive holes are required to be electrically connected, the process steps are increased, and the packaging difficulty is improved. And the chips are easy to interfere with each other, so that the layout requirement on the chips is high, the structure is complex, the breakthrough of the number of the chips is difficult to realize, the number of the stacked chips is limited, and the performance of the device is reduced.
In order to solve the above-mentioned problems, the present invention provides a chip stack package structure and a chip stack package method, and it should be noted that the features in the embodiments of the present invention may be combined with each other without collision.
First embodiment
Referring to fig. 1 to 3, the present embodiment provides a chip stack package structure 100, which has a simple structure and low chip layout requirements, and avoids mutual interference between chips, reduces packaging difficulty, and can stack more chips at the same time, thereby improving device performance.
The chip stack package structure 100 provided in this embodiment includes a substrate circuit board 110, a first chip 120, a protective covering layer 130, a second chip 140, a circuit connection layer 150, a third chip 160 and an encapsulation layer 170, where the first chip 120 is mounted on the substrate circuit board 110, the protective covering layer 130 is disposed on the substrate circuit board 110 and covers the first chip 120, the second chip 140 is disposed on the protective covering layer 130, the circuit connection layer 150 is disposed on the substrate circuit board 110 and covers the circuit connection layer 150 outside the protective covering layer 130, the third chip 160 is disposed on the circuit connection layer 150, the encapsulation layer is disposed on the substrate circuit board 110 and covers the circuit connection layer 150 and the third chip 160, the circuit connection layer 150 is provided with a first electrical pillar 180, two ends of the first electrical pillar 180 respectively penetrate through two side surfaces of the circuit connection layer 150, the third chip 160 and the second chip 140 are respectively connected with two ends of the first electrical pillar 180, and the third chip 160, the second chip 140 and the circuit connection layer 150 are electrically connected with the substrate circuit connection layer 110 through the first electrical pillar 180.
In this embodiment, the first chip 120, the second chip 140 and the third chip 160 may be the same type of chip, or may be different types of chips, for example, the first chip 120 is a control chip, and the second chip 140 and the third chip 160 are memory chips. Meanwhile, the first chip 120, the second chip 140 and the third chip 160 may have the same or different structural dimensions, and in case of different dimensions, for example, when the first chip 120 has a larger dimension, the first chip 120 is directly mounted on the base circuit board 110, and the second chip 140 and the third chip 160 are mounted on the upper and lower sides of the circuit connection layer 150, so that the overall structure is more compact, and the improvement of the stacking number of the second chip 140 and the third chip 160 is more facilitated.
It should be noted that, in the present embodiment, the second chips 140 and the third chips 160 are plural, the second chips 140 and the third chips 160 are disposed in one-to-one correspondence, and the first electrical columns 180 are disposed between each second chip 140 and the corresponding third chip 160. The plurality of second chips 140 are disposed on the protective covering layer 130 and attached to the lower surface of the circuit connection layer 150, and the plurality of second chips 140 are disposed at different positions of the protective covering layer 130. The third chips 160 are attached to the upper surface of the circuit connection layer 150 and are located at different positions of the circuit connection layer 150. Of course, the specific number of the second chip 140 and the third chip 160 is not limited herein, and the number of the second chip 140 and the third chip 160 may be reasonably set according to the size of the second chip 140 and the third chip 160 and the requirement of the package size.
In this embodiment, the base circuit board 110 is provided with a base pad 111, the base pad 111 is surrounded around the first chip 120, and the line connection layer 150 is connected to the base pad 111 and electrically connected to the base circuit board 110 through the base pad 111. Specifically, the plurality of base pads 111 are provided around the plurality of base pads 111 and are used to define a mounting area on the base circuit board 110, and the first chip 120 is mounted in the middle of the mounting area, so that the plurality of base pads 111 are provided around the first chip 120, and when the wire connection layer 150 is formed, the wire connection layer 150 is in electrical contact with at least one base pad 111, thereby achieving electrical connection between the wire connection layer 150 and the base circuit board 110.
In this embodiment, the protective glue layer 130 is coated outside the first chip 120, the glue layer can be coated on the surface of the first chip 120 by a vacuum film coating machine, and the edge of the protective glue layer 130 is limited in the mounting area defined by the substrate pad 111. For edge definition of the protective covering glue layer 130, the base bonding pad 111 can be set to a certain height and can be realized by using a glue blocking mode of the base bonding pad 111, or the base bonding pad 111 can be directly set to be in a ring-shaped protruding structure, so that the glue layer is directly blocked. Specifically, the protective covering layer 130 is a thermoplastic adhesive, such as a polymer material including polyethylene, polypropylene, and polyvinyl chloride, and is deformed to a certain extent when heated, so that the second chip 140 is conveniently attached by a hot pressing process.
It should be noted that, in this embodiment, the first chip 120 is a flip chip, the mounting area of the substrate circuit board 110 is provided with an electrical connection pad, the bottom of the first chip 120 is provided with a connection bump, and the connection bump and the electrical connection pad are soldered together, thereby realizing flip-chip electrical connection of the first chip 120. The specific mounting structure of the first chip 120 may refer to an existing flip chip. Of course, the first chip 120 may be a front-mounted chip, that is, the first chip 120 is electrically connected to the base circuit board 110 by wire bonding, and the protective covering layer 130 needs to cover the wire bonding.
In the present embodiment, the second chip 140 is embedded on the protective covering layer 130, and the surface of the second chip 140 is flush with the surface of the protective covering layer 130. Specifically, after the protective covering layer 130 is formed, since the protective covering layer 130 is made of thermoplastic glue, the second chip 140 needs to be mounted by a hot-press welding process, and the substrate is heated by using the welding head and the rail on the hot-press chip mounter, so that the protective covering layer 130 is softened after being heated, then the second chip 140 is mounted on the upper surface of the thermoplastic glue layer, the second chip 140 is flush with the surface of the thermoplastic glue layer, and after cooling, the second chip 140 is coated by the thermoplastic glue, and the surface of the second chip 140 leaks.
In this embodiment, the shape of the circuit connection layer 150 is adapted to the protective covering layer 130, the protective covering layer 130 includes a boss portion 131 and a first surrounding portion 133, the first surrounding portion 133 is disposed around the boss portion 131, and the height of the boss portion 131 relative to the base circuit board 110 is greater than the height of the first surrounding portion 133 relative to the base circuit board 110, so that the boss portion 131 is disposed protruding relative to the first surrounding portion 133, at least one second chip 140 is disposed on the boss portion 131, and at least one second chip 140 is disposed on the first surrounding portion 133. Specifically, since the first chip 120 is attached, when the protective cover layer 130 is formed, the protective cover layer 130 located at the middle position is protruded upward to cover the first chip 120, and at the same time, the wire connection layer 150 is protruded upward at the middle position, and the boss portion 131 is formed, the first surrounding portion 133 is formed at the surrounding portion, the first surrounding portion 133 and the boss portion 131 are integrally formed, the upper and lower surfaces of the boss portion 131 may be provided with the plurality of second chips 140 and the third chips 160, and the surface of the first surrounding portion 133 may be provided with the plurality of second chips 140 and the third chips 160.
It should be noted that, the wiring connection layer 150 may be formed by one of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), sputtering, electroplating, or electroless plating.
In this embodiment, the circuit connection layer 150 includes an electrical wiring layer 151 and a first dielectric layer 153, the electrical wiring layer 151 is coated outside the protective covering layer 130, the first dielectric layer 153 is coated outside the electrical wiring layer 151, the third chip 160 is disposed on the first dielectric layer 153, the second chip 140 is electrically connected to the electrical wiring layer 151, the third chip 160 is electrically connected to the second chip 140 through the first electrical pillar 180, and the electrical wiring layer 151 is electrically connected to the base circuit board 110.
Specifically, after the protective covering layer 130 is formed and the second chip 140 is disposed on the protective covering layer 130, an electrical wiring layer 151 covering the second chip 140 and the protective covering layer 130 may be formed by covering and wiring, and then a first dielectric layer 153 is formed on the surface of the electrical wiring layer 151, where the first dielectric layer 153 is made of a dielectric material, such as an amine cured epoxy material, an epoxy polymer, polyimide, and the like, and by disposing the first dielectric layer 153, protection of the electrical wiring layer 151 can be effectively achieved, and problems of water vapor/moisture or foreign matter pollution/ESD and the like are avoided, and reliability of the product is improved.
It should be noted that, in the present embodiment, the first electrical pillar 180 penetrates through the first dielectric layer 153 and the electrical wiring layer 151 at the same time, and in the present embodiment, the second chip 140 may be electrically connected to the electrical wiring layer 151 through a pad, and may be electrically connected to the third chip 160 through the first electrical pillar 180. In forming the first electrical pillar 180, after the first dielectric layer 153 is formed, holes may be formed on the first dielectric layer 153 and the electrical wiring layer 151 by means of laser holes, and then metal may be sputtered to form the first electrical pillar 180. Of course, the first electrical pillar 180 may be formed by recessing and then filling with conductive adhesive, and the specific molding method of the first electrical pillar 180 is not limited herein.
In other preferred embodiments of the present invention, the circuit connection layer 150 may only include the electrical wiring layer 151, the third chip 160 and the second chip 140 are disposed on the upper and lower sides of the electrical wiring layer 151, respectively, and at least one of the third chip 160 and the second chip 140 is directly electrically connected to the electrical wiring layer 151 through bonding pads. The specific arrangement is not described here in detail.
In summary, the present embodiment provides a chip stack package structure 100, which is formed by attaching the first chip 120 to the base circuit board 110, disposing the second chip 140 on the protective covering layer 130 covered outside the first chip 120, disposing the third chip 160 on the circuit connecting layer 150 covered outside the protective covering layer 130, and disposing the first electrical column 180 on the circuit connecting layer 150, wherein the third chip 160, the second chip 140 and the circuit connecting layer 150 are electrically connected together through the first electrical column 180, and the circuit connecting layer 150 is electrically connected with the base circuit board 110, so that the electrical connection among the third chip 160, the second chip 140 and the base circuit board 110 is realized, meanwhile, the stacking of the first chip 120, the second chip 140 and the third chip 160 is completed, the stacking structure avoids the mutual interference among the chips, and no wire bonding is required, thereby reducing the packaging difficulty, improving the number of memory chips, and improving the product performance.
Second embodiment
Referring to fig. 4 and 5, the basic structure and principle of the chip stack package structure 100 according to the present embodiment and the technical effects thereof are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the embodiment is not mentioned. The present embodiment is different from the first embodiment in the wiring connection layer 150.
In this embodiment, the circuit connection layer 150 includes an electrical wiring layer 151, a first dielectric layer 153 and a second dielectric layer 155, the second dielectric layer 155 is coated outside the protective covering layer 130, the electrical wiring layer 151 is coated outside the second dielectric layer 155, the first dielectric layer 153 is coated outside the electrical wiring layer 151, a third chip 160 is disposed on the first dielectric layer 153, the third chip 160 is electrically connected to the second chip 140 through a first electrical pillar 180, the electrical wiring layer 151 is electrically connected to the substrate circuit board 110, and the second chip 140 is mounted on the second dielectric layer 155.
In this embodiment, the upper and lower sides of the electrical wiring layer 151 are respectively coated with the first dielectric layer 153 and the second dielectric layer 155, and the electrical wiring layer 151 can be better protected by the double-layer dielectric layer.
In this embodiment, a second electrical pillar 190 is further disposed on the first dielectric layer 153, the second electrical pillar 190 penetrates through the first dielectric layer 153 and is connected to the electrical wiring layer 151, and the third chip 160 is connected to the second electrical pillar 190 and is electrically connected to the electrical wiring layer 151 through the second electrical pillar 190. Specifically, the second electrical pillar 190 may be formed by sputtering metal after laser drilling, and the second electrical pillar 190 and the first electrical pillar 180 may be formed together.
In this embodiment, the second electrical pillar 190 may electrically connect the third chip 160 and the electrical wiring layer 151 as a whole, and then electrically connect the second chip 140 and the third chip 160 as a whole through the first electrical pillar 180, thereby ensuring the electrical connection effect and avoiding the occurrence of poor conductive contact.
According to the chip stack package structure 100 provided by the embodiment, the first dielectric layer 153 and the second dielectric layer 155 are arranged on the upper side and the lower side of the electrical wiring layer 151, so that the electrical wiring layer 151 can be better protected, and the reliability of a device is further improved.
Third embodiment
Referring to fig. 6, the present embodiment provides a chip stack package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the embodiment is not mentioned. The present embodiment is different from the first embodiment in the wiring connection layer 150.
In this embodiment, the circuit connection layer 150 includes an electrical wiring layer 151, a first dielectric layer 153 and a second dielectric layer 155, the second dielectric layer 155 is coated outside the protective covering layer 130, the electrical wiring layer 151 is coated outside the second dielectric layer 155, the first dielectric layer 153 is coated outside the electrical wiring layer 151, a third chip 160 is disposed on the first dielectric layer 153, the third chip 160 is electrically connected to the second chip 140 through a first electrical pillar 180, the electrical wiring layer 151 is electrically connected to the substrate circuit board 110, and the second chip 140 is mounted on the second dielectric layer 155.
In this embodiment, the second chips 140 and the third chips 160 are multiple, the second chips 140 and the third chips 160 are arranged in a one-to-one correspondence, a first electrical pillar 180 is disposed between each second chip 140 and the corresponding third chip 160, the electrical wiring layer 151 includes a first electrical layer 157 and a second electrical layer 159, the first electrical layer 157 and the second electrical layer 159 are arranged in staggered layers, at least one first electrical pillar 180 is disposed on the first electrical layer 157, and at least one first electrical pillar 180 is disposed on the second electrical layer 159.
In this embodiment, the first electrical layer 157 and the second electrical layer 159 are disposed in a staggered manner, and at least one first electrical pillar 180 is disposed on the first electrical layer 157 and is directly electrically connected to at least one second chip 140 and at least one third chip 160, and at least one first electrical pillar 180 is disposed on the second electrical layer 159 and is directly electrically connected to at least one second chip 140 and at least one third chip 160. By adopting staggered layer design and utilizing different electric layers to connect different chips, the wiring length can be greatly reduced, and the chip transmission efficiency is improved. Meanwhile, according to the types of the second chip 140 and the third chip 160 which are mounted, the welding line widths of different electrical layers can be designed, for example, the welding line width of the first electrical layer 157 is designed to be 35 μm, so that the size of the bonding pad on the corresponding second chip 140 and third chip 160 is designed to be 55 μm, the welding line width of the second electrical layer 159 is designed to be 55 μm, and the size of the bonding pad on the second chip 140 and third chip 160 is designed to be 75 μm, thereby realizing that the second chip 140/third chip 160 of different types are mounted on the first electrical layer 157 and the second electrical layer 159 respectively, and improving the mounting adaptability.
Of course, the electrical wiring layer 151 may also have a multi-layer electrical layer structure, and the multi-layer electrical layers are designed in a staggered manner, which can be suitable for more chip types and greatly reduce the wiring length.
Fourth embodiment
Referring to fig. 7, the present embodiment provides a chip stack package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the embodiment is not mentioned.
In this embodiment, the protective covering layer 130 includes a boss portion 131, a first surrounding portion 133 and a second surrounding portion 135, the first surrounding portion 133 is disposed around the boss portion 131, and the height of the boss portion 131 relative to the base circuit board 110 is greater than the height of the first surrounding portion 133 relative to the base circuit board 110, so that the boss portion 131 is disposed protruding with respect to the first surrounding portion 133, at least one second chip 140 is disposed on the boss portion 131, and at least one second chip 140 is disposed on the first surrounding portion 133. The second surrounding portion 135 is disposed around the first surrounding portion 133, and the height of the second surrounding portion 135 relative to the base circuit board 110 is smaller than the height of the first surrounding portion 133 relative to the base circuit board 110, so that the second surrounding portion 135 and the first surrounding portion 133 form a stepped structure, and at least one second chip 140 is also disposed on the second surrounding portion 135.
In the present embodiment, the boss portion 131, the first surrounding portion 133 and the second surrounding portion 135 form a stepped boss structure, so that a plurality of second chips 140 can be respectively arranged on different step surfaces, further improving the stacking number of chips. The stepped structure in this embodiment has three layers, that is, the boss portion 131, the first surrounding portion 133, and the second surrounding portion 135 respectively form three step surfaces. Of course, the number of layers of the stepped structure may be four, five or six, and the number of steps of the protective covering layer 130 is not limited herein.
Fifth embodiment
Referring to fig. 8, the present embodiment provides a chip stack packaging method for preparing the chip stack packaging structure 100 as provided in the first embodiment, the second embodiment, the third embodiment or the fourth embodiment, the method including the steps of:
s1: the first chip 120 is mounted on the base circuit board 110.
Referring to fig. 9 in combination, specifically, a base circuit board 110 is provided, on which base circuit board 110 is designed a base pad 111 and an electrical connection pad, the base pad 111 being disposed around and circumscribing a mounting region, the electrical connection pad being located in the mounting region. The first chip 120 is mounted in the mounting area, where the first chip 120 is a flip chip, and the connection bumps on the first chip 120 are soldered with the electrical connection pads, so as to connect the first chip 120 with the substrate circuit board 110.
S2: a protective cover layer 130 is disposed on the base circuit board 110 and covers the first chip 120.
Referring to fig. 10 in combination, specifically, the surface of the first chip 120 is covered with the adhesive layer by a vacuum film coating machine, the protective adhesive layer 130 is formed after curing, and the edge of the protective adhesive layer 130 is limited to the mounting area defined by the substrate pad 111. For edge definition of the protective covering glue layer 130, the base bonding pad 111 can be set to a certain height and can be realized by using a glue blocking mode of the base bonding pad 111, or the base bonding pad 111 can be directly set to be in a ring-shaped protruding structure, so that the glue layer is directly blocked.
In the present embodiment, the protective covering layer 130 is a thermoplastic adhesive, such as a polymer material of polyethylene, polypropylene, polyvinyl chloride, etc., which is deformed to a certain extent when heated, thereby facilitating the subsequent process.
S3: the second chip 140 is thermally pressed and mounted on the protective cover adhesive layer 130.
Referring to fig. 11 in detail, after the protective covering layer 130 is formed, since the protective covering layer 130 is made of thermoplastic glue, the second chip 140 can be mounted by a hot-press welding process, and the substrate is heated by the welding head and the track on the hot-press chip mounter, so that the protective covering layer 130 is softened after being heated, then the second chip 140 is mounted on the upper surface of the thermoplastic glue layer, and the second chip 140 is flush with the surface of the thermoplastic glue layer, and after cooling, the second chip 140 is covered by the thermoplastic glue and leaks out of the surface of the second chip 140.
S4: a wire connection layer 150 is disposed on the base circuit board 110 and covers the protective cover layer 130 and the second chip 140.
Specifically, referring to fig. 12, after the thermocompression bonding of the second chip 140 is completed, the predetermined RDL electrical layer position is masked with a photomask and is not exposed, then the unexposed area is removed by a development process using a developing solution in a spray manner, the RDL electrical wiring layer 151 position is leaked out, a groove is formed, and then the RDL wiring is completed at the groove again using an exposure development technique. Wherein the heat conducting holes can be formed together in the exposure and development process. Meanwhile, the RDL electrical wiring layer 151 may be prepared by one of a physical vapor deposition Process (PVD), a chemical vapor deposition process (CVD), sputtering, electroplating, or electroless plating.
In the case of forming the chip stack package structure 100 according to the first embodiment, after the electrical wiring layer 151 is formed, a dielectric material is coated on the surface of the electrical wiring layer again to form the first dielectric layer 153, thereby realizing protection.
In forming the chip stack package structure 100 according to the second embodiment, before forming the electrical wiring layer 151, a dielectric material needs to be coated on the protective covering layer 130 to form the second dielectric layer 155, so as to realize protection.
In forming the chip stack package structure 100 provided in the third embodiment, it is necessary to separately provide the electrical wiring layers 151 and to provide different electrical layers in a staggered manner.
After forming the wiring connection layer 150, it is further necessary to form a slot on the wiring connection layer 150 through a laser drilling process, and then sputter metal to form the first electrical pillar 180.
S5: a third chip 160 is mounted on the line connection layer 150.
Referring to fig. 13 in combination, specifically, the third chip 160 is mounted on the circuit connection layer 150, and the third chip 160 is connected with the first electrical pillar 180, so that the second chip 140, the third chip 160, and the circuit connection layer 150 are electrically connected as one body.
S6: an encapsulation layer 170 is disposed on the base circuit board 110 to encapsulate the wire connection layer 150 and the third chip 160.
Referring to fig. 14 in combination, specifically, the connected structure is protected by plastic molding to form an encapsulation layer 170, and after tin balls are planted on the back surface of the substrate by a ball planting process, the product is cut into single pieces by a cutting process to complete the manufacturing process.
In the embodiment, a first electrical column 180 is disposed on the circuit connection layer 150, two ends of the first electrical column 180 respectively penetrate through two side surfaces of the circuit connection layer 150, the third chip 160 and the second chip 140 are respectively connected with two ends of the first electrical column 180, the third chip 160, the second chip 140 and the circuit connection layer 150 are electrically connected together through the first electrical column 180, and the circuit connection layer 150 is electrically connected with the substrate circuit board 110.
In summary, the present embodiment provides a chip stacking packaging method, in which the first chip 120 is mounted on the base circuit board 110, the second chip 140 is disposed on the protective covering layer 130 covered outside the first chip 120, the third chip 160 is disposed on the circuit connecting layer 150 covered outside the protective covering layer 130, the first electrical column 180 is further disposed on the circuit connecting layer 150, the third chip 160, the second chip 140 and the circuit connecting layer 150 are electrically connected together through the first electrical column 180, and the circuit connecting layer 150 is electrically connected with the base circuit board 110, so that the electrical connection among the third chip 160, the second chip 140 and the base circuit board 110 is realized, meanwhile, the stacking of the first chip 120, the second chip 140 and the third chip 160 is completed, the stacking structure avoids the mutual interference among the chips, wire bonding is not required, the packaging difficulty is reduced, the number of memory chips is improved, and the product performance is improved.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A chip stack package structure, comprising:
a base circuit board;
a first chip mounted on the base circuit board;
the protective covering glue layer is arranged on the base circuit board and coated outside the first chip;
the second chip is arranged on the protective covering layer;
the circuit connecting layer is arranged on the base circuit board and coated outside the protective coating layer;
the third chip is arranged on the circuit connection layer;
the encapsulating layer is arranged on the base circuit board and is coated outside the circuit connecting layer and the third chip;
the circuit connecting layer is provided with a first electric column, two ends of the first electric column penetrate through two side surfaces of the circuit connecting layer respectively, the third chip and the second chip are connected with two ends of the first electric column respectively, the third chip, the second chip and the circuit connecting layer are electrically connected into a whole through the first electric column, and the circuit connecting layer is electrically connected with the base circuit board;
the protective covering glue layer is made of thermoplastic glue, the second chip is embedded on the protective covering glue layer through a hot-press welding process, and the surface of the second chip is flush with the surface of the protective covering glue layer.
2. The chip stack package structure of claim 1, wherein the circuit connection layer comprises an electrical wiring layer and a first dielectric layer, the electrical wiring layer is coated outside the protective coating layer, the first dielectric layer is coated outside the electrical wiring layer, the third chip is disposed on the first dielectric layer, the second chip is electrically connected with the electrical wiring layer, the third chip is electrically connected with the second chip through the first electrical pillar, and the electrical wiring layer is electrically connected with the substrate circuit board.
3. The chip stack package structure of claim 2, wherein the circuit connection layer further comprises a second dielectric layer, the second dielectric layer is coated outside the protective covering layer, the electrical wiring layer is coated outside the second dielectric layer, and the second chip is mounted on the second dielectric layer.
4. The chip stack package structure according to claim 2 or 3, wherein a second electrical pillar is further disposed on the first dielectric layer, the second electrical pillar penetrates through the first dielectric layer and is connected to the electrical wiring layer, and the third chip is connected to the second electrical pillar and is electrically connected to the electrical wiring layer through the second electrical pillar.
5. The chip stack package structure according to claim 2 or 3, wherein the second chips and the third chips are plural, the plural second chips and the plural third chips are disposed in one-to-one correspondence, the first electrical pillar is disposed between each second chip and the corresponding third chip, the electrical wiring layer includes a first electrical layer and a second electrical layer, the first electrical layer and the second electrical layer are disposed in staggered layers, at least one first electrical pillar is disposed on the first electrical layer, and at least one first electrical pillar is disposed on the second electrical layer.
6. The chip stack package structure according to claim 1, wherein a base pad is disposed on the base circuit board, the base pad is disposed around the first chip, and the wiring connection layer is connected to the base pad and electrically connected to the base circuit board through the base pad.
7. The chip stack package structure according to claim 1, wherein the shape of the circuit connection layer is adapted to the protective cover layer, the protective cover layer includes a boss portion and a first surrounding portion, the first surrounding portion is disposed around the boss portion, and the boss portion is greater than the first surrounding portion with respect to the base circuit board, so that the boss portion is disposed in a protruding manner with respect to the first surrounding portion, at least one second chip is disposed on the boss portion, and at least one second chip is disposed on the first surrounding portion.
8. The chip stack package structure according to claim 7, wherein the protective cover layer further comprises a second surrounding portion, the second surrounding portion is disposed around the first surrounding portion in a surrounding manner, and a height of the second surrounding portion with respect to the base circuit board is smaller than a height of the first surrounding portion with respect to the base circuit board, so that the second surrounding portion and the first surrounding portion form a stepped structure, and at least one second chip is disposed on the second surrounding portion.
9. A method for chip stack packaging, for preparing the chip stack packaging structure according to claim 1, comprising:
attaching a first chip on a base circuit board;
a protective glue coating layer coated outside the first chip is arranged on the base circuit board;
a second chip is thermally pressed and attached on the protective covering glue layer;
a circuit connecting layer coated outside the protective coating layer and the second chip is arranged on the base circuit board;
a third chip is attached to the circuit connecting layer;
an encapsulation layer which is coated outside the circuit connection layer and the third chip is arranged on the base circuit board;
the circuit connecting layer is provided with a first electric column, two ends of the first electric column penetrate through two side surfaces of the circuit connecting layer respectively, a third chip and a second chip are connected with two ends of the first electric column respectively, the third chip, the second chip and the circuit connecting layer are connected into a whole through the first electric column, and the circuit connecting layer is electrically connected with the base circuit board.
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