CN113540069A - Chip lamination packaging structure and chip lamination packaging method - Google Patents
Chip lamination packaging structure and chip lamination packaging method Download PDFInfo
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- CN113540069A CN113540069A CN202110819499.9A CN202110819499A CN113540069A CN 113540069 A CN113540069 A CN 113540069A CN 202110819499 A CN202110819499 A CN 202110819499A CN 113540069 A CN113540069 A CN 113540069A
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- 239000010410 layer Substances 0.000 claims description 264
- 239000000758 substrate Substances 0.000 claims description 69
- 238000009429 electrical wiring Methods 0.000 claims description 56
- 239000012790 adhesive layer Substances 0.000 claims description 38
- 239000000853 adhesive Substances 0.000 claims description 35
- 230000001070 adhesive effect Effects 0.000 claims description 35
- 239000011247 coating layer Substances 0.000 claims description 26
- 239000011253 protective coating Substances 0.000 claims description 7
- 238000007731 hot pressing Methods 0.000 claims description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Abstract
The embodiment of the invention provides a chip lamination packaging structure and a chip lamination packaging method, relating to the technical field of semiconductor packaging, wherein the chip lamination packaging structure comprises a base circuit board, a first chip, a protective covering glue layer, a second chip, a circuit connecting layer, a third chip and an encapsulating layer, the first chip is pasted on the base circuit board, the second chip is arranged on the protective covering glue layer covering the first chip, the third chip is arranged on the circuit connecting layer covering the protective covering glue layer, the first electric column is also arranged on the circuit connecting layer, the third chip, the second chip and the circuit connecting layer are electrically connected into a whole through the first electric column, and meanwhile, the first chip, the second chip and the third chip are stacked, the stacking structure avoids mutual interference among the chips, does not need routing, and reduces the packaging difficulty, and the number of the memory chips is increased, and the product performance is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip lamination packaging structure and a chip lamination packaging method.
Background
In the chip package field, along with the development of technique, the structure that a plurality of chips piled up has appeared, to current pile up the technique, what its adopted usually is that simple repetition piles up, and is higher to the overall arrangement requirement of a plurality of chips, and causes the interference each other easily when routing or welding, has improved the encapsulation degree of difficulty undoubtedly, and can't effectively utilize three-dimensional space to pile up, causes product storage chip quantity not enough, and then leads to producing the property ability low.
Disclosure of Invention
The invention aims to provide a chip lamination packaging structure and a chip lamination packaging method, which can realize the stacking of a plurality of chips, simultaneously avoid the mutual interference of the plurality of chips during routing or welding, reduce the packaging difficulty, improve the number of storage chips and improve the product performance.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a chip stack package structure, including:
a base circuit board;
a first chip mounted on the base circuit board;
the protective adhesive coating layer is arranged on the substrate circuit board and covers the first chip;
the second chip is arranged on the protective adhesive-coated layer;
the circuit connecting layer is arranged on the substrate circuit board and is coated outside the protective coating layer;
a third chip disposed on the line connection layer;
the encapsulating layer is arranged on the substrate circuit board and wraps the circuit connecting layer and the third chip;
the circuit comprises a circuit connecting layer, a first electric column, a second electric column, a third chip, a second chip, a circuit connecting layer and a base circuit board, wherein the circuit connecting layer is provided with the first electric column, two ends of the first electric column are respectively penetrated to two side surfaces of the circuit connecting layer, the third chip and the second chip are respectively connected with two ends of the first electric column, the third chip, the second chip and the circuit connecting layer are connected into a whole through the first electric column, and the circuit connecting layer is electrically connected with the base circuit board.
In an optional embodiment, the circuit connection layer includes an electrical wiring layer and a first dielectric layer, the electrical wiring layer is coated outside the protective rubber coating layer, the first dielectric layer is coated outside the electrical wiring layer, the third chip is arranged on the first dielectric layer, the second chip is electrically connected with the electrical wiring layer, the third chip is electrically connected with the second chip through the first electrical column, and the electrical wiring layer is electrically connected with the substrate circuit board.
In an optional embodiment, the circuit connection layer further includes a second dielectric layer, the second dielectric layer is wrapped outside the protective rubber-coated layer, the electrical wiring layer is wrapped outside the second dielectric layer, and the second chip is attached to the second dielectric layer.
In an optional embodiment, a second electrical pillar is further disposed on the first dielectric layer, the second electrical pillar penetrates through the first dielectric layer and is connected to the electrical wiring layer, and the third chip is connected to the second electrical pillar and is electrically connected to the electrical wiring layer through the second electrical pillar.
In an optional implementation manner, the second chip and the third chip are multiple, the second chip and the third chip are arranged in a one-to-one correspondence manner, the first electrical pillar is arranged between each second chip and the corresponding third chip, the electrical wiring layer includes a first electrical layer and a second electrical layer, the first electrical layer and the second electrical layer are arranged in a staggered manner, the first electrical layer is provided with at least one first electrical pillar, and the second electrical layer is provided with at least one first electrical pillar.
In an optional embodiment, a substrate pad is disposed on the substrate circuit board, the substrate pad surrounds the first chip, and the circuit connection layer is connected to the substrate pad and electrically connected to the substrate circuit board through the substrate pad.
In an optional embodiment, the second chip is embedded in the protection adhesive layer, and a surface of the second chip is flush with a surface of the protection adhesive layer.
In an optional embodiment, the circuit connection layer has a shape adapted to the protective adhesive coating layer, the protective adhesive coating layer includes a boss portion and a first surrounding portion, the first surrounding portion is disposed around the boss portion, and a height of the boss portion relative to the base circuit board is greater than a height of the first surrounding portion relative to the base circuit board, so that the boss portion is disposed in a protruding manner relative to the first surrounding portion, the boss portion is provided with at least one of the second chips, and the first surrounding portion is provided with at least one of the second chips.
In an optional embodiment, the protective adhesive coating layer further includes a second surrounding portion, the second surrounding portion is disposed around the first surrounding portion, and a height of the second surrounding portion relative to the base circuit board is smaller than a height of the first surrounding portion relative to the base circuit board, so that the second surrounding portion and the first surrounding portion form a stepped structure, and the second surrounding portion is also provided with at least one second chip.
In a second aspect, the present invention provides a chip stack packaging method for preparing the chip stack packaging structure according to the foregoing embodiments, including:
mounting a first chip on a substrate circuit board;
arranging a protective adhesive coating layer coated outside the first chip on the substrate circuit board;
hot-pressing and mounting a second chip on the protective adhesive-coated layer;
a circuit connecting layer which is coated outside the protective adhesive coating layer and the second chip is arranged on the substrate circuit board;
mounting a third chip on the circuit connecting layer;
arranging an encapsulating layer which is coated outside the circuit connecting layer and the third chip on the substrate circuit board;
the circuit comprises a circuit connecting layer, a first electric column, a second electric column, a third chip, a second chip, a circuit connecting layer and a base circuit board, wherein the circuit connecting layer is provided with the first electric column, two ends of the first electric column are respectively penetrated to two side surfaces of the circuit connecting layer, the third chip and the second chip are respectively connected with two ends of the first electric column, the third chip, the second chip and the circuit connecting layer are connected into a whole through the first electric column, and the circuit connecting layer is electrically connected with the base circuit board.
The beneficial effects of the embodiment of the invention include, for example:
according to the chip lamination packaging structure provided by the invention, the first chip is pasted on the substrate circuit board, the second chip is arranged on the protective adhesive coating layer coated outside the first chip, the third chip is arranged on the circuit connecting layer coated outside the protective adhesive coating layer, the first electric column is further arranged on the circuit connecting layer, the third chip, the second chip and the circuit connecting layer are electrically connected into a whole through the first electric column, and the circuit connecting layer is electrically connected with the substrate circuit board, so that the third chip, the second chip and the substrate circuit board are electrically connected. Compared with the prior art, the chip stacking structure has the advantages that the first chip is pasted, the second chip and the third chip are respectively arranged on the upper side and the lower side of the circuit connecting layer, the chips are stacked, the mutual interference among the chips is avoided through the stacking structure, routing is not needed, the packaging difficulty is reduced, the number of the storage chips is increased, and the product performance is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is an overall schematic view of a chip-on-package structure according to a first embodiment of the invention;
fig. 2 is a partial schematic view of a chip-on-package structure provided in a first embodiment of the invention under a first viewing angle;
fig. 3 is a partial schematic view of a chip stack package structure according to a first embodiment of the invention at a second viewing angle;
fig. 4 is an overall schematic view of a chip-on-package structure according to a second embodiment of the invention;
fig. 5 is a partial schematic view of a chip-on-package structure according to a second embodiment of the invention;
fig. 6 is a partial schematic view of a chip stack package structure according to a third embodiment of the invention;
fig. 7 is a partial schematic view of a chip-on-package structure according to a fourth embodiment of the invention;
fig. 8 is a block diagram illustrating steps of a chip-on-chip packaging method according to a fifth embodiment of the present invention;
fig. 9 to 14 are process flow diagrams of a chip stack packaging method according to a fifth embodiment of the invention.
Icon: 100-chip stack package structure; 110-base circuit board; 111-substrate pad; 120-a first chip; 130-protective adhesive coating layer; 131-a boss portion; 133-a first surround; 135-a second surrounding portion; 140-a second chip; 150-a line connection layer; 151-electrical wiring layer; 153-first dielectric layer; 155-a second dielectric layer; 157-a first electrical layer; 159 — a second electrical layer; 160-a third chip; 170-an encapsulation layer; 180-a first electrical pillar; 190-second electrical pillar.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
As disclosed in the background art, in the conventional packaging structure, a plurality of chips are often directly stacked together in a chip stacking process and then are subjected to plastic packaging, the structure is unstable and easy to collapse during packaging, and as the plurality of chips are required to be electrically connected with a substrate, no matter routing or conductive holes are used for realizing the electrical connection, process steps are increased undoubtedly, and the packaging difficulty is improved. And mutual interference is easily formed between the chips, the layout requirement on the chips is high, the structure is complex, and the breakthrough of the number of the chips is difficult to realize, so that the number of the stacked chips is limited, and the performance of the device is reduced.
In order to solve the above problems, the present invention provides a chip stack package structure and a chip stack package method, and it should be noted that, in a non-conflicting manner, features in the embodiments of the present invention may be combined with each other.
First embodiment
Referring to fig. 1 to fig. 3, the present embodiment provides a chip stacked package structure 100, which has a simple structure and low chip layout requirements, and avoids mutual interference between chips, thereby reducing the packaging difficulty, and simultaneously stacking more chips to improve the device performance.
The chip stack package structure 100 provided in this embodiment includes a substrate circuit board 110, a first chip 120, a protection adhesive layer 130, a second chip 140, a circuit connection layer 150, a third chip 160, and an encapsulation layer 170, wherein the first chip 120 is attached to the substrate circuit board 110, the protection adhesive layer 130 is disposed on the substrate circuit board 110 and covers the first chip 120, the second chip 140 is disposed on the protection adhesive layer 130, the circuit connection layer 150 is disposed on the substrate circuit board 110 and covers the circuit connection layer 150 outside the protection adhesive layer 130, the third chip 160 is disposed on the circuit connection layer 150, the encapsulation layer is disposed on the substrate circuit board 110 and covers the circuit connection layer 150 and the third chip 160, wherein the circuit connection layer 150 is disposed with a first electrical pillar 180, two ends of the first electrical pillar 180 respectively penetrate through two side surfaces of the circuit connection layer 150, the third chip 160 and the second chip 140 are respectively connected to two ends of the first electrical pillar 180, the third chip 160, the second chip 140 and the circuit connection layer 150 are electrically connected to each other through the first electrical pillar 180, and the circuit connection layer 150 is electrically connected to the base circuit board 110.
In this embodiment, the first chip 120, the second chip 140, and the third chip 160 may be the same type of chip, or may be different types of chips, for example, the first chip 120 is a control chip, and the second chip 140 and the third chip 160 are memory chips. Meanwhile, the first chip 120, the second chip 140, and the third chip 160 may have the same or different structural dimensions, and in the case of different dimensions, for example, when the first chip 120 has a larger dimension, the first chip 120 is directly attached to the base circuit board 110, and the second chip 140 and the third chip 160 are attached to the upper and lower sides of the circuit connection layer 150, so that the overall structure is more compact, and the stacking number of the second chip 140 and the third chip 160 is more favorably increased.
It should be noted that in this embodiment, the second chips 140 and the third chips 160 are multiple, the second chips 140 and the third chips 160 are correspondingly disposed one by one, and the first electrical pillar 180 is disposed between each second chip 140 and the corresponding third chip 160. The plurality of second chips 140 are disposed on the protective adhesive layer 130 and attached to the lower surface of the circuit connection layer 150, and the plurality of second chips 140 are disposed at different positions of the protective adhesive layer 130. The third chips 160 are attached to the upper surface of the circuit connection layer 150 and located at different positions of the circuit connection layer 150. Of course, the specific number of the second chips 140 and the third chips 160 is not limited herein, and the number of the second chips 140 and the third chips 160 can be set reasonably according to the size of the second chips 140 and the third chips 160 and the requirement of the package size.
In the present embodiment, the substrate pad 111 is disposed on the substrate circuit board 110, the substrate pad 111 surrounds the first chip 120, and the circuit connection layer 150 is connected to the substrate pad 111 and electrically connected to the substrate circuit board 110 through the substrate pad 111. Specifically, the plurality of substrate pads 111 are disposed around the substrate pad 111 and define a mounting area on the substrate circuit board 110, the first chip 120 is mounted in a middle portion of the mounting area, so that the plurality of substrate pads 111 are disposed around the first chip 120, and when the wire connection layer 150 is formed, the wire connection layer 150 is in electrical contact with at least one substrate pad 111, thereby achieving electrical connection between the wire connection layer 150 and the substrate circuit board 110.
In the embodiment, the protective adhesive layer 130 covers the first chip 120, the adhesive layer can be covered on the surface of the first chip 120 by a vacuum coating machine, and the edge of the protective adhesive layer 130 is limited to the mounting area defined by the substrate pad 111. For the edge limitation of the protective adhesive coating layer 130, the substrate pad 111 may be set to a certain height, and the adhesive blocking of the substrate pad 111 is used, or the substrate pad 111 may be directly set to be an annular protruding structure, so as to directly block the adhesive layer inside. Specifically, the protective coating layer 130 is a thermoplastic colloid, such as a high molecular material of polyethylene, polypropylene, polyvinyl chloride polymer, etc., which may deform when heated, so as to facilitate the subsequent mounting of the second chip 140 through a hot pressing process.
It should be noted that, in this embodiment, the first chip 120 is a flip chip, the mounting area of the substrate circuit board 110 is provided with an electrical connection pad, the bottom of the first chip 120 is provided with a connection bump, and the connection bump and the electrical connection pad are soldered together, so that the flip electrical connection of the first chip 120 is realized. The specific mounting structure of the first chip 120 may refer to an existing flip chip. Of course, the first chip 120 may also be a normal chip, that is, the first chip 120 is electrically connected to the base circuit board 110 by wire bonding, and the protective adhesive layer 130 is required to cover the wire bonding.
In the embodiment, the second chip 140 is embedded on the protective adhesive layer 130, and the surface of the second chip 140 is flush with the surface of the protective adhesive layer 130. Specifically, after the protection glue-coating layer 130 is formed, since the protection glue-coating layer 130 adopts the thermoplastic glue, the second chip 140 needs to be mounted by a hot-press welding process, a welding head and a rail on a hot-press chip mounter are used for heating the substrate, so that the protection glue-coating layer 130 is softened after being heated, then the second chip 140 is mounted on the upper side surface of the thermoplastic glue layer, the second chip 140 is flush with the surface of the thermal plastic layer, and the second chip 140 is coated by the thermoplastic glue after being cooled and leaks out of the surface of the second chip 140.
In the present embodiment, the circuit connection layer 150 is shaped to fit the protection adhesive coating layer 130, the protection adhesive coating layer 130 includes a boss portion 131 and a first surrounding portion 133, the first surrounding portion 133 is disposed around the boss portion 131, and the height of the boss portion 131 relative to the base circuit board 110 is greater than the height of the first surrounding portion 133 relative to the base circuit board 110, so that the boss portion 131 is disposed in a protruding manner relative to the first surrounding portion 133, at least one second chip 140 is disposed on the boss portion 131, and at least one second chip 140 is disposed on the first surrounding portion 133. Specifically, since the first chip 120 is mounted, when the protective coating 130 is formed, the protective coating 130 at the middle position protrudes upward to cover the first chip 120, and the wire connection layer 150 also protrudes upward at the middle position to form the boss portion 131, the first surrounding portion 133 is formed at the peripheral portion, the first surrounding portion 133 and the boss portion 131 are integrally formed, the upper and lower surfaces of the boss portion 131 may be provided with the plurality of second chips 140 and the third chips 160, and the surface of the first surrounding portion 133 may also be provided with the plurality of second chips 140 and the third chips 160.
It should be noted that the circuit connection layer 150 can be prepared by one of a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, sputtering, electroplating or electroless plating.
In this embodiment, the circuit connection layer 150 includes an electrical wiring layer 151 and a first dielectric layer 153, the electrical wiring layer 151 covers the protective adhesive layer 130, the first dielectric layer 153 covers the electrical wiring layer 151, the third chip 160 is disposed on the first dielectric layer 153, the second chip 140 is electrically connected to the electrical wiring layer 151, the third chip 160 is electrically connected to the second chip 140 through the first electrical pillar 180, and the electrical wiring layer 151 is electrically connected to the base circuit board 110.
Specifically, after the protective cover adhesive layer 130 is formed and the second chip 140 is disposed on the protective cover adhesive layer 130, the electrical wiring layer 151 covering the second chip 140 and the protective cover adhesive layer 130 may be formed by means of adhesive coating and wiring, and then the first dielectric layer 153 is formed on the surface of the electrical wiring layer 151, where the first dielectric layer 153 is made of a dielectric material, such as an amine cured epoxy material, an epoxy polymer, polyimide, and the like, and by disposing the first dielectric layer 153, the protection of the electrical wiring layer 151 may be effectively achieved, thereby avoiding the problems of moisture/humidity or foreign substance contamination/ESD, and improving the reliability of the product.
It should be noted that, in the embodiment, the first electrical pillar 180 penetrates through the first dielectric layer 153 and the electrical wiring layer 151 at the same time, in this embodiment, the second chip 140 may be electrically connected to the electrical wiring layer 151 through a pad, and electrically connected to the third chip 160 through the first electrical pillar 180. In forming the first electrical pillar 180, after the first dielectric layer 153 is formed, a laser may be used to form a hole in the first dielectric layer 153 and the electrical wiring layer 151, and then a metal is sputtered to form the first electrical pillar 180. Of course, the first electrical pillar 180 may also be formed by filling a conductive adhesive after grooving and curing, and the specific forming method of the first electrical pillar 180 is not limited herein.
In other preferred embodiments of the present invention, the line connection layer 150 may also only include the electrical wiring layer 151, the third chip 160 and the second chip 140 are respectively disposed on the upper and lower sides of the electrical wiring layer 151, and at least one of the third chip 160 and the second chip 140 is directly electrically connected to the electrical wiring layer 151 through a pad. The specific configuration thereof will not be described herein.
In summary, the present embodiment provides a chip stacked package structure 100, in which a first chip 120 is mounted on a substrate circuit board 110, a second chip 140 is disposed on a protective adhesive layer 130 covering the first chip 120, a third chip 160 is disposed on a circuit connecting layer 150 covering the protective adhesive layer 130, a first electrical pillar 180 is further disposed on the circuit connecting layer 150, the third chip 160, the second chip 140 and the circuit connecting layer 150 are electrically connected to each other through the first electrical pillar 180, the circuit connecting layer 150 is electrically connected to the substrate circuit board 110, so as to achieve electrical connection between the third chip 160, the second chip 140 and the substrate circuit board 110, and complete stacking of the first chip 120, the second chip 140 and the third chip 160, the stacked structure avoids mutual interference among chips, does not need wire bonding, and reduces the difficulty of packaging, and the number of the memory chips is increased, and the product performance is improved.
Second embodiment
Referring to fig. 4 and 5, the chip stack package structure 100 provided in the present embodiment has the same basic structure and principle and the same technical effect as the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents in the first embodiment for parts not mentioned in the present embodiment. The present embodiment is different from the first embodiment in the line connection layer 150.
In this embodiment, the circuit connection layer 150 includes an electrical wiring layer 151, a first dielectric layer 153 and a second dielectric layer 155, the second dielectric layer 155 covers the protective adhesive layer 130, the electrical wiring layer 151 covers the second dielectric layer 155, the first dielectric layer 153 covers the electrical wiring layer 151, the third chip 160 is disposed on the first dielectric layer 153, the third chip 160 is electrically connected to the second chip 140 through the first electrical pillar 180, the electrical wiring layer 151 is electrically connected to the base circuit board 110, and the second chip 140 is attached to the second dielectric layer 155.
In this embodiment, the upper and lower sides of the electrical wiring layer 151 are respectively covered with the first dielectric layer 153 and the second dielectric layer 155, and the electrical wiring layer 151 can be better protected by the two dielectric layers.
In this embodiment, the first dielectric layer 153 is further provided with a second electrical pillar 190, the second electrical pillar 190 penetrates through the first dielectric layer 153 and is connected to the electrical wiring layer 151, and the third chip 160 is connected to the second electrical pillar 190 and is electrically connected to the electrical wiring layer 151 through the second electrical pillar 190. Specifically, the second electrical pillar 190 may also be formed by laser drilling and sputtering metal, and the second electrical pillar 190 and the first electrical pillar 180 may be formed together.
In this embodiment, the second electrical pillar 190 can electrically connect the third chip 160 and the electrical wiring layer 151 into a whole, and then the first electrical pillar 180 electrically connects the second chip 140 and the third chip 160 into a whole, so as to ensure the electrical connection effect and avoid the occurrence of poor conductive contact.
In the chip stack package structure 100 provided in this embodiment, the first dielectric layer 153 and the second dielectric layer 155 are disposed on the upper side and the lower side of the electrical wiring layer 151, so that the electrical wiring layer 151 can be better protected, and the reliability of the device is further improved.
Third embodiment
Referring to fig. 6, the present embodiment provides a chip on package structure 100, the basic structure and principle and the generated technical effect are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents in the first embodiment for the parts not mentioned in the present embodiment. The present embodiment is different from the first embodiment in the line connection layer 150.
In this embodiment, the circuit connection layer 150 includes an electrical wiring layer 151, a first dielectric layer 153 and a second dielectric layer 155, the second dielectric layer 155 covers the protective adhesive layer 130, the electrical wiring layer 151 covers the second dielectric layer 155, the first dielectric layer 153 covers the electrical wiring layer 151, the third chip 160 is disposed on the first dielectric layer 153, the third chip 160 is electrically connected to the second chip 140 through the first electrical pillar 180, the electrical wiring layer 151 is electrically connected to the base circuit board 110, and the second chip 140 is attached to the second dielectric layer 155.
In this embodiment, the second chips 140 and the third chips 160 are multiple, the second chips 140 and the third chips 160 are disposed in a one-to-one correspondence manner, a first electrical pillar 180 is disposed between each second chip 140 and the corresponding third chip 160, the electrical wiring layer 151 includes a first electrical layer 157 and a second electrical layer 159, the first electrical layer 157 and the second electrical layer 159 are disposed in a staggered manner, at least one first electrical pillar 180 is disposed on the first electrical layer 157, and at least one first electrical pillar 180 is disposed on the second electrical layer 159.
In the embodiment, the first electrical layer 157 and the second electrical layer 159 are disposed in a staggered manner, and the first electrical layer 157 is disposed with at least one first electrical pillar 180 and directly electrically connected with at least one second chip 140 and at least one third chip 160 as a whole, and the second electrical layer 159 is disposed with at least one first electrical pillar 180 and directly electrically connected with at least one second chip 140 and at least one third chip 160 as a whole. By adopting the staggered layer design and connecting different chips by using different electric layers, the wiring length can be greatly reduced, and the chip transmission efficiency is improved. Meanwhile, the bonding line widths of different electrical layers can be designed according to the types of the second chip 140 and the third chip 160 to be mounted, for example, the bonding line width of the first electrical layer 157 is designed to be 35 μm, so that the sizes of the corresponding pads on the second chip 140 and the third chip 160 are designed to be 55 μm, the bonding line width of the second electrical layer 159 is designed to be 55 μm, and the sizes of the corresponding pads on the second chip 140 and the third chip 160 are designed to be 75 μm, thereby realizing that the second chip 140/the third chip 160 of different types are respectively mounted on the first electrical layer 157 and the second electrical layer 159, and improving the mounting adaptability.
Of course, the electrical wiring layer 151 may also be a multi-layer electrical layer structure, and the multi-layer electrical layers are designed in a staggered manner, which is suitable for more chip types and greatly reduces the wiring length.
Fourth embodiment
Referring to fig. 7, the present embodiment provides a chip on package structure 100, the basic structure and principle thereof and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment without reference to the parts of the present embodiment.
In the present embodiment, the protective coating layer 130 includes a boss portion 131, a first surrounding portion 133 and a second surrounding portion 135, the first surrounding portion 133 is disposed around the boss portion 131, and a height of the boss portion 131 relative to the base circuit board 110 is greater than a height of the first surrounding portion 133 relative to the base circuit board 110, so that the boss portion 131 is disposed in a protruding manner relative to the first surrounding portion 133, at least one second chip 140 is disposed on the boss portion 131, and at least one second chip 140 is disposed on the first surrounding portion 133. The second surrounding portion 135 surrounds the first surrounding portion 133, and a height of the second surrounding portion 135 relative to the base circuit board 110 is smaller than a height of the first surrounding portion 133 relative to the base circuit board 110, so that the second surrounding portion 135 and the first surrounding portion 133 form a stepped structure, and the second surrounding portion 135 is also provided with at least one second chip 140.
In the present embodiment, the boss portion 131, the first surrounding portion 133 and the second surrounding portion 135 form a stepped boss structure, so that a plurality of second chips 140 can be respectively arranged on different step surfaces, further increasing the number of stacked chips. The stepped structure in this embodiment has three layers, i.e., the boss portion 131, the first surrounding portion 133 and the second surrounding portion 135 form three layers of stepped surfaces, respectively. Of course, the number of the step-shaped structure may be four, five or six, and the number of the step-shaped layers of the protective cover adhesive layer 130 is not limited herein.
Fifth embodiment
Referring to fig. 8, the present embodiment provides a chip on package method for preparing the chip on package structure 100 according to the first, second, third or fourth embodiment, the method includes the following steps:
s1: the first chip 120 is mounted on the base circuit board 110.
Referring to fig. 9 in combination, specifically, a base circuit board 110 is provided, a base pad 111 and an electrical connection pad are designed on the base circuit board 110, the base pad 111 is disposed around and defines a mounting area, and the electrical connection pad is located in the mounting area. The first chip 120 is mounted in the mounting region, where the first chip 120 is a flip chip, and the connection bumps on the first chip 120 are soldered to the electrical connection pads, so that the first chip 120 is connected to the base circuit board 110.
S2: a protective adhesive layer 130 is disposed on the substrate circuit board 110 and covers the first chip 120.
Referring to fig. 10, specifically, the adhesive layer is coated on the surface of the first chip 120 by a vacuum coating machine, and after curing, the protective adhesive layer 130 is formed, and the edge of the protective adhesive layer 130 is limited to the mounting area defined by the substrate pad 111. For the edge limitation of the protective adhesive coating layer 130, the substrate pad 111 may be set to a certain height, and the adhesive blocking of the substrate pad 111 is used, or the substrate pad 111 may be directly set to be an annular protruding structure, so as to directly block the adhesive layer inside.
In the embodiment, the protective coating layer 130 is a thermoplastic adhesive, such as a high molecular material of polyethylene, polypropylene, polyvinyl chloride polymer, etc., which is deformed by heating, thereby facilitating the subsequent process.
S3: the second chip 140 is mounted on the protective adhesive layer 130 by hot pressing.
Referring to fig. 11 in detail, after the protective adhesive coating layer 130 is formed, since the protective adhesive coating layer 130 uses a thermoplastic adhesive, the second chip 140 can be attached by a thermocompression bonding process, and the bonding head and the track on the thermocompression bonding machine are used to heat the substrate, so that the protective adhesive coating layer 130 is heated and softened, and then the second chip 140 is attached to the upper surface of the thermoplastic adhesive, and the second chip 140 is flush with the surface of the thermoplastic adhesive, and after cooling, the second chip 140 is covered by the thermoplastic adhesive and leaks out of the surface of the second chip 140.
S4: a circuit connection layer 150 is disposed on the substrate circuit board 110 and covers the protective adhesive layer 130 and the second chip 140.
Referring to fig. 12, specifically, after the hot pressing mounting of the second chip 140 is completed, the predetermined RDL electrical layer is masked by a mask without exposure, then the unexposed area is removed by spraying a developing solution through a developing process, the RDL electrical wiring layer 151 is leaked out, a groove is formed, and then the RDL wiring is completed at the groove by using an exposure and development technology again. Wherein the heat conduction holes can be formed together in the exposure and development process. Meanwhile, the RDL electrical wiring layer 151 may be prepared by one of a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, sputtering, electroplating, or electroless plating.
It should be noted that, when the chip stack package structure 100 provided in the first embodiment is formed, after the electrical wiring layer 151 is formed, a dielectric material is coated on the surface of the electrical wiring layer again to form the first dielectric layer 153, so as to implement protection.
In forming the chip stack package structure 100 according to the second embodiment, before the electrical wiring layer 151 is formed, a dielectric material needs to be coated on the protective adhesive layer 130 to form the second dielectric layer 155 for protection.
In forming the chip stack package structure 100 according to the third embodiment, the electrical wiring layers 151 need to be separately disposed, and different electrical layers need to be disposed.
After the circuit connection layer 150 is formed, it is necessary to open a groove on the circuit connection layer 150 through a laser opening process and then sputter metal to form the first electrical pillar 180.
S5: the third chip 160 is mounted on the wire connection layer 150.
Referring to fig. 13, specifically, the third chip 160 is mounted on the circuit connection layer 150, and the third chip 160 is connected to the first electrical pillar 180, so that the second chip 140, the third chip 160 and the circuit connection layer 150 are electrically connected to form a whole.
S6: an encapsulation layer 170 is disposed on the base circuit board 110 and covers the circuit connection layer 150 and the third chip 160.
Referring to fig. 14, specifically, the connected structures are protected by a plastic package material through a plastic package process to form an encapsulating layer 170, and after the solder balls are implanted on the back surface of the substrate through a ball implanting process, the product is cut and surrounded by a single piece through a cutting process to complete the manufacturing process.
In this embodiment, the circuit connection layer 150 is provided with a first electrical pillar 180, two ends of the first electrical pillar 180 respectively penetrate through two side surfaces of the circuit connection layer 150, the third chip 160 and the second chip 140 are respectively connected with two ends of the first electrical pillar 180, the third chip 160, the second chip 140 and the circuit connection layer 150 are electrically connected into a whole through the first electrical pillar 180, and the circuit connection layer 150 is electrically connected with the base circuit board 110.
In summary, the present embodiment provides a chip stacking and packaging method, which includes mounting a first chip 120 on a substrate circuit board 110, disposing a second chip 140 on a protective adhesive layer 130 covering the first chip 120, disposing a third chip 160 on a circuit connection layer 150 covering the protective adhesive layer 130, and further disposing a first electrical pillar 180 on the circuit connection layer 150, wherein the third chip 160, the second chip 140 and the circuit connection layer 150 are electrically connected to each other through the first electrical pillar 180, and the circuit connection layer 150 is electrically connected to the substrate circuit board 110, so as to achieve electrical connection between the third chip 160, the second chip 140 and the substrate circuit board 110, and simultaneously complete stacking of the first chip 120, the second chip 140 and the third chip 160, and the stacking structure avoids mutual interference among chips, does not need wire bonding, and reduces packaging difficulty, and the number of the memory chips is increased, and the product performance is improved.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A chip stack package structure, comprising:
a base circuit board;
a first chip mounted on the base circuit board;
the protective adhesive coating layer is arranged on the substrate circuit board and covers the first chip;
the second chip is arranged on the protective adhesive-coated layer;
the circuit connecting layer is arranged on the substrate circuit board and is coated outside the protective coating layer;
a third chip disposed on the line connection layer;
the encapsulating layer is arranged on the substrate circuit board and wraps the circuit connecting layer and the third chip;
the circuit comprises a circuit connecting layer, a first electric column, a second electric column, a third chip, a second chip, a circuit connecting layer and a base circuit board, wherein the circuit connecting layer is provided with the first electric column, two ends of the first electric column are respectively penetrated to two side surfaces of the circuit connecting layer, the third chip and the second chip are respectively connected with two ends of the first electric column, the third chip, the second chip and the circuit connecting layer are connected into a whole through the first electric column, and the circuit connecting layer is electrically connected with the base circuit board.
2. The chip stack package structure according to claim 1, wherein the circuit connection layer includes an electrical wiring layer and a first dielectric layer, the electrical wiring layer is coated outside the protective adhesive layer, the first dielectric layer is coated outside the electrical wiring layer, the third chip is disposed on the first dielectric layer, the second chip is electrically connected to the electrical wiring layer, the third chip is electrically connected to the second chip through the first electrical pillar, and the electrical wiring layer is electrically connected to the base circuit board.
3. The chip stack package structure according to claim 2, wherein the circuit connection layer further comprises a second dielectric layer, the second dielectric layer covers the protective adhesive layer, the electrical wiring layer covers the second dielectric layer, and the second chip is attached to the second dielectric layer.
4. The chip stack package structure according to claim 2 or 3, wherein a second electrical pillar is further disposed on the first dielectric layer, the second electrical pillar penetrates through the first dielectric layer and is connected to the electrical wiring layer, and the third chip is connected to the second electrical pillar and is electrically connected to the electrical wiring layer through the second electrical pillar.
5. The chip stacked package structure according to claim 2 or 3, wherein the second chip and the third chip are both plural, the plural second chips and the plural third chips are disposed in a one-to-one correspondence, the first electrical pillar is disposed between each second chip and the corresponding third chip, the electrical wiring layer includes a first electrical layer and a second electrical layer, the first electrical layer and the second electrical layer are disposed in a staggered manner, the first electrical layer is disposed with at least one of the first electrical pillars, and the second electrical layer is disposed with at least one of the first electrical pillars.
6. The chip stack package structure according to claim 1, wherein a substrate pad is disposed on the substrate circuit board, the substrate pad is disposed around the first chip, and the circuit connecting layer is connected to the substrate pad and electrically connected to the substrate circuit board through the substrate pad.
7. The chip stack package structure according to claim 1, wherein the second chip is embedded on the protection adhesive layer, and a surface of the second chip is flush with a surface of the protection adhesive layer.
8. The chip stack package structure according to claim 1 or 7, wherein the trace connection layer has a shape adapted to the protective adhesive coating layer, the protective adhesive coating layer includes a boss portion and a first surrounding portion, the first surrounding portion is disposed around the boss portion, and a height of the boss portion relative to the base circuit board is greater than a height of the first surrounding portion relative to the base circuit board, so that the boss portion is disposed in a protruding manner relative to the first surrounding portion, the boss portion is disposed with at least one of the second chips, and the first surrounding portion is disposed with at least one of the second chips.
9. The chip stack package structure according to claim 8, wherein the protective adhesive coating layer further includes a second surrounding portion, the second surrounding portion is disposed around the first surrounding portion, and a height of the second surrounding portion relative to the base circuit board is smaller than a height of the first surrounding portion relative to the base circuit board, so that the second surrounding portion and the first surrounding portion form a step-shaped structure, and the second surrounding portion is also disposed with at least one of the second chips.
10. A chip stack packaging method for preparing the chip stack packaging structure according to claim 1, comprising:
mounting a first chip on a substrate circuit board;
arranging a protective adhesive coating layer coated outside the first chip on the substrate circuit board;
hot-pressing and mounting a second chip on the protective adhesive-coated layer;
a circuit connecting layer which is coated outside the protective adhesive coating layer and the second chip is arranged on the substrate circuit board;
mounting a third chip on the circuit connecting layer;
arranging an encapsulating layer which is coated outside the circuit connecting layer and the third chip on the substrate circuit board;
the circuit comprises a circuit connecting layer, a first electric column, a second electric column, a third chip, a second chip, a circuit connecting layer and a base circuit board, wherein the circuit connecting layer is provided with the first electric column, two ends of the first electric column are respectively penetrated to two side surfaces of the circuit connecting layer, the third chip and the second chip are respectively connected with two ends of the first electric column, the third chip, the second chip and the circuit connecting layer are connected into a whole through the first electric column, and the circuit connecting layer is electrically connected with the base circuit board.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050212114A1 (en) * | 2004-03-29 | 2005-09-29 | Nec Electronics Corporation | Semiconductor device |
| US20170170154A1 (en) * | 2015-12-10 | 2017-06-15 | Seung-Kwan Ryu | Semiconductor package and method of fabricating the same |
| CN106898625A (en) * | 2015-12-18 | 2017-06-27 | 中芯国际集成电路制造(上海)有限公司 | The encapsulating structure and method for packing of image sensor chip |
| CN107958882A (en) * | 2017-12-20 | 2018-04-24 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure of chip and preparation method thereof |
| CN108389850A (en) * | 2018-05-04 | 2018-08-10 | 袁鹰 | Three-dimensional system level packaging structure and its packaging method |
| CN111584478A (en) * | 2020-05-22 | 2020-08-25 | 甬矽电子(宁波)股份有限公司 | Laminated chip packaging structure and laminated chip packaging method |
| CN111816625A (en) * | 2020-08-25 | 2020-10-23 | 甬矽电子(宁波)股份有限公司 | Multilayer chip stacking structure and multilayer chip stacking method |
| CN112768364A (en) * | 2021-01-29 | 2021-05-07 | 广东佛智芯微电子技术研究有限公司 | Board-level three-dimensional chip packaging structure and preparation method thereof |
-
2021
- 2021-07-20 CN CN202110819499.9A patent/CN113540069B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050212114A1 (en) * | 2004-03-29 | 2005-09-29 | Nec Electronics Corporation | Semiconductor device |
| US20170170154A1 (en) * | 2015-12-10 | 2017-06-15 | Seung-Kwan Ryu | Semiconductor package and method of fabricating the same |
| CN106898625A (en) * | 2015-12-18 | 2017-06-27 | 中芯国际集成电路制造(上海)有限公司 | The encapsulating structure and method for packing of image sensor chip |
| CN107958882A (en) * | 2017-12-20 | 2018-04-24 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure of chip and preparation method thereof |
| CN108389850A (en) * | 2018-05-04 | 2018-08-10 | 袁鹰 | Three-dimensional system level packaging structure and its packaging method |
| CN111584478A (en) * | 2020-05-22 | 2020-08-25 | 甬矽电子(宁波)股份有限公司 | Laminated chip packaging structure and laminated chip packaging method |
| CN111816625A (en) * | 2020-08-25 | 2020-10-23 | 甬矽电子(宁波)股份有限公司 | Multilayer chip stacking structure and multilayer chip stacking method |
| CN112768364A (en) * | 2021-01-29 | 2021-05-07 | 广东佛智芯微电子技术研究有限公司 | Board-level three-dimensional chip packaging structure and preparation method thereof |
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