CN106898625B - Packaging structure and packaging method of image sensor chip - Google Patents
Packaging structure and packaging method of image sensor chip Download PDFInfo
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- CN106898625B CN106898625B CN201510960949.0A CN201510960949A CN106898625B CN 106898625 B CN106898625 B CN 106898625B CN 201510960949 A CN201510960949 A CN 201510960949A CN 106898625 B CN106898625 B CN 106898625B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
Abstract
The invention provides a packaging structure and a packaging method of an image sensor chip.A substrate groove etching process on the back of the chip is adopted to avoid using a silicon perforation process, and meanwhile, the peripheral edge of a bonding pad exposed at the bottom of a groove is modified into a step-shaped structure, so that the filling difficulty of a wiring metal layer is reduced, the contact area between the subsequently filled wiring metal layer and the bonding pad is increased, and the connection reliability of the wiring metal layer is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a packaging structure and a packaging method of an image sensor chip.
Background
A CMOS Image Sensor (CIS) is an important component of a digital camera, and its imaging principle is to sense light by a photosensor, convert an optical signal into an electrical signal, and output an Image.
Currently, the mainstream CIS chip packaging technology includes: CSP (chip Scale Package), COB (chip OnBoard) and FC (Flip chip). The CSP refers to a chip packaging technology in which a chip size package and a chip core size are substantially the same, and is currently and generally applied to Wafer level (Wafer level) packaging of low-end and low-pixel (2M pixel or less) image sensors. The CSP Technology generally includes using the front Surface of an image sensor chip as a light-sensing window, bonding a wafer-level glass (a light-transmitting cover plate on the front Surface of the chip) to a wafer, and separating the image sensor chips on the wafer by using a fence, then contacting the image sensor chips on the wafer in a pad area of the ground wafer by making Through Silicon Vias (TSVs) connected to the Surface of the pad (or connected to a ring metal on the side of a Via in the pad area) or making a Ball Grid Array (BGA) after extending a circuit on the back Surface of the wafer, so as to redistribute the pads on the front Surface of the chip to the back Surface of the chip in a certain manner to achieve interconnection with the outside, and finally cutting the wafer to form an image sensor unit with a single sealed cavity, and using a Surface Mount Technology (Surface Mount Technology), SMT) form a module assembly structure. The ratio of the CSP core area to the package area is about 1:1.1, and any package meeting this standard may be referred to as a CSP. The packaging form greatly improves the integration level on a Printed Circuit Board (PCB), reduces the volume and the weight of an electronic device and improves the performance of a product.
The through-silicon-via technology generally includes forming a through-silicon-via on a silicon body on a back surface of a chip by a dry etching method, then performing an insulation process on exposed chip substrate silicon and silicon in the through-silicon-via, forming an interconnection window at a bottom of the through-silicon-via for a subsequent metal filling to form a contact with a pad, then filling metal in the through-silicon-via, and redistributing a metal circuit layer. However, the wafer-level image sensor packaging method introduces through silicon via interconnection, so that the packaging structure is complex; in addition, the through silicon via interconnection technology is not mature, and the problems of failure or poor reliability caused by the problems of poor insulation in holes, incomplete interconnection windows, unreal metal filling and the like are caused, so that the problems of high process difficulty and low interconnection reliability exist in the wafer-level image sensor packaging by utilizing the through silicon via interconnection. Meanwhile, the complexity of the through silicon via interconnection process also causes the wafer level image sensor package adopting the technology to be expensive.
Disclosure of Invention
The invention aims to provide a packaging structure and a packaging method of an image sensor chip, which can simplify the packaging structure and reduce the process difficulty and the process cost.
In order to solve the above problems, the present invention provides a method for packaging an image sensor chip, comprising the following steps:
providing a packaging substrate and an image sensor chip, wherein the packaging substrate is provided with a light transmission area, the image sensor chip is formed on the front surface of a semiconductor substrate, a plurality of bonding pads are formed on the front surface of the semiconductor substrate around the image sensor chip, and each bonding pad is a metal structure formed by interconnection of a plurality of metal layers;
bonding the packaging substrate and the front surface of the semiconductor substrate, wherein the light-transmitting area corresponds to the light-sensing area of the image sensor chip;
etching the back surface of the semiconductor substrate to form a groove, wherein the groove exposes the bottommost metal layer of the bonding pad;
etching the bonding pad to enable the multilayer metal layer of the bonding pad to form a step-shaped structure, and forming an insulating layer on the back of the semiconductor substrate, wherein the insulating layer exposes each step surface of the step-shaped structure;
forming wiring metal layers on the surfaces of the insulating layer and the stepped structure, wherein the wiring metal layers are in contact with each metal layer of the stepped structure;
forming a protective layer on the surface of the wiring metal layer, and etching the protective layer to form a plurality of openings exposing the wiring metal layer; and
bumps are provided in the openings.
Further, the step of providing the image sensor chip includes:
providing the semiconductor substrate;
forming at least one image sensing unit on the front surface of the semiconductor substrate, wherein the area where the image sensing unit is located is the photosensitive area;
a plurality of pads are formed around each image sensing unit.
Further, the image sensing unit and each pad are partially formed in a passivation layer on the front surface of the semiconductor substrate.
Further, the packaging substrate and the front surface of the semiconductor substrate are bonded in a glue dispensing, glue drawing, glue printing, glue rolling or photoetching process patterned glue mode.
Further, after the groove is formed, the metal layers of the bonding pad at the groove are etched in different degrees to form a step-shaped structure, and then an insulating layer is formed on the back surface of the semiconductor substrate.
Further, after the groove is formed, an insulating layer is formed on the back surface of the semiconductor substrate, and then the metal layers of the bonding pad at the groove are etched in different degrees to form a stepped structure.
Furthermore, when the step-shaped structure is formed, the etching degree from the bottommost metal layer to the topmost metal layer of the pad is sequentially and uniformly reduced, so that the extending lengths of the bottommost metal layer to the topmost metal layer on the side wall of the groove are sequentially and uniformly lengthened.
Further, when the metal layers of the bonding pad at the groove are etched to form a step-shaped structure, at least the topmost metal layer of the metal layers of the bonding pad is not etched.
Further, the insulating layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and an organic polymer.
Further, the bumps are formed at the opening positions by a reflow soldering method, a ball implanting method, an evaporation method, an electroless plating method, an electroplating method, a ball placing method, a paste stencil printing method, or a printing paste method.
Further, the material of the bump comprises one or more of aluminum, tin, silver, lead, copper, zinc, bismuth, indium, gold and antimony.
The present invention also provides a package structure of an image sensor chip, including:
a semiconductor substrate;
an image sensor chip formed on a front surface of the semiconductor substrate;
the groove is formed on the back surface of the semiconductor substrate;
the bonding pads are distributed in the semiconductor substrate around the image sensor chip, and the bonding pads at the grooves are of a stepped structure formed by interconnection of multiple metal layers;
the insulating layer covers the back surface of the semiconductor substrate and exposes each step surface of the step-shaped structure;
a wiring metal layer covering the insulating layer and the exposed step surfaces of the stepped structure and contacting the metal layer of each step of the stepped structure;
a protective layer covering the surface of the wiring metal layer and having a plurality of openings exposing the wiring metal layer; and
and the salient point is arranged in the opening and is in conductive contact with the wiring metal layer.
Further, the image sensor chip is located on a wafer, and the wafer comprises a semiconductor substrate and at least one image sensor chip formed on the front surface of the semiconductor substrate.
Furthermore, the front surface of the wafer is covered with a passivation layer, and the image sensing unit of the image sensor chip and each bonding pad distributed around the image sensing unit are partially formed in the passivation layer.
Furthermore, in the stepped structure, the extending lengths of the bottommost metal layer to the topmost metal layer on the side wall of the trench are sequentially and uniformly lengthened.
Further, the material of the bump comprises one or more of aluminum, tin, silver, lead, copper, zinc, bismuth, indium, gold and antimony.
Compared with the prior art, the packaging structure and the method of the image sensor chip provided by the invention have the following beneficial effects:
(1) firstly, forming a groove at the position of a semiconductor substrate at the bottom of a bonding pad around a chip, wherein the bottom of the groove is exposed out of the back surface of the bonding pad; then trimming each metal layer of each bonding pad, and modifying the edge of each bonding pad into a step-shaped structure; finally, forming a wiring metal layer which is in conductive contact with the stepped structure in the groove, so that the chip electrical signal is transferred from the front surface of the chip to the back surface of the chip; compared with through silicon via interconnection, the structure is relatively simple;
(2) the size of the bottom of the groove formed by the method is larger, so that the process difficulty of filling the wiring metal layer in the subsequent groove is reduced, and the problem of poor reliability caused by incomplete metal filling in the through silicon via is avoided;
(3) because the stepped structure of the invention increases the contact area of the wiring metal layer and the bonding pad, the adverse effect that the filled wiring metal layer only contacts with the surface of the topmost metal layer or the bottommost metal layer of the bonding pad in the prior art is avoided, and the problem of poor connection reliability of the wiring metal layer and the bonding pad in the through silicon via is avoided;
(4) the invention avoids the use of through silicon via interconnection technology, thereby simplifying the packaging structure and process and reducing the packaging cost.
Drawings
FIG. 1 is a flow chart of a method for packaging an image sensor chip according to an embodiment of the present invention;
fig. 2A to 2F are schematic cross-sectional views of the device in the packaging method shown in fig. 1.
Detailed Description
The core idea of the invention is to provide a low-cost image sensor inverted packaging process without through silicon vias, wherein a substrate groove etching process on the back of a chip is adopted to avoid using a Through Silicon Via (TSV) process, and meanwhile, the peripheral edge of a bonding pad exposed at the bottom of a groove is modified into a step-shaped structure, so that the filling difficulty of a wiring metal layer is reduced, the contact area between the subsequently filled wiring metal layer and the bonding pad is increased, and the connection reliability of the wiring metal layer is improved.
The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.
The invention provides a packaging method of an image sensor chip, which comprises the following steps:
s1, providing a packaging substrate and an image sensor chip, wherein the packaging substrate is provided with a light-transmitting area, the image sensor chip is formed on the front surface of a semiconductor substrate, a plurality of bonding pads are formed on the front surface of the semiconductor substrate around the image sensor chip, and each bonding pad is a metal structure formed by interconnection of a plurality of metal layers;
s2, bonding the packaging substrate and the front surface of the semiconductor substrate, wherein the light-transmitting area corresponds to the light-sensing area of the image sensor chip;
s3, etching the back surface of the semiconductor substrate to form a groove, wherein the groove exposes the bottommost metal layer of the pad;
s4, etching the pad to enable the multiple metal layers of the pad to form a step-shaped structure, and forming an insulating layer on the back of the semiconductor substrate, wherein the insulating layer exposes each step surface of the step-shaped structure;
s5, forming wiring metal layers on the insulating layer and the surfaces of the stepped structures, wherein the wiring metal layers are in contact with each metal layer of the stepped structures;
s6, forming a protective layer on the surface of the wiring metal layer, and etching the protective layer to form a plurality of openings exposing the wiring metal layer; and
and S7, arranging a bump in the opening.
Referring to fig. 2A, the starting point of the packaging method of the present embodiment is an image sensor wafer, which includes a semiconductor substrate 10, an image sensor semiconductor substrate 10 located on the front surface of the semiconductor substrate 10, a pad 14 around the semiconductor substrate 10, and an inner passivation layer 13 where the image sensor semiconductor substrate 10 and the pad 14 are located, so that in step S1, when providing the image sensor chip, the following processes can be completed in advance: firstly, providing the semiconductor substrate 10, wherein the semiconductor substrate can be a bulk silicon substrate or a silicon-on-insulator Substrate (SOI) and the like;
then, forming at least one image sensing unit on the front surface of the semiconductor substrate 10, wherein the area where the image sensing unit is located is a photosensitive area 101 of the image sensor chip;
next, a plurality of pads 14 are formed around each image sensing unit.
A passivation layer 13 is formed on the front surface of the semiconductor substrate 10, wherein the passivation layer 13 is silicon oxide, silicon nitride, epoxy, polyimide, resin, FR4 or any other suitable dielectric material. The image sensing unit (including a photodiode) and a plurality of pads 14 distributed around the image sensing unit, the passivation layer 13, the semiconductor substrate 10 below and other related devices (such as peripheral MOS transistor circuits of the image sensing unit) around the image sensing unit form an image sensor chip (or image sensor chip region), the image sensing unit is usually partially located in the semiconductor substrate 10, partially located on the front surface of the semiconductor substrate 10, and located in a light-sensing region 101 of the image sensor chip, each pad 14 surrounds the image sensing unit and is electrically connected to the image sensing unit, wherein the passivation layer 13 is usually a stacked structure formed by stacking a plurality of dielectric layers, so that a metal interconnection structure of a plurality of metal layers can be formed therein, for connecting the image sensing unit in the image sensor chip and the peripheral MOS transistor circuit of the image sensing unit, the topmost metal layer of the metal interconnection structure finally forms a plurality of discrete connection pads on the surface of the passivation layer 13. Therefore, each bonding pad 14 is a metal structure formed by stacking a plurality of metal layers, and the flip-chip packaging process of the image sensor chip is to connect the back surface of the bonding pad to the back surface of the semiconductor substrate 10.
The process involved in step S1 is well known to those skilled in the art, and includes oxidation, pattern transfer, photolithography, doping, polysilicon deposition, metal deposition, etching, and so on, and will not be described herein again.
With continued reference to fig. 2A, in step S2, an adhesion layer 12 may be formed on the surface of the pad 14 by dispensing, painting, printing, rolling, or patterning the adhesive by a photolithography process, wherein the adhesion layer 12 has a thickness of 200 angstroms to 3000 angstroms and is composed of a chemical adhesive; the package substrate 11 is then bonded to the front side of the semiconductor substrate 10. Before the package substrate 11 is bonded to the front surface of the semiconductor substrate 10, a support layer may be formed on the surface of the pad 14 or on the surface of the package substrate 11 (not shown), so as to provide a reasonable space for the light sensing region 101 of the image sensor chip, and provide a support function for a subsequent packaging step, thereby preventing the package substrate from being pressed against the front surface of the chip and damaging the image sensor chip. An adhesive layer 12 is formed between the support layer and the pad 14. Preferably, the distance between the package substrate 11 and the photosensitive area 101 is greater than 10 micrometers.
With continued reference to fig. 2B, in step S3, the back surface of the semiconductor substrate 10 may be thinned by wafer lapping or etching to obtain a target thickness of the semiconductor substrate 10, for example, 100 to 200 μm; a trench (not shown) is then formed in the back side of the semiconductor substrate 10 by a photolithographic and etch process, with the trench etch stopping at the back side of the lowest metal layer at the bottom of the pad 14. The back thinning process of the wafer can reduce the depth-to-width ratio of groove etching and subsequent filling, and improve the performance of the groove etching and the subsequent filling.
Referring to fig. 2C, in step S4, an insulating layer 15 is deposited on the surface of the trench and the back surface of the semiconductor substrate 10 (i.e., the insulating layer 15 is partially filled in the trench, and the insulating layer has a thickness that does not fill the trench), and the insulating layer is made to partially cover the back surface of the semiconductor substrate 10 and a portion of the surface of the bottom metal layer that covers the pad 14 in the trench and is close to the semiconductor substrate 10 by photolithography and etching. The material of the insulating layer 15 may be one or more of silicon oxide, silicon nitride, and silicon oxynitride.
Referring to fig. 2D, in step S4, after the insulating layer 15 is formed, the metal layers on the outer edge of the pad 14 exposed by the insulating layer 15 are sequentially etched upwards in the trench, so that the metal layers on the outer edge of the pad 14 are stepped. When the stepped structure is formed, the etching degree from the bottommost metal layer of the bonding pad 14 to the topmost metal layer of the bonding pad 14 can be sequentially and uniformly decreased, so that the extending lengths of the bottommost metal layer to the topmost metal layer on the side wall of the trench are sequentially and uniformly lengthened. For example, the pad 14 at the trench is mainly formed by 3 metal layers, the bottom metal layer M1, the middle metal layer M2 and the top metal layer M3 are arranged in sequence from the back surface to the front surface of the semiconductor substrate 10, and in the step-shaped structure formed by etching the outer edges of the M1, the M2 and the M3 away from the photosensitive region 101 to different degrees in sequence in the trench, the step edge of M1 is shortest, the step edge of M3 is longest, and the surface and the side surface of each step are both metal and are used for contacting with a subsequently formed wiring metal layer. In order to avoid the influence on the adhesion performance of the package substrate 11 and the image sensor semiconductor substrate 10 to the maximum extent, when the metal layers of the bonding pad 14 are etched in the trench to form the stepped structure, at least the topmost metal layer of the bonding pad is not etched, for example, three metal layers of M1, M2 and M3 are sequentially arranged from the back surface to the front surface of the semiconductor substrate 10 for the bonding pad 14, and M3 is not etched, and when more than 4 metal layers are arranged for the bonding pad, the topmost metal layer and the next topmost metal layer can be not etched.
In other embodiments of the present invention, the forming order of the step-like structure of the insulating layer and the pad in step S4 may be interchanged, that is, after the trench etching in step S3 is completed, each metal layer in the pad is continuously etched in step S4 to form the step-like structure, and then the insulating layer 15 is deposited and etched on the surface of the trench and the back surface of the semiconductor substrate to expose each step of the step-like structure.
Referring to fig. 2E, in step S5, a wiring metal layer 16 is formed on the surface of the insulating layer by sputtering, electroplating or electroless plating, and the wiring metal layer 16 is subjected to photolithography and etching to form a pre-designed pattern. The wiring metal layer 16 may preferably be a laminated structure of TiW, which is an adhesion layer, and Cu, which is a wiring layer. The wiring metal layer 16 is in contact with each exposed surface of the stepped structure at the position of the pad 14, and has a relatively large contact area and high connection reliability. Meanwhile, the depth-to-width ratio of the groove is small, and the filling performance of the metal wiring layer 16 when the groove formed in the bonding pad 14 is filled is good, so that the performance of the metal wiring layer 16 is relatively reliable.
With continued reference to fig. 2E, in step S6, a protection layer 17 is formed on the surface of the metal wiring layer 16 by a deposition process to protect the wiring metal layer 16. And further photolithography and etching of the protective layer 17 are performed to form an opening (not shown) exposing the wiring metal layer 16 at a position where a solder bump is to be formed.
Referring to fig. 2F, in step S7, bumps 18 are formed at the opening positions by reflow soldering, ball-implanting, evaporation, electroless plating, electroplating, ball-placing, stencil printing, or solder paste printing, and the bumps 18 are in conductive contact with the metal wiring layer 16. In this embodiment, the bumps 18 may be formed on the pad by a reflow process, which includes: the solder layer is formed by an electroplating or deposition process, the material of the solder layer may include one or more of aluminum, tin, silver, lead, copper, zinc, bismuth, indium, gold, and antimony, such as tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium, or tin silver antimony, and the solder layer includes an active agent, and then reflow soldering may be performed by using nitrogen as a shielding gas and adopting a heating manner of temperature rise-constant temperature-Reflow (RSS) to form the bumps 18 in the openings. Specifically, the reflow soldering process firstly carries out temperature rise operation, and the temperature is stably raised at the temperature rise rate of 1-2 ℃/s from room temperature to about 100 ℃; then, carrying out constant temperature operation, wherein the temperature range of the constant temperature stage is 150-250 ℃, and the constant temperature time range is 50-100 s; finally, carrying out reflux operation, wherein the reflux time range is 30-60 s, and the temperature range is 225-250 ℃. It should be noted that, in other embodiments of the present invention, the solder bump may be formed by a ball-implanting method, an evaporation method, an electroless plating method, an electroplating method, a ball-placing method, a solder paste stencil printing method, or a printing solder paste method, which is not limited by the present invention.
According to the packaging method of the image sensor chip, the groove is formed at the position of the semiconductor substrate at the bottom of the bonding pad at the peripheral edge of the chip, and the bottom of the groove is exposed out of the back surface of the bonding pad; then trimming each metal layer of each bonding pad, and modifying the edge of each bonding pad into a step-shaped structure; forming a wiring metal layer in the groove and in conductive contact with the stepped structure, and forming a soldering tin bump on the wiring metal layer on the back surface of the chip, so that the chip electrical signal is transferred from the front surface of the chip to the back surface of the chip; compared with through silicon via interconnection, the formed groove has larger bottom size, so that the process difficulty of filling a wiring metal layer in a subsequent groove is reduced, and the problem of poor reliability caused by incomplete metal filling in the through silicon via is avoided; meanwhile, the contact area between the wiring metal layer and the bonding pad is increased due to the stepped structure, so that the adverse effect that the filled wiring metal layer is only contacted with the surface of the topmost metal layer or the bottommost metal layer of the bonding pad in the prior art is avoided, and the problem of poor connection reliability between the wiring metal layer and the bonding pad in the through silicon via is avoided; and because the through silicon via interconnection technology is avoided, the packaging process is simplified, and the packaging cost is reduced.
Referring to fig. 2F, the present invention further provides a package structure of an image sensor chip, including:
a semiconductor substrate 10;
an image sensor chip formed on the front surface of the semiconductor substrate 10;
a trench formed on the back surface of the semiconductor substrate 10;
a plurality of bonding pads 14 distributed in the semiconductor substrate 10 around the image sensor chip, wherein the bonding pads 14 at the groove are in a step-shaped structure formed by interconnection of a plurality of metal layers;
an insulating layer 15 covering the back surface of the semiconductor substrate 10 and exposing each step surface of the stepped structure;
a wiring metal layer 16 covering the insulating layer 15 and the exposed step surfaces of the stepped structure, and contacting the metal layer of each step of the stepped structure;
a protective layer 17 covering the surface of the wiring metal layer 16 and having a plurality of openings exposing the wiring metal layer 16; and
and a bump 18 disposed in the opening and in conductive contact with the wiring metal layer 16.
Further, the image sensor chip is located on a wafer, and the wafer includes the semiconductor substrate 10 and at least one image sensor chip formed on the front surface of the semiconductor substrate 10.
Further, the front surface of the wafer is covered with a passivation layer 13, and the image sensing units (i.e., the photosensitive regions 101) of the image sensor chip and the bonding pads 14 distributed around the image sensing units are partially formed in the passivation layer 13.
Furthermore, in the stepped structure, the extending lengths of the bottommost metal layer to the topmost metal layer on the side wall of the trench are sequentially and uniformly lengthened.
Therefore, the packaging structure of the image sensor chip provided by the invention transfers the chip electrical signal from the front side of the chip to the back side of the chip through the structures of the groove, the step-shaped bonding pad structure, the wiring metal layer and the soldering tin salient point, and compared with through silicon via interconnection, the packaging structure is relatively simple, and the packaging cost is reduced; and the performance of filling the wiring metal layer in the trench with the depth-to-width ratio is higher than that of filling the wiring metal layer in the traditional through silicon via, and the contact area of the stepped pad structure and the wiring metal layer is large, so that the problem of poor connection reliability of the wiring metal layer and the pad in the through silicon via is avoided.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (13)
1. A packaging method of an image sensor chip is characterized by comprising the following steps:
providing a packaging substrate and an image sensor chip, wherein the packaging substrate is provided with a light transmission area, the image sensor chip is formed on the front surface of a semiconductor substrate, a plurality of bonding pads are formed on the front surface of the semiconductor substrate around the image sensor chip, and each bonding pad is a metal structure formed by interconnection of a plurality of metal layers;
forming an adhesive layer on the surface of the bonding pad, and bonding the packaging substrate and the front surface of the semiconductor substrate through the adhesive layer, wherein the light-transmitting area corresponds to the light-sensing area of the image sensor chip;
thinning the back surface of the semiconductor substrate, and etching the thinned back surface of the semiconductor substrate to form a groove, wherein the groove exposes the bottommost metal layer of the bonding pad;
forming an insulating layer on the groove and the back surface of the semiconductor substrate, wherein the insulating layer covers the back surface of the semiconductor substrate and a part of surface, close to the semiconductor substrate, of the bottommost metal layer of the bonding pad exposed by the groove;
etching the bonding pad to different degrees to enable the multiple metal layers of the bonding pad to form a step-shaped structure, and at least reserving the topmost metal layer in the metal layers of the bonding pad not to be etched when etching the metal layers of the bonding pad at the groove to form the step-shaped structure;
forming wiring metal layers on the surfaces of the insulating layer and the stepped structure, wherein the wiring metal layers are in contact with each metal layer of the stepped structure;
forming a protective layer on the surface of the wiring metal layer, and etching the protective layer to form a plurality of openings exposing the wiring metal layer; and
bumps are provided in the openings.
2. The packaging method of claim 1, wherein the step of providing the image sensor chip comprises:
providing the semiconductor substrate;
forming at least one image sensing unit on the front surface of the semiconductor substrate, wherein the area where the image sensing unit is located is the photosensitive area;
a plurality of pads are formed around each image sensing unit.
3. The packaging method according to claim 2, wherein the image sensing unit and each pad are partially formed in a passivation layer on the front surface of the semiconductor substrate.
4. The method of claim 1, wherein the adhesive layer is formed by dispensing, painting, printing, rolling or patterning a photoresist by a photolithography process to adhere the package substrate and the front surface of the semiconductor substrate through the adhesive layer.
5. The packaging method according to claim 1, wherein the etching degree from the bottommost metal layer to the topmost metal layer of the bonding pad is gradually and uniformly decreased when the stepped structure is formed, so that the extending lengths of the bottommost metal layer to the topmost metal layer on the side wall of the trench are sequentially and uniformly lengthened.
6. The packaging method of claim 1, wherein the insulating layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, and an organic polymer.
7. The packaging method according to claim 1, wherein the bumps are formed at the opening positions by a reflow soldering method, a ball-implanting method, an evaporation method, an electroless plating method, an electroplating method, or a solder paste printing method.
8. The packaging method according to claim 1 or 7, wherein the material of the bump comprises one or more of aluminum, tin, silver, lead, copper, zinc, bismuth, indium, gold, and antimony.
9. An image sensor chip packaging structure manufactured by the image sensor chip packaging method according to any one of claims 1 to 8, comprising:
a semiconductor substrate;
an image sensor chip formed on a front surface of the semiconductor substrate;
the groove is formed on the back surface of the semiconductor substrate;
the bonding pads are distributed in the semiconductor substrate around the image sensor chip, the bonding pads at the grooves are of a step-shaped structure formed by interconnection of a plurality of metal layers, the step-shaped structure is formed by etching the metal layers of the bonding pads at the grooves to different degrees, and in the process of forming the step-shaped structure, at least the topmost metal layer of each metal layer of the bonding pads is not etched;
the insulating layer covers the back surface of the semiconductor substrate and exposes each step surface of the step-shaped structure;
a wiring metal layer covering the insulating layer and the exposed step surfaces of the stepped structure and contacting the metal layer of each step of the stepped structure;
a protective layer covering the surface of the wiring metal layer and having a plurality of openings exposing the wiring metal layer; and
a bump disposed in the opening and in conductive contact with the wiring metal layer;
the packaging substrate is provided with a light-transmitting area, the packaging substrate is adhered to the front face of the semiconductor substrate through an adhesive layer formed on the surface of the bonding pad, and the light-transmitting area corresponds to the light-sensing area of the image sensor chip.
10. The package structure of claim 9, wherein the image sensor die is on a wafer comprising a semiconductor substrate and at least one image sensor die formed on a front side of the semiconductor substrate.
11. The package structure of claim 10, wherein the front surface of the wafer is further covered with a passivation layer, and the image sensing unit of the image sensor chip and each of the pads distributed around the image sensing unit are partially formed in the passivation layer.
12. The package structure according to claim 9, wherein in the step-like structure, the extending lengths of the bottom-most metal layer to the top-most metal layer on the side wall of the trench are sequentially and uniformly lengthened.
13. The package structure of claim 9, wherein a material of the bump comprises one or more of aluminum, tin, silver, lead, copper, zinc, bismuth, indium, gold, and antimony.
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| CN109698208B (en) * | 2017-10-20 | 2023-06-30 | 新加坡有限公司 | Image sensor packaging method, image sensor packaging structure and lens module |
| CN108121364B (en) * | 2017-12-15 | 2021-04-23 | 上海索广映像有限公司 | Position adjusting system and method of image sensor |
| US11211414B2 (en) * | 2019-12-23 | 2021-12-28 | Omnivision Technologies, Inc. | Image sensor package |
| CN112992658B (en) * | 2021-04-15 | 2021-07-30 | 中芯集成电路制造(绍兴)有限公司 | Electroless plating method on bonding pad, semiconductor device and manufacturing method thereof |
| CN113540069B (en) * | 2021-07-20 | 2024-02-02 | 甬矽电子(宁波)股份有限公司 | Chip stack packaging structure and chip stack packaging method |
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| CN1314069A (en) * | 1999-04-30 | 2001-09-19 | 出光兴产株式会社 | Organic electroluminescent device and method of manufacturing the same |
| CN102142413A (en) * | 2010-02-01 | 2011-08-03 | 台湾积体电路制造股份有限公司 | Semiconductor element and manufacturing method thereof |
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