WO2019042120A1

WO2019042120A1 - Chip packaging structure and manufacturing method therefor, and electronic device

Info

Publication number: WO2019042120A1
Application number: PCT/CN2018/100301
Authority: WO
Inventors: 王双福
Original assignee: 华为技术有限公司
Priority date: 2017-08-29
Filing date: 2018-08-13
Publication date: 2019-03-07
Also published as: CN109427759A

Abstract

Disclosed are a chip packaging structure and a manufacturing method therefor, and an electronic device, which relate to the technical field of electronic packaging and solve the problem of a chip packaging structure being relatively thick. The specific solution involves: the chip packaging structure comprising a main chip; a first rewiring layer, which is arranged on an active face of the main chip and is electrically connected to the main chip; a second rewiring layer, which is arranged on a back face of the main chip and is in contact with the back face of the main chip; a first electrical connection part, which is arranged between the first rewiring layer and the second rewiring layer, wherein the first electrical connection part is used for electrically connecting the first rewiring layer to the second rewiring layer; and overlay chips, which are arranged on one side, away from the main chip, of the second rewiring layer and are electrically connected to the second rewiring layer. The chip packaging structure provided in the present application is used for being connected to a circuit board in an electronic device.

Description

Chip package structure and manufacturing method thereof, and electronic device

This application claims the priority of the Chinese Patent Application entitled "A Chip Package Structure and Its Manufacturing Method, Electronic Device", filed on August 29, 2017, with the application number of 201710771362.4, the entire contents of which are incorporated by reference. Combined in this application.

Technical field

The present application relates to the field of electronic packaging technologies, and in particular, to a chip package structure, a manufacturing method thereof, and an electronic device.

Background technique

With the rapid development of wireless communications, automotive electronics and other consumer electronics, electronic devices are moving toward versatility. Based on this, in the prior art, when the above electronic device is manufactured, chips of different functions are usually packaged separately, and then integrated, and the integrated components are disposed in the above electronic device.

The current package and integration technology is a package on package (POP) technology. Specifically, the chip package structure formed by the stacked package technology includes a stacked lower package and an upper package. The lower package includes a first functional chip mounted on the lower substrate by a molding compound (MC) or between the lower substrate and the interposer; the upper package includes a first package mounted on the upper substrate by a molding compound. Two-function chip. A solder ball for electrically interconnecting the upper package and the lower package is disposed between the upper package and the lower package.

Since the upper substrate, the lower substrate, and the adapter plate are limited by the manufacturing process of the substrate itself, the thickness of the metal layer in the substrate is about 20 μm, the thickness of the dielectric layer is about 45 μm, and the distance between the metal lines is about 16-18 μm. . Therefore, the thickness of the above substrate is large, resulting in a large thickness of the entire chip package structure, thereby causing a problem that the signal transmission path of the package structure is long and the heat dissipation performance is poor.

Summary of the invention

The present application provides a chip package structure, a manufacturing method thereof, and an electronic device, which solve the problem of a large thickness of the chip package structure.

To achieve the above objectives, the present application adopts the following technical solutions:

In a first aspect of the present application, a chip package structure includes: a main chip; a first redistribution layer disposed on an active surface of the main chip and electrically connected to the main chip; and a second rewiring layer disposed on the main chip a back surface and in contact with a back surface of the main chip; a first electrical connection member disposed between the first redistribution layer and the second redistribution layer and disposed in parallel with the main chip, the first electrical connector being used for the first The redistribution layer and the second redistribution layer are electrically connected; the stacked chip is disposed on a side of the second redistribution layer facing away from the main chip, and is electrically connected to the second redistribution layer. The main chip is a logic chip, and the superimposed chip is a memory chip. It can be seen from the above that in the chip package structure, it is not necessary to provide an adapter board and a solder ball for electrically connecting the package body of the chip having different functions, so that the thickness of the entire chip package structure is smaller, and the main chip is stacked to the chip. The signal transmission path is shorter. In addition, a dielectric layer composed of a resin film layer and a metal wiring layer alternately provided with the dielectric layer are included in any one of the first redistribution layer and the second redistribution layer. Therefore, the thickness of the redistribution layer is smaller with respect to the rewiring layer formed by the above dielectric layer than the substrate formed by the press-bonding process. In addition, since only the second redistribution layer having a thin thickness is formed between the superimposing chip and the main chip, it is advantageous to reduce the thermal resistance of the entire chip package structure and facilitate heat dissipation of the chip.

The chip package structure provided by the present application, in combination with the first aspect, in a possible implementation manner, the chip package structure further includes a second electrical connector. The second electrical connector is disposed between the active surface of the main chip and the first redistribution layer, and the second electrical connector is configured to electrically connect the main chip to the first redistribution layer. Wherein, the second electrical connector is a copper pillar.

The chip package structure provided by the present application, in combination with the first aspect, in another possible implementation, the chip package structure further includes a second electrical connector for electrically connecting the main chip and the first redistribution layer, the first The two electrical connectors include interconnecting terminals and pads that are in contact and electrically connected. The interconnect terminal is disposed on the active surface of the main chip. The pad is disposed on a side surface of the first redistribution layer adjacent to the main chip.

In conjunction with the first aspect, in another possible implementation, the interconnect terminal includes a first sub-portion adjacent the main chip and a second sub-portion adjacent the pad side. Wherein, the material constituting the first sub-portion includes at least one of metal copper, titanium, nickel, tungsten, and silver, and the material constituting the second sub-portion includes solder. In this case, the first sub-portion can provide a certain hardness to the interconnect terminals. In addition, a spot welding process on the second sub-portion can connect the interconnect terminals to the pads.

In combination with the first aspect, in another possible implementation, the first electrical connector is columnar, and the material constituting the first electrical connector is at least one of metallic copper, metallic aluminum, metallic silver, or solder. Metal copper or solder can be used for reasons of production cost.

In combination with the first aspect, in another possible implementation, the chip package structure further includes: a first molding layer and a second molding layer. The first molding layer is filled between the first redistribution layer and the second redistribution layer and wrapped around the main chip and the first electrical connection member, so that the main molding chip can be packaged by the first molding layer. Further, the second molding layer covers the stacked chip and is in contact with the second redistribution layer, thereby encapsulating the stacked chip with the second molding layer. In this case, the main chip and the superimposing chip in the chip package structure can be independently packaged.

In conjunction with the first aspect, in another possible implementation, the chip package structure further includes a bonding wire for electrically connecting the stacked chip to the second redistribution layer. The process of electrically connecting the superimposing chip and the second rewiring layer by the bonding wires is simpler.

In combination with the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the chip package structure further includes an under bump metal layer and solder balls sequentially disposed on a side of the first redistribution layer facing away from the main chip. The chip package structure can be connected to an external circuit board by solder balls.

In a second aspect of the present application, an electronic device is provided, comprising a circuit board and any one of the chip package structures described above. Wherein, in the case where a solder ball is disposed on a side of the first rewiring layer of the chip package structure facing away from the main chip, the circuit board is electrically connected to the solder ball. The above electronic device has the same technical effects as the chip package structure provided by the first aspect, and details are not described herein again.

In a third aspect of the present application, a method for fabricating a chip package structure is provided. In the case where the chip package structure includes a second electrical connector and the second connector is a copper post, the manufacturing method includes: first, at Forming a first protective layer on a carrier; next, forming a second redistribution layer on the first protective layer; next, connecting the back side of the main chip to the second redistribution layer; next, at the second weight The wiring layer faces away from a side surface of the first carrier, forming a first electrical connector disposed in parallel with the main chip, the first electrical connector is electrically connected to the second redistribution layer; and then, the second redistribution layer deviates from the first a side surface of a carrier plate forming a first molding layer wrapped around the main chip and the first electrical connector; next, forming an electrical connection with the first electrical connector and the main chip on the active surface of the main chip a first re-wiring layer; next, removing the first carrier and the first protective layer; next, a second protective layer and a second carrier are sequentially formed on a side surface of the first redistribution layer facing away from the main chip; Next, the load on the second carrier And forming a superimposing chip electrically connected to the second rewiring layer on a side surface of the second rewiring layer facing away from the main chip; and then forming a superimposing chip on a side surface of the second rewiring layer facing away from the main chip a second molding layer; next, removing the second carrier layer and the second protective layer; finally, on the side of the first redistribution layer facing away from the main chip, the under bump metal layer and the solder balls are sequentially formed. The manufacturing method of the chip package structure described above has the same technical effect as the chip package structure provided by the first aspect, and details are not described herein again.

In a fourth aspect of the present application, a method of fabricating a chip package structure is provided, wherein the chip package structure includes a second electrical connector, and the second electrical connector includes interconnecting terminals and pads that are in contact and electrically connected The manufacturing method includes the following steps: first, forming a first protective layer on the first carrier; next, forming a first redistribution layer on the first protective layer; and then, the active surface of the main chip and the first rewiring a layer electrical connection; next, a first electrical connection member disposed in parallel with the main chip on the side surface of the first redistribution layer facing away from the first carrier, the first electrical connection member being electrically connected to the first redistribution layer Next, a first molding layer wrapped around the main chip and the periphery of the first electrical connection member is formed on a side surface of the first redistribution layer facing away from the first carrier, and then formed on the back surface of the main chip. a second redistribution layer electrically connected to the first electrical connection; next, a superimposing chip electrically connected to the second redistribution layer is formed on a side of the second redistribution layer facing away from the main chip; Double wiring layer away from the main core a side surface, forming a second molding layer covering the stacked chip; next, removing the first carrier and the first protective layer; finally, forming a bump under the side of the first redistribution layer facing away from the main chip Metal layer and solder balls. The manufacturing method of the chip package structure described above has the same technical effect as the chip package structure provided by the first aspect, and details are not described herein again.

DRAWINGS

1 is a schematic structural diagram of a chip package structure provided by the present application;

2 is a schematic structural diagram of another chip package structure provided by the present application;

3 is a schematic structural diagram of still another chip package structure provided by the present application;

4 is a schematic structural view of the second electrical connector of FIG. 3;

FIG. 5 is a schematic structural diagram of still another chip package structure provided by the present application; FIG.

6 is a schematic structural diagram of a package structure fabricated by using a HBPOP process according to the present application;

7 is a schematic structural view of a package structure fabricated by using an InFO POP process according to the present application;

FIG. 8 is a flowchart of a method for fabricating a chip package structure according to the present application; FIG.

9a, 9b, 9c, 9d, 9e, and 9f are respectively schematic structural views obtained by performing the respective manufacturing steps shown in Fig. 8;

FIG. 10 is a flow chart of another method for fabricating a chip package structure provided by the present application; FIG.

11a, 11b, 11c, 11d, and 11e are schematic views respectively showing the respective manufacturing steps shown in Fig. 10.

Reference mark:

01-chip package structure; 10-main chip; 11-superimposing chip; 20-first redistribution layer; 21-second redistribution layer; 201-dielectric layer; 202-metal wiring layer; 310-interconnect terminal; 320-pad; 30-first electrical connector; 31-second electrical connector; 310-interconnect terminal; 3111-first sub-section; 3122-second sub-section; 320-pad; 32-bond Lead wire; 40-first molding layer; 41-second molding layer; 50-under bump metal layer; 51-bump ball; 60-array plate; 61-memory chip substrate; 62-logic chip substrate; - memory chip solder ball; 80 - first carrier plate; 81 - second carrier plate; 90 - first protective layer; 91 - second protective layer.

Detailed ways

The present application provides a chip package structure 01, as shown in FIG. 1, comprising: a main chip 10, a first redistribution layer 20, a second redistribution layer 21, a first electrical connector 30, and a stacked chip 11.

It should be noted that the number of the above-mentioned main chip 10 and superimposing chip 11 is not limited in the present application. Further, the above-described main chip 10 and superimposing chip 11 generally have different functions. For example, the main chip 10 may be a logic chip, and the superimposing chip 11 may be a memory chip. In this case, when the chip package structure 01 has a plurality of logic chips as the master chip 10, the plurality of master chips 10 may be located on the same plane and spaced apart. In this case, the first electrical connector 30 may be disposed between the adjacent two main chips 10, or may not be provided. Those skilled in the art can make settings as needed.

In addition, when the chip package structure 01 has a plurality of memory chips as the stacked chips 11, the plurality of stacked chips 11 may be disposed in parallel, or may be stacked as shown in FIG.

Based on this, any one of the first redistribution layer 20 and the second redistribution layer 21 (Restribution Layer, RDL) includes a multilayer dielectric layer 201 and a plurality of metal wiring layers as shown in FIG. 202. A metal wiring layer 202 is alternately disposed with a dielectric layer 201. The multilayer metal wiring layer 202 constitutes a metal wiring structure in the redistribution layer. In addition, a via hole for electrically connecting adjacent two metal wiring layers 202 is further disposed on the dielectric layer 201.

The dielectric layer 201 of the redistribution layer may be an insulating resin material, such as polybenzoxazole (PBO) or polyimide (PI), and formed by a spin coating process. Film layer. The metal wiring layer 202 may be formed by a physical vapor deposition (PVD) process in combination with a plating process, and the material constituting the metal wiring layer 202 may include metal copper or the like.

Hereinafter, the installation positions and connection manners of the main chip 10, the first redistribution layer 20, the second redistribution layer 21, the first electrical connector 30, and the superimposing chip 11 will be described in detail with reference to the drawings.

Specifically, the main chip 10 includes an active surface and a back surface disposed opposite to the active surface. The active surface is provided with a signal interface for providing an external signal path for the circuit inside the main chip 10. The active surface of the main chip 10 is fixed on the first redistribution layer 20 by the second connection member 31, and the signal interface on the active surface is electrically connected to the metal wiring structure in the first redistribution layer 20 through the second connection member 31. . In this case, the main chip 10 can perform signal transmission with the first redistribution layer 20 through the active surface.

In the embodiment of the present invention, one end of the second electrical connector 31 is connected to the active surface of the main chip 10, and the other end is opposite to the exposed metal wiring layer 202 on the surface of the first rewiring layer 20 on the side close to the active surface. The purpose of electrically connecting the second electrical connector 31 to the metal wiring structure in the first redistribution layer 20 is achieved. In this way, the active surface of the main chip 10 and the first redistribution layer 20 are electrically connected through the second electrical connection 31.

The second electrical connector 31 may be a copper pillar as shown in FIG. 1 .

Alternatively, for example, the second electrical connector 31 described above, as shown in FIG. 2 or FIG. 3, includes interconnecting terminals 310 and pads 320 that are in contact and electrically connected.

In this case, the above-described interconnection terminal 310 is disposed on the active surface of the main chip 10, and the pad 320 is disposed on the side surface of the first redistribution layer 20 adjacent to the main chip 10.

Specifically, the pad 320 may be an Under Bump Metallization (UBM), and the under bump metal layer includes a plurality of metal thin film layers. The metal wiring layer 202 exposed on the side surface of the first redistribution layer 20 close to the active surface may be covered by the under bump metal layer. The under bump metal layer may serve to adhere the interconnect terminal 310 and to block the interdiffusion of the metal material constituting the interconnect terminal 310 and the material constituting the bare metal wiring layer 202 on the first redistribution layer 20. .

Based on this, the above-mentioned interconnection terminal 310 can be a solder ball as shown in FIG. 2 .

Alternatively, the interconnect terminal 310 can be a solder-containing connection post as shown in FIG. In this case, the interconnect terminal 310, as shown in FIG. 4, may be composed of two parts, including a first sub-portion 3111 adjacent to the main chip 10 and a second sub-portion 3112 near the side of the pad 320.

The material constituting the first sub-portion 3111 includes at least one of metallic copper, titanium, nickel, tungsten, and silver. The material constituting the second sub-portion 3112 includes solder. In this way, the first sub-portion 3111 can provide a certain hardness to the interconnect terminal 310. In addition, a spot welding process on the second sub-portion 3112 can connect the interconnect terminal 310 to the pad 320.

On the basis of this, in order to integrate chips having different functions in the chip package structure 01, the chip package structure 01 further includes a second redistribution layer 21, as shown in FIG. 1, FIG. 2 or FIG. The layer 21 is disposed on the back surface of the main chip 10 and is in contact with the back surface of the main chip 10.

In this case, the first electrical connector 30 is provided in parallel with the main chip 10 between the first redistribution layer 20 and the second redistribution layer 21. One end of the first electrical connector 30 is electrically connected to the exposed metal wiring layer 202 on the surface of the first redistribution layer 20 on the side close to the main chip 10, and the other end is adjacent to the main chip 10 of the second redistribution layer 21. The bare metal wiring layer 202 on the surface of one side is electrically connected, so that communication between the first redistribution layer 20 and the second redistribution layer 21 can be achieved by the first electrical connection member 30.

Hereinafter, the structure of the first electrical connector 30 will be described in detail.

Specifically, for example, as shown in FIG. 1, FIG. 2 or FIG. 3, the first electrical connector may be cylindrical, such as a cylinder. At this time, the material constituting the first electrical connection member 30 may be at least one of metallic copper, metallic aluminum, metallic silver, or solder. Metal copper or solder can be used for reasons of production cost. For example, the material constituting the first electrical connection member 30 is metallic copper, and may be on the side of the first redistribution layer 20 close to the main chip 10 or on the side of the second redistribution layer 21 close to the main chip 10. The electroplating process forms the first electrical connector 30 described above.

In this case, after the main chip 10 is packaged, the chip package structure 01 further includes a first molding layer 40. The first molding layer 40 is filled between the first redistribution layer 20 and the second redistribution layer 21 and wrapped around the main chip 10 and the first electrical connector 30. The main chip 10 can be packaged by the first molding layer 40 to provide physical protection to the main chip 10.

At this time, the hole formed by the first molding layer 40 wrapped around the first electrical connector 30 is a Through Integrated Fan Out Vias (TIV). The shape of the TIV is determined by the shape of the first electrical connector 30 described above.

Alternatively, for example, the shape of the longitudinal interface of the first electrical connector 30 may be elliptical as shown in FIG. At this time, the material constituting the first electrical connection member 30 may be solder. When the first electrical connector 30 is fabricated, a first molding layer 40 for packaging the main chip 10 is first formed, and then formed on the first molding layer 40 to expose the first red wiring layer 20 or the second weight. Through Mold Vias (TMV) of the metal layer on the wiring layer 21. Next, solder ball filling is performed in the TMV and reflowed to form a solder post, which is the first electrical connector 30 described above.

Of course, the above is only an example of the structure, material, and manufacturing method of the first electrical connector 30. The structure, material, and manufacturing method of the first electrical connector 30 are not limited.

On the basis of this, the superimposing chip 11 is disposed on a side of the second redistribution layer 21 facing away from the main chip 10, and is electrically connected to the second redistribution layer 21.

Taking the superimposing chip 11 as a memory chip as an example, the superposing chip 11 can be connected to the bare metal layer on the second redistribution layer 21 through the bonding wire 32 as shown in FIG. 5, so that the bonding wire 32 can pass through the bonding wire 32. The bonding wires electrically connect the stacked chips 11 to the second redistribution layer 21.

Based on this, in order to package the above-described stacked chip 11, the above-described chip package structure 01 further includes a second molding layer 41. The second molding layer 41 covers the stacked chip 11 and is in contact with a side surface of the second redistribution layer 21 adjacent to the stacked chip 11. The stacked chip 11 can be packaged by the second molding layer 41 and provide physical protection to the stacked chip 11.

It is to be noted that the above-described first molding layer 40 and second molding layer 41 may be formed by a molding process, and the materials constituting the first molding layer 40 and the second molding layer 41 are molded (Molding Compand) )material.

In addition, in order to enable the chip package structure 01 to be connected to a printed circuit board (PCB) in the electronic device, the chip package structure is as shown in FIG. 3, and further includes sequentially disposed on the first redistribution layer 20 away from the main The metal layer 50 and the solder balls 51 are bumped on the side of the chip 10.

As can be seen from the above, the present application provides a chip package structure 01 main chip 10, a first redistribution layer 20, a second redistribution layer 21, a first electrical connector 30, and a stacked chip 11. In this case, the bonding chip 32, the second redistribution layer 21, the first electrical connection member 30, the first redistribution layer 20, and the second electrical connection member 31 may be sequentially passed between the main chips 10 of the superimposing chip 11 Communication. On the basis of this, communication with the external electronic system is realized by the solder balls 51 located on the side of the first redistribution layer 20 facing away from the main chip 10.

Based on this, for the package structure shown in FIG. 6 fabricated by using High Bandwidth Package on Package (HBPOP) technology, in order to realize communication between the logic chip and the memory chip, the logic chip in the HBPOP structure is used. It is packaged between the logic chip substrate 62 and the interposer 60 by a molding material to form a separate package. The memory chip is packaged on the memory chip substrate 61 by a molding material to form another independent package. Then, the two separate packages are electrically connected through the memory chip solder balls 70. The dielectric layers of the logic chip substrate 62, the interposer 60, and the memory chip substrate 61 are formed by a press-bonding process, and the semi-cured material to be pressed has a large thickness, so that the thickness of the substrate is large. Specifically, the thickness H of the above HBPOP structure is 1.1 to 1.3 mm. In this case, the memory chip needs to communicate with the logic chip through the memory chip substrate 61, the memory chip solder ball 70, the interposer board 60, the TMV, and the logic chip substrate 62 in sequence, so the signal transmission path of the memory chip to the logic chip is 10 ~15mm, the signal transmission path is long.

In addition, for the package structure shown in FIG. 7 fabricated by the Integrated Fan Out Package on Package (InFO POP) technology, the InFO POP is used to implement communication between the logic chip and the memory chip. The logic chip in the structure is encapsulated between two oppositely disposed redistribution layers by a molding material to form a separate package. The memory chip is packaged on the memory chip substrate 61 by a molding material to form another independent package. Then, the two separate packages are electrically connected through the memory chip solder balls 70. Among them, only the dielectric layer of the memory chip substrate 61 in the InFO POP structure is formed by a press-bonding process. Therefore, the thickness H of the InFO POP structure is reduced from 0.9 to 1.1 mm with respect to the HBPOP structure. In this case, the memory chip needs to communicate with the logic chip through the memory chip substrate 61, the memory chip solder ball 70, the redistribution layer above the logic chip, the TIV, and the redistribution layer under the logic chip, and store the chip to the logic chip. The signal transmission path can be reduced to 8 to 12 mm.

As can be seen from the above, in the chip package structure 01 provided by the present application, the main chip 10 is packaged between the first redistribution layer 20 and the second redistribution layer 21, and then the stacked chip is packaged on the second redistribution layer 21. Above. Therefore, with respect to the HBPOP structure shown in FIG. 6, in the chip package structure 01 provided by the present application, only the second redistribution layer 21 is provided between the main chip 10 and the superimposing chip 11, so that the second rewiring layer 21 can replace the memory chip substrate 61. The interposer board 60 and the memory chip solder ball 70 in FIG. 6 are omitted, and the first re-wiring layer 20 is replaced with the logic chip substrate 62. In addition, with respect to the InFO POP structure shown in FIG. 7, the chip package structure 01 provided by the present application can also enable the second redistribution layer 21 to replace the memory chip substrate 61, so that the memory chip soldering in FIG. 7 can be omitted. Ball 70. In this way, the omitted structure can make the thickness H of the entire chip package structure 01 smaller, and the signal transmission path of the main chip 10 to the superimposing chip 11 is shorter. On the basis of this, since any one of the first redistribution layer 20 and the second redistribution layer 21 includes a thin film layer formed by a spin coating process as the dielectric layer 201, and two adjacent layers A metal wiring layer 202 formed between the dielectric layers 201 by a PVD process in combination with an electroplating process. Therefore, the thickness of the redistribution layer is smaller with respect to the re-wiring layer formed by the dielectric layer 201 with respect to the substrate formed by the press-bonding process (for example, the memory chip substrate 61 or the logic chip substrate 62). Further, the line width and the line pitch of the metal wires in the redistribution layer can be made to a minimum of about 2 μm. Thereby the integration rate of the circuit is higher. In summary, the chip package structure 01 provided by the present application can adopt the above-mentioned redistribution layer, so that the thickness H of the entire chip package structure 01 can be less than 0.9 mm, and the signal transmission path of the main chip 10 to the superimposing chip 11 can reach 5 to 8mm.

In addition, one of the heat dissipation paths of the main chip 10 in the chip package structure 01 is such that heat is conducted upward. In this case, as described above, only the second thickness of the thin chip 11 and the main chip 10 are thin. The wiring layer 21 is therefore advantageous for reducing the thermal resistance of the entire chip package structure 01, which is advantageous for heat dissipation of the chip.

The present application provides an electronic device including a circuit board and any one of the chip package structures 01 as described above. In this case, as shown in FIG. 3, in the case where the solder ball 51 is disposed on the side of the first re-wiring layer 20 of the chip package structure 01 facing away from the main chip 01, the circuit board can be electrically connected to the solder ball 51. Therefore, the chip package structure 01 and the electronic system in the electronic device can be transmitted.

It should be noted that the foregoing electronic device has the same technical effects as the chip package structure 01 provided in the foregoing embodiment, and details are not described herein again.

The present application provides another method for fabricating any of the chip package structures 01 as described above, in which the chip package structure 01 includes a second connector 31 as shown in FIG. 1 and the second connector 31 In the case of a copper pillar, as shown in FIG. 8, the method includes:

S101, as shown in FIG. 9a, a first protective layer 90 is formed on the first carrier 80.

S102, as shown in FIG. 9a, a second redistribution layer 21 is formed on the first protective layer 80.

S103, as shown in FIG. 9b, the back surface of the main chip 10 is connected to the second redistribution layer 21.

S104, as shown in FIG. 9c, on a side surface of the second redistribution layer 21 facing away from the first carrier 80, forming a first electrical connector 30 disposed in parallel with the main chip 10, the first electrical connector 30 and the first The double wiring layer 21 is electrically connected.

S105, as shown in Fig. 9c, on the side of the second redistribution layer 21 facing away from the first carrier 80, a first molding layer 40 is formed which is wrapped around the main chip 10 and the first electrical connector 30.

It should be noted that the step S104 of forming the first electrical connector 30, the step S105 of forming the first molding layer 40, and the step S103 of connecting the main chip 10 and the second redistribution layer 21 are as described above. I will not repeat them here.

S106, as shown in FIG. 9d, on the active surface of the main chip 10, a first redistribution layer 20 electrically connected to the first electrical connector 30 and the main chip 10 is formed.

S107. The first carrier 80 and the first protective layer 90 are removed.

S108. As shown in FIG. 9e, on the side surface of the first redistribution layer 20 facing away from the main chip 10, a second protective layer 91 and a second carrier 81 are sequentially formed.

S109, as shown in FIG. 9f, under the bearing of the second carrier 91, on the side of the second redistribution layer 21 facing away from the main chip 10, a superimposing chip 11 electrically connected to the second redistribution layer 21 is formed.

The manner in which the superimposing chip 11 and the second re-wiring layer 21 are electrically connected is not described herein again.

S110, on a side surface of the second redistribution layer 21 facing away from the main chip 10, a second molding layer 41 covering the superposition chip 11 is formed.

S111, removing the second carrier 81 and the second protective layer 91.

S112. As shown in FIG. 1, on the side of the first redistribution layer 20 facing away from the main chip 10, the under bump metal layer 50 and the solder balls 51 are sequentially formed.

Alternatively, the present application provides a method for fabricating any of the chip package structures 01 as described above, wherein the package structure 01 includes a second connector 31 as shown in FIG. 2 or FIG. In the case where the two connectors 31 include interconnecting terminals 310 and pads 320 that are in contact and electrically connected, as shown in FIG. 10, the method includes:

S201, as shown in FIG. 11a, a first protective layer 90 is formed on the first carrier 80.

The first carrier 80 may be a glass substrate or a substrate made of a hard resin material. The first protective layer 90 may be formed of a soft resin material, thereby facilitating the peeling of the first carrier 80 and the first protective layer 90 in a subsequent step. In addition, since the texture of the first protective layer 90 is soft, the first protective layer 90 can buffer the structure formed on the first protective layer 90 after an external force acts on the first carrier 80. effect.

S202, as shown in FIG. 11a, a first redistribution layer 20 is formed on the first protective layer 90.

S203. The active surface of the main chip 10 is electrically connected to the first redistribution layer 20.

Specifically, the second electrical connector 31 is an interconnection terminal 310 formed on the active surface of the main chip 10 by an electroplating process, and a pad 320 formed on the first rewiring layer 20, as shown in FIG. 11b. . The structure of the interconnecting terminal 310 is as described above, and details are not described herein again.

S204, as shown in FIG. 11c, on a side surface of the first redistribution layer 20 facing away from the first carrier 80, forming a first electrical connector 30 disposed in parallel with the main chip 10, the first electrical connector 30 and the first A wiring layer 20 is electrically connected.

S205, as shown in FIG. 11c, on the side surface of the first redistribution layer 20 facing away from the first carrier 80, a first molding layer 40 wrapped around the main chip 10 and the first electrical connector 30 is formed. Thereby, the package of the main chip 10 is completed.

Specifically, a molding layer wrapped around the main chip 10 and the first electrical connector 30 may be formed by a molding process using a molding material. On the basis of this, in order to reduce the distance between the main chip 10 and the superimposing chip 11, and expose the first electrical connection member 30, the thickness of the molding layer can be reduced by a thinning process to form the first molding layer. 40.

It should be noted that the sequence of the above steps is not limited in this application, and the order of the above steps may be adjusted according to different manufacturing processes. For example, the above step S204 may be located before step S205, that is, before the first molding layer 40 is formed, the first electrical connector 30 may be fabricated on the surface of the first redistribution layer 20 by an electroplating process as shown in FIG. 11a. . At this time, step S204 may be located before step S203, that is, after the first electrical connector 30 is fabricated, the main chip 10 is placed on one side of the at least one first connector 30.

Alternatively, for example, the above step S204 may be after the step S205, that is, after the first molding layer 40 is formed, the TMV hole is formed on the first molding layer 40, and the solder ball is filled in the TMV hole and reflowed. To form the first electrical connector 30 described above.

S206, as shown in FIG. 11d, on the back surface of the main chip 10, a second redistribution layer 21 electrically connected to the first electrical connector 30 is formed.

S207, as shown in FIG. 11e, on the side surface of the second redistribution layer 21 facing away from the main chip 10, a superimposing chip 11 electrically connected to the second redistribution layer 21 is formed.

Among them, the bonding chip 11 can be electrically connected to the second redistribution layer 21 through the bonding wires 32 by a bonding process.

S208, as shown in FIG. 11e, on the side surface of the second redistribution layer 21 facing away from the main chip 10, a second molding layer 41 covering the superposition chip 11 is formed to complete the encapsulation of the main chip 11.

As apparent from the above, the main chip 10 is packaged by the first molding layer 40, and the superposed chip 11 is packaged by the second molding layer 41. In the chip package structure provided by the present application, the main chip 10 and the superimposing chip 11 are independently packaged, the performance between different chips does not affect each other, and the main chip 10 and the superimposing chip 11 are integrated in the packaging stage. The material constituting the first molding layer 40 and the second molding layer 41 may be the same or different.

S209, removing the first carrier 80 and the first protective layer 90.

Specifically, the first carrier 80 and the first protective layer 90 may be peeled off by a lift-off process.

S210. As shown in FIG. 3, on the side of the first redistribution layer 20 facing away from the main chip 10, the under bump metal layer 50 and the solder balls 51 are sequentially formed.

It should be noted that the interconnection terminals 310 in FIGS. 11b to 11e are all illustrated by taking the connection pillar containing solder in FIG. 3 as an example. When the interconnection terminal 310 is a solder ball as shown in FIG. 2, the manufacturing method is similarly available, and details are not described herein again.

In addition, the manufacturing method of the chip package structure described above has the same technical effects as the chip package structure provided in the foregoing embodiment, and details are not described herein again.

The above is only the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions within the technical scope of the present invention should be covered by the scope of the present invention. . Therefore, the scope of the invention should be determined by the scope of the appended claims.

Claims

A chip package structure, comprising:

main chip;

a first redistribution layer disposed on the active surface of the main chip and electrically connected to the main chip;

a second redistribution layer disposed on a back surface of the main chip and in contact with a back surface of the main chip;

a first electrical connection member disposed between the first redistribution layer and the second redistribution layer, the first electrical connection member for using the first redistribution layer and the second redistribution layer Layer electrical connection;

And superposing a chip disposed on a side of the second redistribution layer facing away from the main chip and electrically connected to the second redistribution layer.
The chip package structure of claim 1 , wherein the chip package structure further comprises a second electrical connector; the second electrical connector is disposed on the active surface of the main chip and the first rewiring Between the layers, the second electrical connector is for electrically connecting the main chip and the first redistribution layer;

The second electrical connector is a copper post.
The chip package structure of claim 1 , wherein the chip package structure further comprises a second electrical connector; the second electrical connector is disposed on the active surface of the main chip and the first rewiring Between the layers, the second electrical connector is for electrically connecting the main chip and the first redistribution layer;

Wherein the second electrical connector comprises interconnecting terminals and pads that are in contact and electrically connected;

The interconnection terminal is disposed on the active surface of the main chip; the pad is disposed on a side surface of the first redistribution layer adjacent to the main chip.
The chip package structure according to claim 3, wherein the interconnection terminal comprises a first sub-portion adjacent to the main chip and a second sub-section adjacent to a side of the pad;

The material constituting the first sub-portion includes at least one of metal copper, titanium, nickel, tungsten, and silver;

The material constituting the second sub-portion includes solder.
The chip package structure according to claim 1, wherein the first electrical connector is columnar, and the material constituting the first electrical connector is at least one of metal copper, metal aluminum, metal silver or solder. Kind.
The chip package structure according to claim 1, wherein the chip package structure further comprises:

a first molding layer filled between the first redistribution layer and the second redistribution layer and wrapped around the main chip and the first electrical connector;

A second molding layer covers the stacked chip and is in contact with the second redistribution layer.
The chip package structure according to claim 1, wherein the chip package structure further comprises a bonding wire for electrically connecting the stacked chip to the second redistribution layer.
The chip package structure according to claim 1, wherein the main chip is a logic chip, and the superimposing chip is a memory chip.
The chip package structure according to any one of claims 1 to 8, wherein the chip package structure further comprises a lower under bump metal layer disposed on a side of the first redistribution layer facing away from the main chip And solder balls.
An electronic device, comprising: a circuit board; and the chip package structure according to any one of claims 1-9;

In the case where a solder ball is disposed on a side of the first rewiring layer of the chip package structure facing away from the main chip, the circuit board is electrically connected to the solder ball.
A method for fabricating a chip package structure according to any one of claims 1 to 9, wherein the chip package structure comprises a second electrical connector, and the second connector is In the case of a copper pillar, the method includes:

Forming a first protective layer on the first carrier;

Forming a second redistribution layer on the first protective layer;

Connecting the back surface of the main chip to the second redistribution layer;

Forming a first electrical connection member on a side of the second redistribution layer facing away from the first carrier, the first electrical connector being electrically connected to the second redistribution layer;

Forming a first molding layer wrapped around the main chip and the first electrical connection member on a side surface of the second redistribution layer facing away from the first carrier;

Forming, on an active surface of the main chip, a first redistribution layer electrically connected to the first electrical connector and the main chip;

Removing the first carrier and the first protective layer;

Forming a second protective layer and a second carrier in sequence on a side surface of the first redistribution layer facing away from the main chip;

And superposing a chip electrically connected to the second redistribution layer on a side surface of the second redistribution layer facing away from the main chip under the bearing of the second carrier;

Forming a second molding layer covering the stacked chip on a side surface of the second redistribution layer facing away from the main chip;

Removing the second carrier and the second protective layer;

On the side of the first redistribution layer facing away from the main chip, an under bump metal layer and a solder ball are sequentially formed.
A method for fabricating a chip package structure according to any one of claims 1 to 9, wherein the chip package structure comprises a second electrical connector, and the second electrical connector In the case of interconnecting terminals and pads that are in contact and electrically connected, the method includes:

Forming a first protective layer on the first carrier;

Forming a first redistribution layer on the first protective layer;

Electrically connecting the active surface of the main chip to the first redistribution layer;

Forming a first electrical connection member on a side of the first redistribution layer facing away from the first carrier, the first electrical connector being electrically connected to the first redistribution layer;

Forming a first molding layer wrapped around the main chip and the first electrical connection member on a side surface of the first redistribution layer facing away from the first carrier;

Forming a second redistribution layer electrically connected to the first electrical connector on a back side of the main chip;

Forming a stacked chip electrically connected to the second redistribution layer on a side surface of the second redistribution layer facing away from the main chip;

Forming a second molding layer covering the stacked chip on a side surface of the second redistribution layer facing away from the main chip;

Removing the first carrier and the first protective layer;

On the side of the first redistribution layer facing away from the main chip, an under bump metal layer and a solder ball are sequentially formed.