CN112151457A - Packaging structure, manufacturing method thereof and electronic equipment - Google Patents
Packaging structure, manufacturing method thereof and electronic equipment Download PDFInfo
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- CN112151457A CN112151457A CN202011001467.XA CN202011001467A CN112151457A CN 112151457 A CN112151457 A CN 112151457A CN 202011001467 A CN202011001467 A CN 202011001467A CN 112151457 A CN112151457 A CN 112151457A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000004806 packaging method and process Methods 0.000 title abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 239000010410 layer Substances 0.000 claims description 135
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000012790 adhesive layer Substances 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 description 7
- 230000003993 interaction Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000012778 molding material Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 3
- 230000004308 accommodation Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009975 flexible effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012815 thermoplastic material Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The application discloses a packaging structure, a manufacturing method thereof and electronic equipment, wherein the packaging structure comprises a substrate, a first chip module, a second chip module, a first redistribution layer and a second redistribution layer; the substrate is provided with a first surface, a second surface and a cavity which are mutually deviated, the first surface and the second surface are arranged oppositely, and the cavity penetrates through the first surface; the first chip module is arranged in the cavity; the first redistribution layer is arranged on the first surface and covers the cavity; the second redistribution layer is arranged on the second surface and electrically connected with the first redistribution layer; the second chip module is arranged on the second redistribution layer; the first chip module is electrically connected with at least one of the first redistribution layer and the second redistribution layer, and the second chip module is electrically connected with the second redistribution layer. The scheme can solve the problem that the thickness and the size of the existing packaging structure are large.
Description
Technical Field
The application belongs to the technical field of semiconductor packaging, and particularly relates to a packaging structure, a manufacturing method thereof and electronic equipment.
Background
With the advancement of technology, there is a demand for miniaturization and size reduction of electronic components based on the improvement of the functional performance of the electronic components, and at present, the electronic components are usually integrated with higher density, and a Package On Package (POP) is a commonly used means for increasing the integration density of the electronic components.
In the POP packaging structure, the chips are packaged between two substrates, and different substrates need to be electrically connected and fixed through solder balls, so that a multilayer substrate and a multilayer solder ball exist in the thickness direction of the packaging structure, and the thickness dimension of the whole packaging structure is larger, which is not beneficial to the light and thin design of electronic equipment; the above problem is more prominent when there is a case where the capacity of the chip itself is too high.
Disclosure of Invention
An object of the embodiments of the present application is to provide a package structure, a manufacturing method thereof, and an electronic device, which can solve the problem that the thickness and the size of the existing package structure are large.
In order to solve the technical problem, the present application is implemented as follows:
in a first aspect, an embodiment of the present application provides a package structure, where the package structure includes:
the substrate is provided with a first surface, a second surface and a cavity, the first surface and the second surface are arranged oppositely, and the cavity penetrates through the first surface;
the first chip module is arranged in the cavity;
a first redistribution layer disposed on the first surface and covering the cavity;
a second redistribution layer disposed on the second surface and electrically connected to the first redistribution layer;
a second chip module disposed on the second redistribution layer;
wherein the first chip module is electrically connected to at least one of the first redistribution layer and the second redistribution layer, and the second chip module is electrically connected to the second redistribution layer.
In a second aspect, an embodiment of the present application provides an electronic device, which includes the foregoing package structure.
In a third aspect, an embodiment of the present application provides a method for manufacturing a package structure, including:
providing a substrate, and constructing a cavity on a first surface of the substrate;
providing a first chip module, and placing the first chip module in the cavity;
laminating and assembling a first redistribution layer on the first surface of the substrate, and covering the cavity through the first redistribution layer;
laminating and assembling a second redistribution layer on the second surface of the substrate and electrically connecting the second redistribution layer with the first redistribution layer;
and providing a second chip module, and placing the second chip module on the second redistribution layer.
In the package structure disclosed in the embodiment of the present application, the first chip module is disposed in the cavity of the substrate, the first surface of the substrate is provided with a first redistribution layer, the second surface of the substrate is provided with a second redistribution layer, and the second chip module is disposed on the second redistribution layer and uses the second redistribution layer as a configuration carrier; meanwhile, the first redistribution layer and the second redistribution layer are electrically connected, so that the normal use of the whole packaging structure can be realized after the first redistribution layer is installed on an installation base.
Compared with the prior art, the packaging structure disclosed by the embodiment of the application realizes the stack packaging of the electronic elements by embedding the first chip module in the substrate and arranging the second chip module on the second redistribution layer by only utilizing one substrate, avoids using excessive substrates and solder balls, can reduce the thickness of the whole packaging structure undoubtedly, and simplifies the whole structure.
Drawings
Fig. 1 is a schematic structural diagram of a first package structure disclosed in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a second package structure disclosed in the embodiment of the present application;
FIGS. 3-5 illustrate steps in the fabrication of the package structure of FIG. 1;
description of reference numerals:
100-substrate, 110-cavity, 120-through-silicon-via, 130-first surface, 140-second surface,
200-first chip module, 210-first chip, 220-second chip, 221-conductive bump, 230-adhesive layer,
300-first redistribution layer, 400-second redistribution layer,
500-second chip module, 600-molding part, 700-electric connection part.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application are capable of operation in sequences other than those illustrated or described herein. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
The technical solutions disclosed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Referring to fig. 1 and fig. 2, an embodiment of a package structure includes a substrate 100, a first chip module 200, a second chip module 500, a first redistribution layer 300, and a second redistribution layer 400.
The substrate 100 is a base member of the package structure, and directly or indirectly provides a mounting support base for other members of the package structure. Specifically, in the present embodiment, the substrate 100 has a cavity 110, the first chip module 200 is disposed in the cavity 110, and the cavity 110 provides an accommodation space for the first chip module 200. In the present embodiment, the shape of the cavity 110 may be various, such as a circle, a rectangle, a square, etc., and the present embodiment is not limited thereto; since the chip structure is usually rectangular or square, the cavity 110 may be a rectangular or square cavity, and when the first chip module 200 includes a wafer structure, a circular cavity may be used to adapt to the shape of the wafer structure; by adopting the above-mentioned adaptive arrangement, the space utilization and compactness of the substrate 100 can be certainly improved.
In the present embodiment, the substrate 100 may be made of various types of materials, such as germanium, silicon carbide, gallium nitride, etc., and of course, the substrate 100 is usually selected as a silicon substrate because silicon is stable in property, easy to purify, large in storage capacity, and easy to obtain.
The substrate 100 has a first surface 130 and a second surface 140 opposite to each other, and the cavity 110 may be opened on the first surface 130 of the substrate 100, that is, the cavity 110 penetrates through the first surface 130. It is understood that the first surface 130 may be any end surface of the substrate 100.
The first redistribution layer 300 and the second redistribution layer 400 are connection mounting members of the package structure. It should be noted that, in the production process of the chip structure, the I/O interface (usually, a pad) is small, which is not convenient for electrical connection, and the structure of the chip structure itself is also not convenient for fixed installation; in this embodiment, the first redistribution layer 300 and the second redistribution layer 400 are used to solve the above-mentioned problems.
Specifically, the first redistribution layer 300 is disposed on the first surface 130 and covers the cavity 110, so that the cavity 110 is sealed, that is, the first chip module 200 is isolated from the outside, and the first chip module 200 can be prevented from being corroded due to impurities entering the cavity 110.
Meanwhile, the second redistribution layer 400 is disposed on the second surface 140, and the second chip module 500 is disposed on the second redistribution layer 400, of course, the second chip module 500 is disposed on a side of the second redistribution layer 400 departing from the substrate 100. In this case, the package structure realizes stacking of a plurality of chip structures (i.e., the first chip module 200 and the second chip module 500), thereby increasing the integration density of the electronic device.
In order to achieve information interaction inside the package structure, the first chip module 200 is electrically connected to at least one of the first redistribution layer 300 and the second redistribution layer 400, that is, the first chip module 200 may be electrically connected to only the first redistribution layer 300, only the second redistribution layer 400, and both the first redistribution layer 300 and the second redistribution layer 400; the second chip module 500 is electrically connected to the second redistribution layer 400.
It should be noted that, the first redistribution layer 300 and the second redistribution layer 400 are both metal conductive layers in nature and have routing areas with larger areas compared to the chip structures, so that the first redistribution layer 300 can radiate the circuit fan-out of the first chip module 200 to a larger area, and a larger I/O interface corresponding to the first chip module 200 can be disposed on the first redistribution layer 300 (of course, in this embodiment, the first chip module 200 can also achieve the above-mentioned effects based on the second redistribution layer 400); the second redistribution layer 400 may radiate the circuit fan-out of the second chip module 500 to a larger area, and a larger I/O interface corresponding to the second chip module 500 may be disposed on the second redistribution layer 400. Thus, based on the first redistribution layer 300 and the second redistribution layer 400, reliable and stable fixed mounting and telecommunication connection of the first chip module 200 and the second chip module 500 can be achieved, and meanwhile, the density of the I/O interface of the packaging structure is improved, so that the mounting is more convenient.
At the same time, the second redistribution layer 400 is electrically connected to the first redistribution layer 300. With this configuration, the second chip module 500 can achieve information interaction with the first redistribution layer 300 through the second redistribution layer 400, and the first chip module 200 can also achieve information interaction with the first redistribution layer 300, so that logic and information arrays in the longitudinal direction of the package structure can be combined. In this embodiment, the electrical connection manner of each component is not limited, and can be realized by providing pins, solder balls, or wire bonding.
As described above, the package structure needs to seal the second chip module 500, as in the first chip module 200. Accordingly, the package structure of the embodiment may further include a mold sealing portion 600, and the mold sealing portion 600 covers the second chip module 500 and the second redistribution layer 400. Specifically, based on the mold sealing part 600, the second chip module 500 is isolated from the outside, and the second chip module 500 can be prevented from being corroded due to contact of impurities. Meanwhile, the mold sealing portion 600 also protects the second redistribution layer 400 when protecting the second chip module 500.
In the present embodiment, the mold seal 600 may be made of silicone material, thermosetting material, thermoplastic material, or UV-treated material. In general, the mold seal 600 may use a thermosetting material, such as silicone, epoxy, polyimide, etc.
In this embodiment, the package structure may be connected to a mounting base on the side of the first redistribution layer 300, where the mounting base may be a main board or a sub-board of the electronic device, so that the package structure can be connected to other electronic components. The first redistribution layer 300 is typically electrically connected to the mounting base through electrical connections 700, which may be solder balls, pins, etc.
It should be noted that, in the present embodiment, the specific types of the first chip module 200 and the second chip module 500 are not limited, and they may be chip structures with the same function type, so that the package structure has stronger computing capability on the same function; the packaging structure can be a chip structure with different function types, so that more functions can be realized by a single packaging structure, and when the packaging structure is applied to electronic equipment, the electronic equipment has more functions.
Of course, the present embodiment also does not limit the specific number of chip structures inside the first chip module 200 and the second chip module 500, and each of them may only include one chip structure, or may include a plurality of chip structures; in the embodiment including a plurality of chip structures, the plurality of chip structures only need to be adaptively stacked in the cavity 110 and the second redistribution layer 400, and adaptive accommodation may also be achieved by changing the size of the chip structures; in the package structure shown in fig. 1, the first chip module 200 includes two chip structures; as shown in fig. 2, the first chip module 200 includes only one chip structure; in the two packaging structures, the second chip module 500 includes two chip structures.
Meanwhile, in the present embodiment, the specific number of the cavities 110 is not limited, that is, the substrate 100 may be provided with a plurality of cavities 110, and the plurality of cavities 110 are respectively provided with the first chip modules 200, so that integration of more chip structures can be realized. Further, in an embodiment to improve the integration of the package structure, the package structure may further include more chip modules, and the chip modules may be disposed on a side of the second chip module 500 away from the second redistribution layer 400 and adaptively disposed according to the inventive concept of the present application.
As can be seen from the above description, in the package structure disclosed in the embodiment of the present disclosure, the first chip module 200 is disposed in the cavity 110 of the substrate 100, the first redistribution layer 300 is disposed on the first surface 130 of the substrate 100, the second redistribution layer 400 is disposed on the second surface 140 of the substrate 100, and the second chip module 500 is disposed on the second redistribution layer 400 and uses the second redistribution layer 400 as a supporting carrier; meanwhile, the first redistribution layer 300 and the second redistribution layer 400 are electrically connected, so that the normal use of the entire package structure can be realized after the first redistribution layer 300 is mounted on a mounting base.
Compared with the prior art, the packaging structure disclosed by the embodiment of the application realizes the stack packaging of the electronic element by embedding the first chip module in the substrate and arranging the second chip module on the second redistribution layer by only utilizing one substrate, avoids using excessive substrates and solder balls, and ensures that the thickness of the whole packaging structure is reduced and the whole structure of the packaging structure is simplified because the thickness of the first redistribution layer 300 and the thickness of the second redistribution layer 400 are smaller.
To further reduce the thickness of the package structure, in an alternative, the cavity 110 penetrates the second surface 140, and the second redistribution layer 400 covers the cavity 110. It should be understood that, with such an arrangement, the first chip module 200 may be exposed to the side of the substrate 100 close to the second redistribution layer 400 through the cavity 110, and the size of the cavity 110 is certainly reduced under the condition that the size of the first chip module 200 is not changed, that is, the substrate 100 is thinned in the thickness direction thereof, so as to achieve the thickness reduction of the whole package structure.
As described above, in the present embodiment, the specific number of chip structures inside the first chip module 200 is not limited. Taking the example that the first chip module 200 includes two chip structures, the first chip module 200 may include a first chip 210 and a second chip 220 stacked on each other, the first chip 210 faces the first redistribution layer 300 and is electrically connected to the first redistribution layer 300, and the second chip 220 faces the second redistribution layer 400 and is electrically connected to the second redistribution layer 400. Specifically, with such a configuration, the information transmission paths of the first chip 210 and the second chip 220 can be conveniently shortened, and higher information interaction efficiency can be achieved at lower cost; at the same time, the processing operations are also facilitated when the electrical connection of the first chip 210 to the first redistribution layer 300 and the electrical connection of the second chip 220 to the second redistribution layer 400 are achieved.
Generally, the first chip 210 and the second chip 220 may be fixedly connected by the adhesive layer 230, and the adhesive layer 230 may specifically be a die attach film. Based on the adhesive layer 230, the first chip 210 and the second chip 220 can have certain integrity, and are convenient to mount and fix; meanwhile, even when the first chip 210 and the second chip 220 are pressed, the adhesive layer 230 acts as a flexible action on the first chip 210 and the second chip 220, and damage to the first chip 210 and the second chip 220 can be avoided.
In combination with the above, in order to further thin the package structure, the cavity 110 may be disposed to penetrate through the substrate 100, and in order to realize the above technical features, the thinning may be performed on the second surface 140 of the substrate 100; in the thinning process, there is a risk of damaging the second chip 220 due to the contact, and in an alternative, the second chip 220 may be provided with conductive bumps 221 at an end surface facing the second redistribution layer 400, and the second chip 220 is electrically connected to the second redistribution layer 400 through the conductive bumps 221.
It should be understood that, since the end surface of the second chip 220 facing the second redistribution layer 400 is provided with the conductive bump 221, when the second surface 140 of the substrate 100 is thinned, even if the second surface is thinned into the cavity 110, the conductive bump 221 can prevent the second chip 220 from being thinned, which is equivalent to protecting the second chip 220 and can prompt an operator to thin the substrate 100 in place immediately; meanwhile, the conductive bumps 221 further have conductive performance, so that the second chip 220 can be electrically connected to the second redistribution layer 400 conveniently; moreover, since the conductive bumps 211 are spaced, the air flow space can be increased, and the heat dissipation efficiency inside the package structure can be improved.
In order to ensure reliable connection between the second chip 220 and the second redistribution layer 400, in an alternative, the conductive bumps 221 may be multiple, and the conductive bumps 221 are uniformly distributed on the second chip 220. It should be understood that, since the conductive bumps 221 are multiple, that is, multiple points are established between the second chip 220 and the second redistribution layer 400, which is equivalent to the second chip 220 having multiple supporting points on the second redistribution layer 400, so that the connection stability between the two can be improved.
Further, the molding material may be filled in the gap of the cavity 110 outside the first chip module 200, so as to avoid the situations of dislocation, movement and the like of the first chip module 200, and further improve the mounting stability.
In combination with the above, in the present embodiment, an electrical connection relationship needs to be established between the first redistribution layer 300 and the second redistribution layer 400, and the thickness direction of the package structure is inevitably increased by performing the electrical connection in the stack package in a conventional manner (e.g., wire bonding, solder ball, etc.). In this regard, in an alternative embodiment, the substrate 100 is formed with through silicon vias 120, and the first redistribution layer 300 is electrically connected to the second redistribution layer 400 through the through silicon vias 120.
In order to make the through-silicon via 120 conductive, it is usually necessary to fill the through-silicon via 120 with a conductive material, such as copper, polysilicon, tungsten, and the like. Specifically, since the through-silicon via 120 is embedded in the substrate 100, the first redistribution layer 300 and the second redistribution layer 400 can be electrically connected across the substrate 100 only by electrically connecting the first redistribution layer 300 and the second redistribution layer 400 with the through-silicon via 120, respectively. Based on the embodiment of the through silicon via 120, the package structure can avoid using a conventional electrical connection structure, and further can improve the space utilization thereof, and secondly, the through silicon via 120 can shorten the information transmission path between the first redistribution layer 300 and the second redistribution layer 400, and further improve the information interaction efficiency of the package structure.
Based on the foregoing package structure, an embodiment of the application further discloses an electronic device, where the disclosed electronic device includes the foregoing package structure. The electronic device disclosed by the embodiment of the application can be a smart phone, a tablet computer, an electronic book reader, a wearable device and other devices, and the embodiment of the application does not limit the specific type of the electronic device.
The embodiment of the application also discloses a manufacturing method of the packaging structure, and the disclosed manufacturing method can comprise the following steps:
step S100: a substrate 100 is provided and a cavity 110 is formed in a first surface 130 of the substrate 100. In the present embodiment, the specific manner of constructing the cavity 110 is various, for example, by CNC machining process, molding process, etc.
Step S200: a first chip module 200 is provided, and the first chip module 200 is disposed in the cavity 110.
In a case of matching with the foregoing embodiment, step S200 may include:
step S210: providing a second chip 220, constructing a conductive bump 221 on an end face of the second chip 220 facing the inside of the cavity 110, and disposing the second chip 220 in the cavity 110;
step S220: providing a first chip 210, and adhering the first chip 210 to an end face of the second chip 220 facing out of the cavity 110;
step S230: an encapsulation molding material is provided and the cavity 110 is filled with the encapsulation molding material.
Step S300: the first redistribution layer 300 is stacked and assembled on the first surface 130 of the substrate 100, and the first redistribution layer 300 covers the cavity 110. Step S300 specifically further includes electrically connecting the first chip 210 with the first redistribution layer 300.
Step S400: a second redistribution layer 400 is stacked and assembled on the second surface 140 of the substrate 100, and the second redistribution layer 400 is electrically connected to the first redistribution layer 300.
In a case of matching with the foregoing embodiment, step S400 may include:
step S410: a thinning process is performed on the second surface 140 of the substrate 100 so that the cavity 110 penetrates the substrate. Thus, the first chip module 200 is exposed out of the substrate 100. In this embodiment, the specific type of the thinning process is not limited, and the thinning may be generally achieved by a mechanical grinding process, or may be achieved by chemical etching, mechanical glass, thermal baking, ultraviolet irradiation, laser ablation, chemical mechanical polishing, or wet stripping.
Step S420: through-silicon-vias 120 are formed in the substrate 100, it being understood that the through-silicon-vias 120 extend through the substrate 100, i.e., from the first surface 130 to the second surface 140 of the substrate 100;
the second redistribution layer 400 is stacked and assembled on the second surface 140 of the thinned substrate 100, and the second redistribution layer 400 is electrically connected to the first redistribution layer 300 through the through-silicon vias 120. Step S420 may further include electrically connecting the second chip 220 to the second redistribution layer 400. More specifically, the second chip 220 is electrically connected to the second redistribution layer 400 through the conductive bump 221.
Step S500: a second chip module 500 is provided, and the second chip module 500 is disposed on the second redistribution layer 400. Step S500 may further include electrically connecting the second chip module 500 to the second redistribution layer 400. Step S500 may further include providing an encapsulation molding material, and constructing a mold 600 covering the second chip module 500 and the second redistribution layer 400 using the encapsulation molding material.
Of course, in the present embodiment, there are various methods for constructing the mold seal 600, such as compression molding, printing, transfer molding, liquid seal molding, vacuum bonding, and spin coating.
The manufacturing method of the package structure may further include step S600: an electrical connection 700 is constructed at a side of the first redistribution layer 300 facing away from the substrate 100. In practical use, the mounting base can be installed and connected through the electrical connection portion 700.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A package structure, comprising:
a substrate (100), wherein the substrate (100) has a first surface (130), a second surface (140) and a cavity (110), the first surface (130) and the second surface (140) are oppositely arranged, and the cavity (110) penetrates through the first surface (130);
a first chip module (200), wherein the first chip module (200) is arranged in the cavity (110);
a first redistribution layer (300), the first redistribution layer (300) disposed on the first surface (130) and covering the cavity (110);
a second redistribution layer (400), the second redistribution layer (400) disposed on the second surface (140) and electrically connected with the first redistribution layer (300);
a second chip module (500), the second chip module (500) disposed on the second redistribution layer (400);
wherein the first chip module (200) is electrically connected to at least one of the first redistribution layer (300) and the second redistribution layer (400), and the second chip module (500) is electrically connected to the second redistribution layer (400).
2. The encapsulation structure of claim 1, wherein the cavity (110) extends through the second surface (140), and wherein the second redistribution layer (400) covers the cavity (110).
3. The package structure of claim 2, wherein the first chip module (200) comprises a first chip (210) and a second chip (220) stacked, the first chip (210) facing the first redistribution layer (300) and electrically connected to the first redistribution layer (300), the second chip (220) facing the second redistribution layer (400) and electrically connected to the second redistribution layer (400).
4. The package structure according to claim 3, wherein the first chip (210) and the second chip (220) are fixedly connected by an adhesive layer (230).
5. The encapsulation structure according to claim 3, wherein the second chip (220) is provided with conductive bumps (221) at an end surface facing the second redistribution layer (400), and the second chip (220) is electrically connected to the second redistribution layer (400) through the conductive bumps (221).
6. The package structure of claim 5, wherein the conductive bumps (221) are plural, and the plural conductive bumps (221) are uniformly distributed on the second chip (220).
7. The package structure of claim 1, wherein the substrate (100) has a through-silicon via (120) formed thereon, and the first redistribution layer (300) is electrically connected to the second redistribution layer (400) through the through-silicon via (120).
8. The package structure according to claim 1, wherein the substrate (100) is a silicon substrate.
9. An electronic device, characterized in that it comprises a package structure according to any one of claims 1 to 8.
10. A method for manufacturing a package structure includes:
providing a substrate (100), and constructing a cavity (110) on a first surface (130) of the substrate (100);
providing a first chip module (200), and arranging the first chip module (200) in the cavity (110);
laminating a first redistribution layer (300) on the first surface (130) of the substrate (100) and covering the cavity (110) with the first redistribution layer (300);
laminating a second redistribution layer (400) on the second surface (140) of the substrate (100) and electrically connecting the second redistribution layer (400) to the first redistribution layer (300);
providing a second chip module (500), and disposing the second chip module (500) on the second redistribution layer (400).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011001467.XA CN112151457A (en) | 2020-09-22 | 2020-09-22 | Packaging structure, manufacturing method thereof and electronic equipment |
| PCT/CN2021/119248 WO2022063069A1 (en) | 2020-09-22 | 2021-09-18 | Packaging structure and manufacturing method therefor, and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011001467.XA CN112151457A (en) | 2020-09-22 | 2020-09-22 | Packaging structure, manufacturing method thereof and electronic equipment |
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| CN112151457A true CN112151457A (en) | 2020-12-29 |
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| CN202011001467.XA Pending CN112151457A (en) | 2020-09-22 | 2020-09-22 | Packaging structure, manufacturing method thereof and electronic equipment |
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| WO (1) | WO2022063069A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022063069A1 (en) * | 2020-09-22 | 2022-03-31 | 维沃移动通信有限公司 | Packaging structure and manufacturing method therefor, and electronic device |
| WO2024125547A1 (en) * | 2022-12-16 | 2024-06-20 | 维沃移动通信有限公司 | Packaging structure, electronic device and packaging method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040140533A1 (en) * | 2002-11-06 | 2004-07-22 | Stern Jonathan Michael | Method for creating neo-wafers from singulated integrated circuit die and a device made according to the method |
| US20090127686A1 (en) * | 2007-11-21 | 2009-05-21 | Advanced Chip Engineering Technology Inc. | Stacking die package structure for semiconductor devices and method of the same |
| CN105575913A (en) * | 2016-02-23 | 2016-05-11 | 华天科技（昆山）电子有限公司 | Fan-out type 3D packaging structure embedded in silicon substrate |
| CN105990159A (en) * | 2014-12-02 | 2016-10-05 | 旭德科技股份有限公司 | Packaging structure and manufacturing method thereof |
| CN109427759A (en) * | 2017-08-29 | 2019-03-05 | 华为技术有限公司 | A kind of chip-packaging structure and preparation method thereof, electronic equipment |
| CN110299329A (en) * | 2018-03-21 | 2019-10-01 | 华为技术有限公司 | A kind of encapsulating structure and preparation method thereof, electronic equipment |
| CN110634838A (en) * | 2019-08-29 | 2019-12-31 | 上海先方半导体有限公司 | Ultrathin fan-out type packaging structure and manufacturing method thereof |
| CN111613585A (en) * | 2020-05-28 | 2020-09-01 | 华进半导体封装先导技术研发中心有限公司 | Chip packaging structure and method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3522571B2 (en) * | 1999-03-05 | 2004-04-26 | 日本特殊陶業株式会社 | Wiring board |
| TW533758B (en) * | 2000-07-31 | 2003-05-21 | Ngk Spark Plug Co | Printed wiring substrate and method for manufacturing the same |
| KR102108087B1 (en) * | 2013-07-11 | 2020-05-08 | 삼성전자주식회사 | Semiconductor Packages |
| KR20200062666A (en) * | 2018-11-27 | 2020-06-04 | 삼성전자주식회사 | Semiconductor package |
| CN110211888A (en) * | 2019-06-14 | 2019-09-06 | 上海先方半导体有限公司 | A kind of embedded fan-out packaging structure and its manufacturing method |
| CN112151457A (en) * | 2020-09-22 | 2020-12-29 | 维沃移动通信有限公司 | Packaging structure, manufacturing method thereof and electronic equipment |
-
2020
- 2020-09-22 CN CN202011001467.XA patent/CN112151457A/en active Pending
-
2021
- 2021-09-18 WO PCT/CN2021/119248 patent/WO2022063069A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040140533A1 (en) * | 2002-11-06 | 2004-07-22 | Stern Jonathan Michael | Method for creating neo-wafers from singulated integrated circuit die and a device made according to the method |
| US20090127686A1 (en) * | 2007-11-21 | 2009-05-21 | Advanced Chip Engineering Technology Inc. | Stacking die package structure for semiconductor devices and method of the same |
| CN105990159A (en) * | 2014-12-02 | 2016-10-05 | 旭德科技股份有限公司 | Packaging structure and manufacturing method thereof |
| CN105575913A (en) * | 2016-02-23 | 2016-05-11 | 华天科技（昆山）电子有限公司 | Fan-out type 3D packaging structure embedded in silicon substrate |
| CN109427759A (en) * | 2017-08-29 | 2019-03-05 | 华为技术有限公司 | A kind of chip-packaging structure and preparation method thereof, electronic equipment |
| CN110299329A (en) * | 2018-03-21 | 2019-10-01 | 华为技术有限公司 | A kind of encapsulating structure and preparation method thereof, electronic equipment |
| CN110634838A (en) * | 2019-08-29 | 2019-12-31 | 上海先方半导体有限公司 | Ultrathin fan-out type packaging structure and manufacturing method thereof |
| CN111613585A (en) * | 2020-05-28 | 2020-09-01 | 华进半导体封装先导技术研发中心有限公司 | Chip packaging structure and method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022063069A1 (en) * | 2020-09-22 | 2022-03-31 | 维沃移动通信有限公司 | Packaging structure and manufacturing method therefor, and electronic device |
| WO2024125547A1 (en) * | 2022-12-16 | 2024-06-20 | 维沃移动通信有限公司 | Packaging structure, electronic device and packaging method |
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| Publication number | Publication date |
|---|---|
| WO2022063069A1 (en) | 2022-03-31 |
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