WO2022063069A1

WO2022063069A1 - Packaging structure and manufacturing method therefor, and electronic device

Info

Publication number: WO2022063069A1
Application number: PCT/CN2021/119248
Authority: WO
Inventors: 杨望来
Original assignee: 维沃移动通信有限公司
Priority date: 2020-09-22
Filing date: 2021-09-18
Publication date: 2022-03-31
Also published as: CN112151457A

Abstract

Disclosed in the present application are a packaging structure and a manufacturing method therefor, and an electronic device. The disclosed packaging structure comprises a substrate, a first chip module, a second chip module, a first redistribution layer, and a second redistribution layer; the substrate has a first surface and a second surface that face away from each other and a cavity, the first surface and the second surface are arranged facing away from each other, and the cavity penetrates the first surface; the first chip module is arranged in the cavity; the first redistribution layer is arranged on the first surface and covers the cavity; the second redistribution layer is arranged on the second surface and electrically connected to the first redistribution layer; the second chip module is arranged on the second redistribution layer; and the first chip module is electrically connected to at least one of the first redistribution layer and the second redistribution layer, and the second chip module is electrically connected to the second redistribution layer.

Description

Package structure and its manufacturing method and electronic device

This application claims the priority of the Chinese patent application with the application number 202011001467.X and the invention title "Package structure and its manufacturing method and electronic device" filed in the China Patent Office on September 22, 2020. The entire content of the application is approved by Reference is incorporated in this application.

technical field

The application belongs to the technical field of semiconductor packaging, and in particular relates to a packaging structure, a manufacturing method thereof, and an electronic device.

Background technique

With the advancement of science and technology, higher requirements have also been placed on the miniaturized size characteristics of electronic components on the basis of improving the functional performance of electronic components. At present, it is usually achieved by increasing the integration density of electronic components. (Package on Package, POP) is a commonly used method to improve the integration density of electronic components.

In the POP package structure, the chips are packaged between two substrates, and the different substrates need to be electrically connected and fixed by solder balls. Therefore, there will be multi-layer substrates and multi-layer solder balls in the thickness direction of the package structure. This will lead to a larger thickness and size of the entire package structure, which is not conducive to the thin and light design of electronic devices; the above-mentioned problems are more prominent when the chip itself has an excessively high capacity.

SUMMARY OF THE INVENTION

The purpose of the embodiments of the present application is to provide a package structure, a manufacturing method thereof, and an electronic device, which can solve the problem of large thickness and size of the current package structure.

In order to solve the above technical problems, this application is implemented as follows:

In a first aspect, an embodiment of the present application provides a package structure, and the package structure includes:

a substrate, the substrate has a first surface, a second surface and a cavity, the first surface and the second surface are arranged opposite to each other, and the cavity penetrates the first surface;

a first chip module, the first chip module is disposed in the cavity;

a first redistribution layer, the first redistribution layer is disposed on the first surface and covers the cavity;

a second redistribution layer, the second redistribution layer is disposed on the second surface and is electrically connected to the first redistribution layer;

a second chip module, the second chip module is disposed on the second redistribution layer;

Wherein, the first chip module is electrically connected to at least one of the first redistribution layer and the second redistribution layer, and the second chip module is electrically connected to the second redistribution layer.

In a second aspect, an embodiment of the present application provides an electronic device including the aforementioned packaging structure.

In a third aspect, an embodiment of the present application provides a method for fabricating a package structure, including:

providing a substrate with a cavity formed in a first surface of the substrate;

providing a first chip module, and placing the first chip module in the cavity;

A first redistribution layer is stacked and combined on the first surface of the substrate, and the cavity is covered by the first redistribution layer;

Laminate and combine a second redistribution layer on the second surface of the substrate, and electrically connect the second redistribution layer to the first redistribution layer;

A second chip module is provided, and the second chip module is placed on the second redistribution layer.

In the package structure disclosed in the embodiments of the present application, the first chip module is disposed in the cavity of the substrate, the first surface of the substrate is disposed with the first redistribution layer, and the second surface of the substrate is disposed with the second redistribution layer, The second chip module is disposed on the second redistribution layer and the second redistribution layer is used as a carrier; at the same time, the first redistribution layer and the second redistribution layer are electrically connected, so the first redistribution layer is installed in the installation After the foundation, the normal use of the entire package structure can be realized.

Compared with the prior art, in the package structure disclosed in the embodiments of the present application, by embedding the first chip module in the substrate and disposing the second chip module in the second redistribution layer, the electronic module can be realized by using only one substrate. The stacking package of components avoids the use of too many substrates and solder balls, which can undoubtedly reduce the thickness of the entire package structure and simplify the overall structure.

Description of drawings

FIG. 1 is a schematic structural diagram of a first packaging structure disclosed in an embodiment of the present application;

2 is a schematic structural diagram of a second packaging structure disclosed in an embodiment of the present application;

3 to 5 show the steps of manufacturing the package structure in FIG. 1 .

Description of reference numbers:

100-substrate, 110-cavity, 120-via silicon, 130-first surface, 140-second surface,

200-first chip module, 210-first chip, 220-second chip, 221-conductive bump, 230-adhesive layer,

300-first redistribution layer, 400-second redistribution layer,

500-second chip module, 600-molding part, 700-electrical connection part.

detailed description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

The terms "first", "second" and the like in the description and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It is to be understood that data so used may be interchanged under appropriate circumstances so that embodiments of the application can be practiced in sequences other than those illustrated or described herein. In addition, "and/or" in the description and claims indicates at least one of the connected objects, and the character "/" generally indicates that the associated objects are in an "or" relationship.

The technical solutions disclosed in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Please refer to FIG. 1 and FIG. 2 , an embodiment of the present application discloses a package structure. The disclosed package structure includes a substrate 100 , a first chip module 200 , a second chip module 500 , a first redistribution layer 300 and a second Redistribution layer 400 .

The substrate 100 is the basic component of the package structure, which directly or indirectly provides a mounting support foundation for other components of the package structure. Specifically, in this embodiment, a cavity 110 is formed on the substrate 100 , the first chip module 200 is disposed in the cavity 110 , and the cavity 110 provides an accommodation space for the first chip module 200 . In this embodiment, the cavity 110 may have various shapes, such as circular, rectangular, square, etc., which are not limited in this embodiment; since the chip structure is generally rectangular or square, the cavity 110 can be selected as A rectangular or square cavity, of course, when the first chip module 200 includes a wafer structure, a circular cavity can be selected to suit its shape; the above-mentioned adaptation arrangement can undoubtedly improve the space utilization and compactness of the substrate 100 sex.

In this embodiment, the material types of the substrate 100 can be various, such as germanium, silicon carbide, gallium nitride, etc. Of course, the substrate 100 is usually selected as a silicon substrate, because silicon is stable in properties, easy to purify, and has a huge storage capacity. more accessible.

The substrate 100 has a first surface 130 and a second surface 140 disposed opposite to each other. The aforementioned cavity 110 may be opened on the first surface 130 of the substrate 100 , that is, the cavity 110 penetrates through the first surface 130 . It should be understood that the first surface 130 may be any end surface of the substrate 100 .

The first redistribution layer 300 and the second redistribution layer 400 are connection mounting members of the package structure. It should be noted that, in the production process of the chip structure, its I/O interface (usually a pad) is small, which is inconvenient to realize electrical connection, and the structure of the chip structure itself is also inconvenient to realize fixed installation; in this embodiment , the first redistribution layer 300 and the second redistribution layer 400 are used to solve the above problems.

Specifically, the first redistribution layer 300 is disposed on the first surface 130 and covers the cavity 110, so that the cavity 110 is sealed, that is, the first chip module 200 is isolated from the outside world, and impurities can be prevented Enter into the cavity 110 and cause corrosion to the first chip module 200 .

Meanwhile, the second redistribution layer 400 is disposed on the second surface 140 , the second chip module 500 is disposed on the second redistribution layer 400 , and of course, the second chip module 500 is disposed on the second redistribution layer 400 away from the substrate 100 . side. In this case, the package structure realizes the stacking of multiple chip structures (ie, the first chip module 200 and the second chip module 500 ), thereby improving the integration density of electronic components.

In order to realize the information exchange inside the package structure, the first chip module 200 is electrically connected to at least one of the first redistribution layer 300 and the second redistribution layer 400 , that is, the first chip module 200 may only be connected to the first redistribution layer 300 and the second redistribution layer 400 . The first redistribution layer 300 can be electrically connected to the second redistribution layer 400 only, and can also be electrically connected to the first redistribution layer 300 and the second redistribution layer 400 at the same time; the second chip module 500 is electrically connected to the second redistribution layer 400. The two redistribution layers 400 are electrically connected.

It should be noted that, the first redistribution layer 300 and the second redistribution layer 400 are both metal conductive layers in essence, and have a larger area than the chip structure. Therefore, through the first redistribution layer 300 The circuit fan-out of the first chip module 200 can be radiated to a larger area, and a larger I/O interface corresponding to the first chip module 200 can be provided on the first redistribution layer 300 (of course, in the In this embodiment, the first chip module 200 can also achieve the above effects based on the second redistribution layer 400 ); the circuit fan-out of the second chip module 500 can be radiated to a larger area through the second redistribution layer 400 , and a larger I/O interface corresponding to the second chip module 500 can be disposed on the second redistribution layer 400 . In this way, based on the first redistribution layer 300 and the second redistribution layer 400 , the reliable and stable fixed installation and telecommunication connection of the first chip module 200 and the second chip module 500 can be realized, and the packaging is also improved. The I/O interface density of the structure makes the installation more convenient.

At the same time, the second redistribution layer 400 is electrically connected to the first redistribution layer 300 . Under this setting, the second chip module 500 can realize information interaction with the first redistribution layer 300 through the second redistribution layer 400 , and at the same time, the first chip module 200 can also realize information interaction with the first redistribution layer 300 , so the logic and information arrays in the longitudinal direction of the package structure can be combined. In this embodiment, there is no restriction on the electrical connection manner of each component, which can usually be realized by setting pins, solder balls, or bonding wires.

As mentioned above, like the first chip module 200 , the package structure needs to seal the second chip module 500 . Based on this, the package structure of this embodiment may further include a molding part 600 , and the molding part 600 covers the second chip module 500 and the second redistribution layer 400 . Specifically, based on the mold sealing portion 600 , the second chip module 500 is isolated from the outside world, which can prevent impurities from contacting the second chip module 500 and causing corrosion. At the same time, when the mold sealing part 600 protects the second chip module 500 , it also plays a protective role for the second redistribution layer 400 .

In this embodiment, the molding part 600 may be made of a silicone-based material, a thermosetting material, a thermoplastic material, or a UV-treated material. Generally, the molding part 600 can be made of a thermosetting material, such as silica gel, epoxy resin, polyimide, and the like.

In this embodiment, the package structure can be connected to the installation base on the side of the first redistribution layer 300, and the installation base can be a main board or a sub-board of an electronic device. In this way, the package structure can be connected to other Electronic components make connections. The first redistribution layer 300 is usually electrically connected to the mounting base through electrical connection parts 700 , which may be solder balls, pins, or the like.

It should be noted that, in this embodiment, the specific types of the first chip module 200 and the second chip module 500 are not limited, and they can be chip structures of the same functional type, so that the package structure can have the same function. They have more powerful computing power; they can also be chip structures of different functional types, so that a single package structure can achieve more functions. When applied to electronic devices, it is reflected that the electronic devices have more functions. .

Of course, this embodiment does not limit the specific number of chip structures inside the first chip module 200 and the second chip module 500, and they may include only one chip structure or multiple chip structures; In the implementation of multiple chip structures, it is only necessary to adaptively stack multiple chip structures in the cavity 110 and the second redistribution layer 400, and the adaptive accommodation can also be realized by changing the size of the chip structures; for example, In the package structure shown in FIG. 1 , the first chip module 200 includes two chip structures; in the package structure shown in FIG. 2 , the first chip module 200 only includes one chip structure; and the above two packages In the structure, each of the second chip modules 500 includes two chip structures.

Meanwhile, in this embodiment, the specific number of the cavities 110 is not limited, that is, a plurality of cavities 110 can be opened on the substrate 100, and the first chip modules 200 are respectively arranged in the plurality of cavities 110, This enables the integration of more chip structures. Further, in order to improve the integration degree of the package structure, the package structure may further include more chip modules, and these part of the chip modules may be disposed on the second chip module 500 away from the second redistribution layer 400 side, and can be set adaptively through the inventive concept of the present application.

As can be seen from the above description, in the package structure disclosed in the embodiments of the present application, the first chip module 200 is disposed in the cavity 110 of the substrate 100 , the first redistribution layer 300 is disposed on the first surface 130 of the substrate 100 , and the substrate 100 The second surface 140 of the chip is provided with a second redistribution layer 400, the second chip module 500 is disposed on the second redistribution layer 400 and the second redistribution layer 400 is used as a supporting carrier; at the same time, the first redistribution layer 300 and The second redistribution layer 400 is electrically connected, so after the first redistribution layer 300 is installed on the mounting base, the entire package structure can be used normally.

Compared with the prior art, in the package structure disclosed in the embodiments of the present application, by embedding the first chip module in the substrate and disposing the second chip module in the second redistribution layer, the electronic module can be realized by using only one substrate. The stacking package of components avoids the use of too many substrates and solder balls, and at the same time, the thicknesses of the first redistribution layer 300 and the second redistribution layer 400 are both small, which can undoubtedly reduce the thickness of the entire package structure and reduce the size of the package. The overall structure of the package structure is simplified.

In order to further reduce the thickness of the package structure, in an optional solution, the cavity 110 penetrates through the second surface 140 , and the second redistribution layer 400 covers the cavity 110 . It should be understood that, under this arrangement, the first chip module 200 can be exposed to the side of the substrate 100 close to the second redistribution layer 400 through the cavity 110 , and the size of the first chip module 200 is kept unchanged. Therefore, the size of the cavity 110 can undoubtedly be reduced, that is, the substrate 100 can be thinned in the thickness direction thereof, thereby realizing the thinning of the overall thickness of the package structure.

As mentioned above, in this embodiment, the specific number of chip structures inside the first chip module 200 is not limited. Taking the first chip module 200 including two chip structures as an example, the first chip module 200 may include a first chip 210 and a second chip 220 that are stacked and arranged. The first chip 210 faces the first redistribution layer 300 and is connected to the first redistribution layer 300 . The first redistribution layer 300 is electrically connected, and the second chip 220 faces the second redistribution layer 400 and is electrically connected to the second redistribution layer 400 . Specifically, under such a setting, the information transmission path between the first chip 210 and the second chip 220 can undoubtedly be shortened, and a higher information exchange efficiency can be achieved at a lower cost; The electrical connection of the first redistribution layer 300 and the electrical connection of the second chip 220 to the second redistribution layer 400 also facilitates processing operations.

Normally, the first chip 210 and the second chip 220 can be fixedly connected through an adhesive layer 230, and the adhesive layer 230 can be specifically a die-bonding film. Based on the adhesive layer 230, the first chip 210 and the second chip 220 can have a certain integrity, which is convenient for installation and fixation; at the same time, even when the first chip 210 and the second chip 220 are pressed, the The first chip 210 and the second chip 220 function as flexibility, which can avoid damage to the first chip 210 and the second chip 220 .

In combination with the foregoing, in order to further thin the package structure, the cavity 110 may be arranged to penetrate through the substrate 100, and in order to achieve the above-mentioned technical features, the second surface 140 of the substrate 100 may be thinned by technical means; during the thinning process , due to the risk of damage to the second chip 220 due to contact, in an optional solution, the second chip 220 may be provided with conductive bumps 221 on the end face facing the second redistribution layer 400, and the second chip 220 passes through the conductive bumps 221 is electrically connected to the second redistribution layer 400 .

It should be understood that since the end surface of the second chip 220 facing the second redistribution layer 400 is provided with the conductive bumps 221 , when the second surface 140 of the substrate 100 is thinned, even if it is thinned into the cavity 110 , The conductive bumps 221 can prevent the thinning of the second chip 220, which is equivalent to protecting the second chip 220, and can instantly remind the operator that the thinning is in place, and the operator can stop thinning the substrate 100 again. At the same time, the conductive bumps 221 also have electrical conductivity, which can easily realize the electrical connection between the second chip 220 and the second redistribution layer 400; moreover, because the conductive bumps 211 play a role of spacing, it can also increase the air flow space , to improve the heat dissipation efficiency inside the package structure.

In order to ensure reliable connection between the second chip 220 and the second redistribution layer 400 , in an optional solution, there may be multiple conductive bumps 221 , and the plurality of conductive bumps 221 are evenly distributed on the second chip 220 . It should be understood that since there are multiple conductive bumps 221 , multi-point connections are established between the second chip 220 and the second redistribution layer 400 , which is equivalent to that the second chip 220 is on the second redistribution layer 400 With multiple support points, the connection stability between the two can be improved.

Further, the gap of the cavity 110 outside the first chip module 200 can be filled with molding material to prevent the first chip module 200 from being displaced or moved, thereby improving the installation stability.

In combination with the foregoing, in this embodiment, an electrical connection relationship needs to be established between the first redistribution layer 300 and the second redistribution layer 400 , and in the stacked package, the thickness direction is carried out by conventional methods (eg, wire bonding, solder balls, etc.). The electrical connection on the package structure will undoubtedly increase the thickness and size of the package structure. Based on this, in an optional solution, through silicon vias 120 are formed on the substrate 100 , and the first redistribution layer 300 is electrically connected to the second redistribution layer 400 through the silicon vias 120 .

It should be noted that, in order to make the TSV 120 have electrical conductivity, it is usually necessary to fill the TSV 120 with a conductive material, such as copper, polysilicon, tungsten and other substances. Specifically, since the TSV 120 is embedded in the substrate 100 , the first redistribution layer 300 and the second redistribution layer 400 only need to be electrically connected to the TSV 120 , respectively, to ensure that the first redistribution layer 300 and the second redistribution layer 400 are electrically connected to the TSV 120 respectively. The second redistribution layer 400 implements an electrical connection relationship across the substrate 100 . Based on the TSV 120 implementation, the package structure can avoid using a traditional electrical connection structure, thereby improving its space utilization. Secondly, the TSV 120 can shorten the gap between the first redistribution layer 300 and the second redistribution layer 400 the information transmission path, thereby improving the information exchange efficiency of the packaging structure.

Based on the aforementioned packaging structure, an embodiment of the present application further discloses an electronic device, and the disclosed electronic device includes the aforementioned packaging structure. The electronic devices disclosed in the embodiments of the present application may be devices such as smart phones, tablet computers, e-book readers, and wearable devices, and the embodiments of the present application do not limit the specific types of electronic devices.

The embodiment of the present application also discloses a manufacturing method of a package structure, and the disclosed manufacturing method may include:

Step S100 : the substrate 100 is provided, and the cavity 110 is formed on the first surface 130 of the substrate 100 . In this embodiment, there are various specific ways to construct the cavity 110 , for example, through CNC processing, molding processing, and the like.

Step S200 : providing the first chip module 200 , and disposing the first chip module 200 in the cavity 110 .

In the case of matching with the foregoing embodiments, step S200 may include:

Step S210 : providing the second chip 220 , constructing conductive bumps 221 on the end surface of the second chip 220 facing the cavity 110 , and disposing the second chip 220 in the cavity 110 ;

Step S220 : providing the first chip 210 and bonding the first chip 210 to the end surface of the second chip 220 facing outside the cavity 110 ;

Step S230: Provide an encapsulation molding material, and fill the cavity 110 with the encapsulation molding material.

Step S300 : stacking and combining the first redistribution layer 300 on the first surface 130 of the substrate 100 , and covering the cavity 110 with the first redistribution layer 300 . Step S300 specifically further includes electrically connecting the first chip 210 with the first redistribution layer 300 .

Step S400 : stacking and combining the second redistribution layer 400 on the second surface 140 of the substrate 100 , and electrically connecting the second redistribution layer 400 and the first redistribution layer 300 .

In the case of matching with the foregoing embodiments, step S400 may include:

Step S410 : performing a thinning process on the second surface 140 of the substrate 100 so that the cavity 110 penetrates through the substrate. In this way, the first chip module 200 is exposed outside the substrate 100 . In this embodiment, the specific type of the thinning process is not limited. Generally, the thinning can be achieved by a mechanical grinding process, and of course, it can also be achieved by chemical etching, mechanical glass, thermal baking, ultraviolet light irradiation, and laser ablation. , chemical mechanical polishing or wet peeling to achieve thinning.

Step S420 : constructing through silicon vias 120 on the substrate 100 , it should be understood that the silicon vias 120 should penetrate through the substrate 100 , that is, from the first surface 130 of the substrate 100 to the second surface 140 ;

The second redistribution layer 400 is stacked and assembled on the second surface 140 of the thinned substrate 100 , and the second redistribution layer 400 is electrically connected to the first redistribution layer 300 through the TSV 120 . Step S420 specifically further includes electrically connecting the second chip 220 with the second redistribution layer 400 . More specifically, the second chip 220 is electrically connected to the second redistribution layer 400 through the conductive bumps 221 .

Step S500 : providing the second chip module 500 , and disposing the second chip module 500 on the second redistribution layer 400 . Step S500 specifically further includes electrically connecting the second chip module 500 and the second redistribution layer 400 . Step S500 may further include providing an encapsulation molding material, and using the encapsulation molding material to construct the molding part 600 covering the second chip module 500 and the second redistribution layer 400 .

Of course, in this embodiment, there are various methods for constructing the mold sealing portion 600, such as compression molding, printing, transfer molding, liquid sealing molding, vacuum pressing, and spin coating.

The manufacturing method of the package structure may further include step S600 : constructing an electrical connection portion 700 on a side of the first redistribution layer 300 away from the substrate 100 . In actual use, it can be installed and connected to the installation foundation through the electrical connection part 700 .

The embodiments of the present application have been described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific embodiments, which are merely illustrative rather than restrictive. Under the inspiration of this application, without departing from the scope of protection of the purpose of this application and the claims, many forms can be made, which all fall within the protection of this application.

Claims

A package structure, including:

A substrate (100) having a first surface (130), a second surface (140) and a cavity (110), the first surface (130) and the second surface (140) being in phase the back is arranged, the cavity (110) penetrates the first surface (130);

a first chip module (200), wherein the first chip module (200) is disposed in the cavity (110);

a first redistribution layer (300), the first redistribution layer (300) is disposed on the first surface (130) and covers the cavity (110);

a second redistribution layer (400), the second redistribution layer (400) is disposed on the second surface (140) and is electrically connected to the first redistribution layer (300);

a second chip module (500), the second chip module (500) is disposed on the second redistribution layer (400);

Wherein, the first chip module (200) is electrically connected to at least one of the first redistribution layer (300) and the second redistribution layer (400), and the second chip module (500) ) is electrically connected to the second redistribution layer (400).
The package structure according to claim 1, wherein the cavity (110) penetrates through the second surface (140), and the second redistribution layer (400) covers the cavity (110).
The package structure according to claim 2, wherein the first chip module (200) comprises a first chip (210) and a second chip (220) arranged in layers, the first chip (210) facing the The first redistribution layer (300) is electrically connected to the first redistribution layer (300), and the second chip (220) faces the second redistribution layer (400) and is connected to the first redistribution layer (300). The two redistribution layers (400) are electrically connected.
The package structure according to claim 3, wherein a fixed connection is achieved between the first chip (210) and the second chip (220) through an adhesive layer (230).
The package structure according to claim 3, wherein the second chip (220) is provided with a conductive bump (221) on the end face facing the second redistribution layer (400), and the second chip (220) ) is electrically connected to the second redistribution layer (400) through the conductive bumps (221).
The package structure according to claim 5, wherein a plurality of the conductive bumps (221) are provided, and the plurality of the conductive bumps (221) are evenly arranged on the second chip (220).
The package structure according to claim 1, wherein a through-silicon (120) is opened on the substrate (100), and the first redistribution layer (300) communicates with the second through-silicon (120) through the through-silicon (120). The redistribution layer (400) is electrically connected.
The package structure according to claim 1, wherein the substrate (100) is a silicon substrate.
An electronic device, comprising the packaging structure of any one of claims 1 to 8.
A manufacturing method of a package structure, comprising:

providing a substrate (100) with a cavity (110) formed in a first surface (130) of the substrate (100);

A first chip module (200) is provided, and the first chip module (200) is arranged in the cavity (110);

A first redistribution layer (300) is laminated and combined on the first surface (130) of the substrate (100), and the first redistribution layer (300) is covered on the cavity (110);

A second redistribution layer (400) is laminated and combined on the second surface (140) of the substrate (100), and the second redistribution layer (400) is electrically connected to the first redistribution layer (300). ;

A second chip module (500) is provided, and the second chip module (500) is disposed on the second redistribution layer (400).