JP2000260902A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce noise and the resistance or inductance of wiring being connected with a chip capacitor. SOLUTION: The wiring board 1 comprises a chip capacitor 10 contained in a recess 4 on the first major surface 2a of a core board 2, a first multiplayer wiring part 20 formed on the first major surface 2a, a terminal 28 to be connected with an IC chip 29 formed on the upper surface thereof, wiring 26, 27 to be connected with the IC connection terminal 28 provided at the wiring part 20, a second multiplayer wiring part 30 formed on the second major surface 2b of the board 2, an external connection terminal 38 formed on the upper surface thereof, and wiring 36, 37 to be connected with the external connection terminal 38 provided at the wiring part 30 and on the bottom face 4b of the recess 4. The capacitor 10 has a first terminal electrode 12 being connected with the first IC connection wiring 26 on the first major surface 2a side and with the first external connection wiring 36 on the second major surface 2b side, and a second terminal electrode 14 being connected with the second IC connection wiring 27 on the first major surface 2a side and with the second external connection wiring 37 on the second major surface 2b side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring substrate having a multilayer wiring portion on both main surfaces of a core substrate, and more particularly to a wiring substrate having a chip substrate built in a core substrate.

[0002]

2. Description of the Related Art In recent years, the operation of IC chips has been increasingly accelerated due to advances in integrated circuit technology. Along with this,
Noise may be superimposed on the power supply wiring and the like, causing a malfunction. Therefore, in order to remove such noise, for example, a chip capacitor is separately mounted on the upper or lower surface of the wiring board, and two terminal electrodes of the chip capacitor are mounted.
(First and second terminal electrodes) are provided inside the wiring board with chip capacitor wirings respectively connected thereto. Thereby, the chip capacitor can be connected to the IC chip via the chip capacitor wiring and the IC connection terminal.

However, in the wiring board having the above structure,
After completion, it is necessary to separately mount a chip capacitor, which requires man-hours and increases costs. In addition, the reliability of the wiring board may be reduced depending on the connection reliability of the chip capacitor, for example, the quality of the connection of the chip capacitor affects the quality of the entire wiring board. In addition, it is necessary to secure the area for mounting the chip capacitor on the upper and lower surfaces in advance, which reduces the degree of freedom in mounting other electronic components and fixing the reinforcing member (stiffener) for reinforcing the wiring board. There is also. In addition, it is limited to other wirings and the like, and the chip capacitor connection wiring for connecting the IC chip and the chip capacitor tends to be long and thin. For this reason, the resistance and inductance of the chip capacitor connection wiring itself tend to be excessive, and there has been a problem that the demand for low resistance and low inductance has not been sufficiently satisfied.

[0004]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems and reduces the noise and reduces the resistance and inductance of the wiring connected to the chip capacitor. It is an object of the present invention to provide a wiring board which has low loss cost even if it occurs, can be manufactured at low cost, and has a built-in chip capacitor having a large capacitance.

[0005]

According to the present invention, in order to solve the above-mentioned problems, a chip capacitor having a large capacitance is built in a core substrate, and two terminal electrodes are provided on the substrate.
This is made in connection with the connection with the lower surface. That is, the wiring board of the present invention includes: a core substrate having a first main surface and a second main surface; a concave portion formed on the first main surface of the core substrate; a chip capacitor housed in the concave portion; A first multilayer wiring portion formed by alternately laminating conductor layers and insulating layers on a first main surface of the core substrate accommodating the chip capacitor; and an IC formed on the upper surface of the first multilayer wiring portion, An IC connection terminal for connecting to the chip, an IC connection wire provided in the first multilayer wiring portion and connected to the IC connection terminal, and a conductor on the second main surface of the core substrate containing the chip capacitor A second multilayer wiring portion formed by alternately stacking layers and insulating layers; an external connection terminal formed on an upper surface of the second multilayer wiring portion; a bottom portion of the second multilayer wiring portion and the concave portion And an external connection line connected to the external connection terminal. Wherein the chip capacitor is connected to the first IC connection wiring on the first main surface side and is connected to the first external connection wiring on the second main surface side. A first terminal electrode connected to a second IC connection wiring on the first main surface side and a second terminal electrode connected to a second external connection wiring on the second main surface side And the following.

In the wiring board, a recess for accommodating a chip capacitor is formed in a core substrate, a chip capacitor is built therein, and a first multilayer wiring portion and a second multilayer wiring portion are formed on both sides of the core substrate.
A layer wiring portion is formed, and the first terminal electrode and the second terminal electrode of the chip capacitor and the IC connection terminal are respectively connected to the IC connection on the first main surface side. Further, the first terminal electrode and the second terminal electrode of the chip capacitor are respectively connected to the external connection wiring on the second main surface side. Therefore, both terminal electrodes of the chip capacitor can be respectively taken out to the first main surface side (upper) and the second main surface side (lower).

That is, a chip capacitor can be arranged at a very short distance from an IC connection terminal connected to an IC chip. Thereby, the first IC connection wiring and the second IC connection wiring can be formed to be extremely short. Therefore, noise can be reduced and the resistance and inductance of the wiring connected to the chip capacitor can be reduced. In addition, since the chip capacitor itself is built in the wiring board, it is not necessary to separately install a chip capacitor after the completion of the wiring board, or the number of chip capacitors to be mounted can be reduced.

In particular, it is desirable that the wiring board is characterized in that at least a part of the plurality of IC connection terminals is located above the chip capacitor and at a position overlapping with the chip capacitor. For example, when the IC connection terminal of the flip chip pad is located above the chip capacitor, the IC connection terminal, the first terminal electrode of the chip capacitor, and the second
A first IC connection wiring for connecting to a terminal electrode of
Can be particularly shortened. Therefore, the resistance and inductance of the first IC connection wiring and the second IC connection wiring can be further reduced, so that the noise reduction ability (effect) can be further improved.

[0009]

Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a cross section of a main part of a wiring board 1 according to the present invention. The wiring substrate 1 has a core substrate 2 made of a composite material of glass-epoxy resin and having a first main surface 2a and a second main surface 2b at substantially the center in the thickness direction, and the first main surface 2a of the core substrate 2 is provided. A concave portion 4 having a substantially rectangular shape is formed in a plan view. A plurality of chip capacitors 10 are accommodated in the recess 4, and each chip capacitor 10 has a first terminal electrode 12 and a second terminal electrode 14 on both left and right ends in the drawing. As such a chip capacitor 10, for example, a multilayer ceramic chip capacitor (capacitor) having a capacitance of about 1000 to 10,000 pF (Picofarat) and using barium titanate or the like as a dielectric is used.
It is about 0.5 × 0.5 mm. The space inside the recess 4 is filled with an insulating material (layer) 4b.

The terminal electrodes 12 and 14 are connected to the upper ends of through-hole conductors 6 and 6 passing through the bottom surface 4a of the recess 4 of the core substrate 2 by solders 16 and 18, respectively. A plurality of through-hole conductors 8 penetrating through the thick portion of the core substrate 2 without the concave portion 4 are formed, and the first and second main surfaces 2a, 2b of the core substrate 2 are formed on the upper and lower ends thereof. An upwardly extending land 9 is formed. The hollow portions in the through-hole conductor 6 and the through-hole conductor 8 are filled with a resin 5 or a resin 7, respectively. Further, the upper end 8a and the upper land 9 of the through-hole conductor 8 form a part of a first conductor layer 20a described below, and the lower end 6a, 8a of the through-hole conductor 6, 8 and the lower land 9a. 9 forms a part of a first conductor layer 30a described later.

Further, the first substrate having the concave portion 4 of the core substrate
On the main surface 2a, first to third conductor layers 20a, 22, 24
And first and second insulating layers 21 and 23 and solder resist
First multi-layer wiring section 20 in which (insulation) layers 25 are alternately stacked
Are formed. Via conductors 22a and 24b are formed in the second and third conductor layers 22 and 24 to penetrate the insulating layers 21 and 23 and establish conduction between the conductor layers. A plurality of IC connection terminals 28 penetrating the solder resist layer 25 and protruding from the surface thereof are formed at appropriate places of the third conductor layer 24. The IC connection terminal 28 is connected to an external connection terminal (not shown) on the bottom surface of the IC chip 29 mounted on the upper surface of the wiring board 1 by brazing. IC chip 29 and first and second terminal electrodes 1 of chip capacitor 10
The conductor layers 20a, 22, 24 that connect the second and the second 14 are
First and second IC connection wirings 26 and 27 are formed.

Further, on the second main surface 2b of the core substrate 2, first to third conductor layers 30a, 32, 34, first and second insulating layers 31, 33, and a solder resist (insulating) layer 35 are alternately stacked to form a second multilayer wiring portion 30.
Via conductors (32a, 34a) are formed in the conductor layers (32, 34) and penetrate the insulating layers (31, 33) to establish conduction between the conductor layers. External connection terminals 38 which are respectively exposed in a plurality of openings 39 formed in the solder resist layer 35 are formed at appropriate places of the third conductor layer 34. The portions of the conductor layers 30a, 32, and 34 that connect the external connection terminals 38 and the first and second terminal electrodes 12 and 14 of the chip capacitor 10 form first and second external connection wires 36 and 37, respectively. ing. The surface of the external connection terminal 38 is made of thin Au and Ni.
Plated. The conductor layer 2 in the wiring board 1 without passing through the IC chip 29 and the chip capacitor 10
The conductor portion connected to the external connection terminal 38 via 4, 22, 20a, 30a, 32, 34 forms a signal connection wiring.

As described above, the wiring board 1 incorporates a plurality of chip capacitors 10 in the recesses 4 of the core
The first terminal electrodes 12, 14 and the IC connection terminal 28
First and second IC connection wirings 26 and 27 in multilayer wiring part 20
Connect with The first capacitor of the chip capacitor 10
The second terminal electrodes 12 and 14 and the external connection terminal 38 are
First and second external connection wirings 36 and 37 in the multilayer wiring part 30
Connect with For this reason, the first and second terminal electrodes 12 and 14 of the chip capacitor 10 are respectively connected to the upper surface (the first main surface 2a side) and the lower surface (the second main surface 2b side) of the substrate 1 and are in conduction. . That is, the chip capacitor 10 can be disposed at a short distance from the IC connection terminal 28 connected to the IC chip 29, and the first and second IC connection wirings 26 and 27 can be disposed to be extremely short.

Therefore, according to the wiring board 1, noise can be reduced, and the resistance and inductance of the IC connection wirings 26 and 27 connected to the chip capacitor 10 can be reduced.
The conduction between the chip 29 and the chip capacitor 10 can be taken at high speed and accurately, and the conduction between the IC chip 29 and the first and second multilayer wiring portions 20 and 30 can be taken reliably. In addition, it is possible to reliably ensure conduction between a circuit element in a motherboard (not shown) to which the wiring board 1 is connected via the external connection terminal 38 and the chip capacitor 10 and the like. Moreover,
Since the chip capacitor 10 is built in the recess 4 of the core substrate 2, it is not necessary to separately mount a chip capacitor on the upper surface of the substrate 1, so that the entire thickness can be suppressed, or the number of chip capacitors separately mounted can be reduced. can do. Further, in the wiring board 1, since each IC connection terminal 28 is located above the chip capacitor 10, the first
The second IC connection wirings 26 and 27 can be made the shortest and their inductance and resistance can be further reduced, so that the noise reduction characteristics are significantly improved.

Hereinafter, a method of manufacturing the above-described wiring board 1 will be described. Note that, in FIG. 2 and subsequent figures, the following description will focus on the left chip capacitor 10 in FIG.
FIG. 2A shows a cross section of a core substrate base plate 2c made of a glass-epoxy resin having copper foils affixed to both sides thereof.
As shown in (B), a through hole 3 is drilled at a predetermined position with a drill. Then, both surfaces of the base plate 2c and the inside of the through hole 3 are plated with copper, and a resin is filled in a hollow portion near the center of the through hole 3 and hardened. Thereafter, both surfaces of the base plate 2c are further plated with copper, and masking is performed to remove the copper plating layer and the copper foil c at unnecessary positions by etching. As a result, as shown in FIG. 2C, a through-hole conductor 6 and a resin 5 buried near the center thereof are formed in each through-hole 3, and substantially circular upper and lower ends of the through-hole conductor 6 are formed. Is formed.
The land 6b extends from a part of the flange 6a by the masking. The lower flange 6a and the land 6b form a part of the first conductor layer 30a.

Next, as shown in FIG. 2 (D), a thick core substrate 2d is laminated on the upper surface of the core substrate 2c via a film-like adhesive sheet 2e and thermocompression-bonded. A substantially rectangular opening 2f is formed in the base plate 2d in advance, and the base plates 2c and 2d are formed.
To form the core substrate 2 and
A concave portion 4 is formed on the first main surface 2a side. Note that the lower surface of the core substrate 2 is the second main surface 2b. Further, as shown in FIG. 3 (A), the chip capacitor 10 is inserted into the recess 4, and the chip capacitor 10 is placed on the upper flange 6 a of each through-hole conductor 6 penetrating the bottom 4 a of the recess 4. The first and second terminal electrodes 12, 14 are brought close to each other. As shown in FIG. 3B, in this state, solders 16 and 18 are applied to join the first and second terminal electrodes 12 and 14 and the through-hole conductors 6 and 6. As a result, the terminal electrodes 12 and 14 having substantially U-shaped cross sections provided at the left and right ends of the chip capacitor 10 are electrically connected to the through-hole conductors 6 and 6 via the solders 16 and 18, respectively.

Next, after an epoxy resin is applied above the core substrate 2 and the chip capacitor 10, the surface is ground and flattened. As a result, as shown in FIG. 3C, the upper end surfaces of the first and second terminal electrodes 12 and 14 in the chip capacitor 10 are exposed, and the chip capacitor 10 is embedded and embedded in the recess 4. Resin (insulation) layer 4
b is formed. In the following, the upper surface of the resin layer 4b is referred to as the first main surface 2a of the core substrate 2 for convenience of description.

Subsequently, as shown in FIG. 4A, through holes 3 are drilled at predetermined positions in the thick portion of the core substrate 2 where there is no concave portion 4. Next, copper plating is applied to both surfaces of the core substrate 2 and the inside of the through hole 3, and a resin is filled in a hollow portion near the center of the through hole 3 and cured. Further, masking is performed to remove the copper plating layer at unnecessary positions by etching. As a result, as shown in FIG.
And a resin 7 embedded near the center thereof, and a substantially circular flange 8a is formed at the upper and lower ends of the through-hole conductor 8. The land 9 is formed to extend from a part of the flange 8a by the masking. The upper and lower flanges 8a and lands 9 are respectively connected to the first conductor layer 20.
a, 30a.

During this time, the chip capacitor 10
The upper ends of the first and second terminal electrodes 12 and 14 are also thickened so as to be at the same level as the flange 8a. Next, an epoxy resin is applied above the core substrate 2 and the chip capacitor 10, and the surface thereof is ground and flattened. As a result, as shown in FIG.
A resin (insulating) layer 19 exposing the upper end surfaces of the first and second terminal electrodes 12 and 14 is formed. Also, an epoxy-based resin is applied on the second main surface 2b of the core substrate 2 and the surface thereof is ground to form a flattened resin layer 19.
In addition, on the surface of the resin layer 19 on the second main surface 2b, the flanges 6a, 8a and the lands 6b, 9 forming the conductor layer 30a are provided.
Is exposed.

Then, as shown in FIG. 5A, a film-shaped photosensitive epoxy resin sheet is attached above the first main surface 2a and the second main surface 2b of the core substrate 2 to form the first substrate. The insulating layers 21 and 31 are formed. Via holes 21a and 31a are formed at predetermined positions in the insulating layers 21 and 31 by a known photolithography technique. After copper plating is formed in the via holes 21a and 31a and on the first insulating layers 21 and 31, respectively, a predetermined pattern is etched (patterned). As a result, as shown in FIG. 5B, the via conductors 22a and 32a and the second conductor layers 22 and 3
2 are formed.

Similarly, an epoxy resin sheet is pasted on the first insulating layers 21 and 31 and the second conductive layers 22 and 32 to form second insulating layers 23 and 33. After the via holes are formed in the via conductors 24a and 34
a and the third conductor layers 24 and 34 are formed. Finally, solder resist layers 25 and 35 are formed on both sides,
5 by projecting through the IC connection terminal 28 from a predetermined position and exposing the external connection terminal 38 in a plurality of openings 39 provided in the resist layer 35, respectively. 1 can be obtained. Note that the IC connection terminal 28 is generally located above the chip capacitor 10.

Then, as shown in FIG. 1, by connecting external connection terminals provided on the bottom surface of the IC chip 29 to each IC connection terminal 28 via a brazing material, the IC chip 29 is placed on the wiring board 1. Is mounted. The IC chip 29 and the first and second terminal electrodes 12, 1 of the chip capacitor 10.
4 are connected to the first conductor layers 20a, 22, 24.
Second IC connection wirings 26 and 27 are formed. In addition, the external connection terminal 38 and the first and second
Conductor layers 30a, 32,
The portion 34 forms first and second external connection wirings 36 and 37. As a result, the first and second terminal electrodes 12 and 14 of the chip capacitor 10 are respectively connected to the first main surface 2a side and the second main surface 2b side of the substrate 1 so as to conduct and connect to the IC chip 29. Since the chip capacitor 10 can be arranged at a short distance from the IC connection terminal 28, the first and second IC connection wirings 26 and 27 can be extremely short.

Therefore, according to the wiring board 1, as described above, noise can be reduced and the chip capacitor 10
The resistance and inductance of the IC connection wirings 26 and 27 connected to the IC chip 29 and the chip capacitor 1 can be reduced.
Conduction with 0 can be taken quickly and accurately. In addition, conduction between the circuit element in the motherboard to which the wiring board 1 is connected via the external connection terminal 38 and the chip capacitor 10 can be reliably ensured. Moreover, since the chip capacitor 10 is built in the recess 4 of the core substrate 2, there is no need to separately mount a chip capacitor on the upper surface of the substrate 1, and the wiring substrate 1
The total thickness can be suppressed, or the number of components mounted on the upper surface can be reduced.

The present invention is not limited to the embodiment described above. For example, a plurality of recesses may be formed in the first main surface of the core substrate, and chip capacitors may be individually incorporated in each of the recesses. Alternatively, the concave portion may be formed by partially removing the first main surface side of the single core substrate by cutting or the like. In addition, chip capacitors include:
In addition to the above-described embodiments, various types such as a semiconductor type ceramic chip capacitor can be applied. Further, as a mounted IC chip, a monolithic IC (bipolar type, MOS type, Bi-CMOS) chip in which a semiconductor is integrated, a hybrid IC chip in which a capacitor and a resistor are integrated together with the semiconductor, and the like are also applicable.

In addition to the glass-epoxy composite material used in the above embodiment, the core substrate 2 may be made of a composite resin material such as BT resin-glass material, glass-PPE material, paper-epoxy, or epoxy, BT Resin, polyimide, PP
It is also possible to use resins such as E and PTFE. Further, the conductor layers 22, 24, etc. are not limited to copper, but Ni and its alloys (Ni-P, Ni-B, Ni-Cu-P), Co and its alloys (Co-P, Co-B, Co- Ni-P), Sn and its alloys (Sn-Pb, Sn-Pb-Pd), or Au, A
It is also possible to use g, Pd, Pt, Rh, Ru, etc., and alloys based on these.

[0026]

In the wiring board of the present invention described above, a chip capacitor is built in the recess of the core substrate, and the first and second terminal electrodes and the IC connection terminal are connected to the first multilayer wiring portion in the first multilayer wiring portion. The first and second terminal electrodes of the chip capacitor are connected to the external connection terminals by the first and second external connection wires of the second multilayer wiring portion. As a result, the first and second terminal electrodes of the chip capacitor are connected to the upper surface (the first main surface side) and the lower surface (the second main surface side) of the wiring board, respectively, and are electrically connected.
The chip capacitor can be arranged at a short distance from the IC connection terminal connected to the chip, and the first and second IC connection wirings can be arranged extremely short.

Therefore, according to such a wiring board, noise can be reduced, and the resistance and inductance of the IC connection wiring connected to the chip capacitor can be reduced, and the conduction between the IC chip and the chip capacitor can be obtained at high speed and accurately.
Conduction between the chip and the first and second multilayer wiring portions 2 can be reliably ensured. In addition, it is possible to reliably ensure conduction between the circuit element in the mother board to which the wiring board is connected via the external connection terminal and the chip capacitor. Moreover, since the chip capacitors are built into the recesses of the core substrate, there is no need to separately mount the chip capacitors on the upper surface of the wiring board, thereby reducing the overall thickness, or reducing the number of chip capacitors separately mounted on the upper surface. can do.

Further, when the IC connection terminals are located above the chip capacitors on the wiring board, the first and second IC connection wirings can be made the shortest, and their inductance and resistance can be further reduced. The noise reduction characteristics are further improved. In addition, even if a defect occurs in the chip capacitor, it is possible to provide a wiring board which has low loss cost, can be manufactured at low cost, and has a built-in chip capacitor having a large capacitance.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a main part of a wiring board according to the present invention.

FIGS. 2A to 2D are partial cross-sectional views schematically showing respective manufacturing steps for obtaining a wiring board of the present invention.

3 (A) to 3 (C) are partial cross-sectional views schematically showing respective manufacturing steps following FIG. 2;

FIGS. 4A and 4B are partial cross-sectional views schematically showing the respective manufacturing steps following FIG.

FIGS. 5A and 5B are partial cross-sectional views schematically showing the respective manufacturing steps following FIG.

[Explanation of symbols]

 1 Wiring substrate 2 Core substrate 2a First main surface 2b Second main surface 4 ... Recesses 4a bottom surface 10 chip capacitor 12 first terminal electrode 14 second terminal Terminal electrode 20 First multilayer wiring portion 20a, 22, 24 Conductive layer 21, 23, 25 Insulating layer 26 First IC connection wiring 27 ... Second IC connection wiring 28 IC connection terminal 29 IC chip 30 Second multilayer wiring part 30 a, 32, 34. Conductive layer 31, 33, 35 Insulating layer 36 First external connection wiring 37 Second external connection wiring 38 External connection terminal

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yukihiro Kimura 14-18 Takatsuji-cho, Mizuho-ku, Nagoya City, Aichi Japan F-term (reference) 5E346 AA02 AA06 AA12 AA15 AA43 BB01 BB16 BB20 CC09 CC31 DD02 FF04 FF45 GG15 HH01 HH02 HH05 HH31

Claims (1)

[Claims] A core substrate having a first main surface and a second main surface; a recess formed in the first main surface of the core substrate; a chip capacitor housed in the recess; A first multilayer wiring portion formed by alternately stacking conductor layers and insulating layers on the first main surface of the accommodated core substrate; and a first multilayer wiring portion formed on the upper surface of the first multilayer wiring portion and connected to an IC chip. Connection terminals provided on the first multilayer wiring portion and connected to the IC connection terminals, and a conductor layer and an insulating layer on a second main surface of the core substrate accommodating the chip capacitor. A second multilayer wiring portion formed by alternately laminating the second multilayer wiring portion, an external connection terminal formed on an upper surface of the second multilayer wiring portion, and a bottom portion of the second multilayer wiring portion and the concave portion, External connection wiring connected to the external connection terminal, A wiring board was example, the chip capacitor, first in the first main surface side
And a first terminal electrode connected to the first external connection wiring on the second main surface side, and connected to a second IC connection wiring on the first main surface side. And a second terminal electrode connected to a second external connection wiring on the second main surface side.