JP2002271029A - Printed wiring board and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board which can reduce its loop inductance and a manufacturing method for the printed wiring board. SOLUTION: A chip capacitor 20 is arranged in the printed wiring board 10, so the distance between an IC chip 90 and the chip capacitor 20 becomes short and the loop inductance can be reduced. The surfaces of 1st and 2nd electrodes 21 and 22 of the chip capacitor 20 are flattened with conductive paste 26. When a non-through hole 43 is bored in the inter-layer resin insulating layer 40, no resin is left, so that the reliability of the connection between the electrodes 21 and 22 when the via hole 46 is formed can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board on which electronic components such as IC chips are mounted, and more particularly to a printed wiring board having a built-in capacitor.

[0002]

2. Description of the Related Art Usually, inside a computer, a wiring distance between a power supply and an IC chip is long, and a loop inductance of this wiring portion is very large.
For this reason, the fluctuation of the IC drive voltage during the high-speed operation increases, which may cause the IC to malfunction. It is also difficult to stabilize the power supply voltage. For this reason, a capacitor is mounted on the surface of the printed wiring board to assist in power supply.

[0003] That is, the loop inductance that causes the voltage fluctuation is changed from the power supply shown in FIG.
Power supply terminal 27 of IC chip 270
It depends on the wiring length up to 2P and the wiring length from the ground terminal 272E of the IC chip 270 to the power supply from the power supply via the ground wire in the printed wiring board 300. Further, the loop inductance can be reduced by reducing the distance between the wirings in which the current flows in the opposite direction, for example, the distance between the power supply line and the ground line. For this reason, as shown in FIG. 19B, by mounting the chip capacitor 298 on the printed wiring board 300, the printed wiring board 300 connecting the IC chip 270 and the chip capacitor 292 serving as a power supply source.
Shorten the wiring length between the power line and the ground line inside
It has been practiced to reduce the loop inductance by reducing the wiring interval.

[0004]

However, the magnitude of the voltage drop that causes the fluctuation of the IC driving voltage depends on the frequency. Therefore, as the driving frequency of the IC chip increases, the loop inductance cannot be reduced even if the chip capacitor is mounted on the surface as described above with reference to FIG. It became difficult to control.

For this reason, the present inventor has an idea of accommodating a chip capacitor in a printed wiring board. As a technique for embedding a capacitor in a substrate, see Japanese Unexamined Patent Publication No.
6472, JP-A-7-263619, JP-A-10-
No. 256429, JP-A-11-45555, JP-A-1
1-112678 and JP-A-11-31868.

Japanese Patent Application Laid-Open No. Hei 6-326472 discloses a technique for embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, power supply noise is reduced, and a space for mounting a chip capacitor is not required, and the size of the insulating substrate can be reduced. In addition, Japanese Patent Application Laid-Open
No. 263619 discloses a technique for embedding a capacitor in a substrate made of ceramic, alumina, or the like. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.

[0007] However, the above-described technique cannot make the distance between the IC chip and the capacitor very short, and cannot reduce the inductance as required at present in a higher frequency region of the IC chip.
In particular, in a resin-made multilayer build-up wiring board, disconnection between a terminal of a chip capacitor and a via hole due to a difference in thermal expansion coefficient between a capacitor made of ceramic and a core substrate made of resin and an interlayer resin insulating layer. Peeling occurred between the chip capacitor and the interlayer resin insulation layer, cracks occurred in the interlayer resin insulation layer, and high reliability could not be achieved for a long period of time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board which can reduce loop inductance and has high reliability, and a method of manufacturing the same. is there.

[0009]

According to a first aspect of the present invention, there is provided a printed wiring board having a resin insulating layer and a conductive circuit laminated on a core substrate, wherein the core substrate has at least A conductive paste is formed on the surface of the metallized electrode of the capacitor, comprising a connection layer formed of at least one insulating resin layer, and a housing layer housing the capacitor and comprising two or more resin layers. Is a technical feature.

A circuit formed by a build-up method in which an interlayer resin insulating layer is provided on a core substrate, a via hole or a through hole is formed in the interlayer resin insulating layer, and a conductive circuit as a conductive layer is formed. I have. They include
Either a semi-additive method or a full-additive method can be used.

According to the first aspect, since the capacitor is arranged in the printed wiring board, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced. Further, the core substrate includes at least one or more connection layers and a housing layer for housing the capacitor. Since the capacitor is housed in the thick housing layer, the core substrate does not become thick, and the interlayer resin is formed on the core substrate. Even when the insulating layer and the conductive circuit are laminated, the printed wiring board does not become thick.

It is desirable to fill the void with a resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if a stress originating from the capacitor is generated, the stress can be reduced by the filled resin. The resin also has the effect of reducing adhesion and migration between the capacitor and the core substrate.

Further, since the conductive paste is applied to the surface of the electrode of the capacitor, the surface becomes completely flat. For this reason, when an opening is formed in the resin layer with a laser,
The resin does not remain on the surface of the electrode, and the connection reliability between the electrode and the via hole formed by plating can be improved.

According to a second aspect of the present invention, there is provided a printed wiring board formed by laminating a resin insulating layer and a conductive circuit on a core substrate, wherein the core substrate comprises at least one or more insulating resin layers. And a capacitor housing and a housing layer formed of two or more resin layers. Vias are formed on both sides to be connected to the capacitor, and a conductive paste is applied to the surface of the metallized electrode of the capacitor. Is a technical feature.

According to the second aspect, since the capacitor is arranged in the printed wiring board, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced. Further, the core substrate includes at least one or more connection layers and a housing layer for housing the capacitor. Since the capacitor is housed in the thick housing layer, the core substrate does not become thick, and the interlayer resin is formed on the core substrate. Even when the insulating layer and the conductive circuit are laminated, the printed wiring board does not become thick.

Further, since the conductive paste is applied to the surface of the electrode of the capacitor, the surface becomes completely flat. For this reason, when an opening is formed in the resin layer with a laser,
The resin does not remain on the surface of the electrode, and the connection reliability between the electrode and the via hole formed by plating can be improved. Furthermore, since via holes are provided on both sides of the core board, the IC chip and the capacitor housed in the board, and the power supply arranged on the external connection board and the capacitor housed in the board are kept at the shortest distance. Can connect. Therefore, the voltage can be instantaneously supplemented from the power supply to the IC chip, and the IC drive voltage can be quickly stabilized.

According to the third aspect, since the metal layer is provided on the conductive paste of the electrode of the capacitor, it is possible to prevent the occurrence of migration at the electrode and further reduce the connection resistance.

According to a fourth aspect, the surface of the capacitor is subjected to a roughening treatment. Thereby, the adhesion between the chip capacitor made of ceramic and the adhesive layer made of resin and the interlayer resin insulating layer is increased, and the adhesive layer and interlayer resin insulating layer are separated at the interface even when the heat cycle test is performed. Nothing.

According to a fifth aspect of the present invention, the surface of the capacitor is subjected to a wettability improving treatment such as a seal coupling or a resin coating. Thereby, the adhesion between the chip capacitor made of ceramic and the adhesive layer made of resin and the interlayer resin insulating layer is increased, and the adhesive layer and interlayer resin insulating layer are separated at the interface even when the heat cycle test is performed. Nothing.

According to the eighth aspect of the present invention, wiring for connecting the IC chip to the external substrate is provided between the capacitors, and the signal line does not pass through the capacitors. No propagation delay occurs due to passage. By providing a capacitor for power supply, IC
Large power can be easily supplied to the chip. Providing the ground capacitor can reduce noise in signal propagation on the printed wiring board.

Further, by disposing the connection wiring,
Wiring can also be provided below the capacitor.
Therefore, the degree of freedom of wiring is increased, and higher density and smaller size can be achieved.

In the ninth aspect, a capacitor is provided on the surface in addition to the capacitor housed in the substrate. Since the capacitor is housed in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance is reduced, and power can be supplied instantaneously. Because a capacitor is provided, a large-capacity capacitor can be attached.
Large power can be easily supplied to the IC chip.

According to the tenth aspect, the capacitance of the capacitor on the surface is larger than the capacitance of the capacitor in the inner layer.
There is no shortage of power supply in the high frequency range, and the desired IC
The operation of the chip is ensured.

According to the eleventh aspect, since the inductance of the capacitor on the surface is equal to or greater than the inductance of the capacitor in the inner layer, there is no shortage of power supply in a high-frequency region, and a desired operation of the IC chip is ensured.

In the twelfth aspect, since a chip capacitor having an electrode formed inside the outer edge is used, a large external electrode can be obtained even when conduction is established through a via hole, and the allowable range of alignment is widened. Disappears.

In the thirteenth aspect, since a capacitor having electrodes formed in a matrix is used, it is easy to accommodate a large chip capacitor in the core substrate. Therefore, the capacitance can be increased, so that an electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is less likely to warp.

In a fourteenth aspect, a plurality of chip capacitors for multi-cavity may be connected to the capacitor. As a result, the capacitance can be adjusted appropriately, and I
The C chip can be operated.

According to a fifteenth aspect, the coefficient of thermal expansion of the insulating adhesive is set to be smaller than that of the encasing layer, that is, close to that of a ceramic capacitor. For this reason, in the heat cycle test, even if internal stress occurs due to the difference in thermal expansion coefficient between the housing layer and the capacitor constituting the core substrate,
Cracks, peeling, and the like are less likely to occur on the core substrate, and high reliability can be achieved.

The technical feature of the method for manufacturing a printed wiring board according to claim 16 is that it comprises at least the following steps (a) to (e): (a) a first method in which a resin is contained in a core material; Forming a through hole for accommodating the capacitor in the resin material; (b) attaching a second resin material to the first resin material in which the through hole has been formed to form a housing layer having a capacitor housing portion. (C) a step of housing a capacitor having a conductive paste applied on a metallized electrode in the housing layer; and (d) attaching a third insulating resin layer to the housing layer in the step (c) to form a core substrate. (E) forming a via hole in the third insulating resin layer by providing an opening to an electrode of the capacitor.

The method for manufacturing a printed wiring board according to the seventeenth aspect is characterized by comprising at least the following steps (a) to (e): (a) a first material in which a resin is contained in a core material; Forming a through hole for accommodating a capacitor in the resin material; (b) applying a conductive paste on the metallized electrode to a position corresponding to the capacitor accommodating portion of the first resin material on the second resin material; (C) attaching the first resin material that has passed through the step (a) and the second resin material that has passed through the step (b) to form a housing layer that houses the capacitor; (D) a step of attaching a third insulating resin layer to the housing layer to form a core substrate; (e) a step of forming a via hole by providing an opening to the electrode of the capacitor in the third insulating resin layer.

The technical feature of the method for manufacturing a printed wiring board according to the eighteenth aspect is to provide at least the following steps (a) to (f): (a) A first method in which a core material contains a resin. Forming a through-hole for accommodating a capacitor in the resin material; (b) providing a through-hole serving as a via hole in the second resin material, and metallizing the electrode to a position corresponding to the capacitor accommodating portion of the first resin material Disposing a capacitor having a conductive paste applied thereon; (c) attaching the first resin material having undergone the above (a) step and the second resin material having undergone the above (b) step to form a capacitor; (D) attaching a third insulating resin layer to the containing layer to form a core substrate; (e) forming an opening in the third insulating resin layer to reach the electrode of the capacitor. Providing step; (f) Step of the via hole in serial through-hole and the opening of the third resin material of the first resin material to form a conductive film.

According to the printed wiring board manufacturing method of the present invention, the chip capacitor can be accommodated in the core substrate, and a printed wiring board with reduced loop inductance can be provided.

Since the conductive paste is applied to the surface of the electrode of the capacitor, the surface becomes completely flat. For this reason, when an opening is formed in the resin layer with a laser,
The resin does not remain on the surface of the electrode, and the connection reliability between the electrode and the via hole formed by plating can be improved.

According to the method for manufacturing a printed wiring board of the eighteenth aspect, the chip capacitor can be accommodated in the core substrate, and a printed wiring board with reduced loop inductance can be provided.

Further, since the conductive paste is applied to the surface of the capacitor electrode, the surface becomes completely flat. For this reason, when an opening is formed in the resin layer with a laser,
The resin does not remain on the surface of the electrode, and the connection reliability between the electrode and the via hole formed by plating can be improved. Furthermore, since via holes are provided on both sides of the core board, the IC chip and the capacitor housed in the board, and the power supply arranged on the external connection board and the capacitor housed in the board are kept at the shortest distance. Can connect. Therefore, the voltage can be instantaneously supplemented from the power supply to the IC chip, and the IC drive voltage can be quickly stabilized.

In the method for manufacturing a printed wiring board according to the nineteenth aspect, since the encasing layer accommodating the capacitor and the third resin material are bonded to each other by applying pressure to both surfaces to form a core substrate, the surface is flattened. An interlayer resin insulating layer and a conductor circuit having high reliability can be laminated.

In the thermosetting resin film used in the interlayer resin insulating layer and the connection layer of the present invention, particles which are soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble particles”) are hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a resin). , Hardly soluble resin). In addition, the "poorly soluble" used in the present invention
The term "soluble" refers to a substance having a relatively high dissolution rate when immersed in a solution containing the same acid or oxidizing agent for the same time as "soluble" for convenience, and a substance having a relatively low dissolution rate for convenience. Called "poorly soluble".

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

As the soluble resin particles, resin particles made of rubber can also be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

Examples of the soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin film can be ensured, and thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulating layer. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, a via opening can be formed in the interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenol F type epoxy resin, and naphthalene type epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin film used in the present invention, it is desirable that the soluble particles are substantially uniformly dispersed in the poorly soluble resin. A roughened surface having unevenness with a uniform roughness can be formed, and even when a via or a through hole is formed in a resin film, the adhesion of a metal layer of a conductive circuit formed thereon can be secured. Because. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby, since the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin film, the compounding amount of the soluble particles dispersed in the poorly soluble resin is preferably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, the soluble particles may be dissolved using an acid or an oxidizing agent. In addition, there is a case where the resin film is melted to a deep portion of the resin film and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

The resin film desirably contains a curing agent and other components in addition to the soluble particles and the hardly soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and microcapsules of these curing agents, and organic materials such as triphenylphosphine, tetraphenylphosphonium, and tetraphenylborate. Phosphine compounds and the like can be mentioned.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin film. 0.
If the amount is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidizing agent into the resin film is increased, and the insulating property of the resin film may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

Examples of the other components include fillers such as inorganic compounds or resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the printed wiring board can be improved by matching the thermal expansion coefficient, improving heat resistance and chemical resistance, and the like.

Further, the resin film may contain a solvent. As the solvent, for example, acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of two or more.

[0056]

Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 6 shows a cross section of the printed wiring board 10, and FIG. 7 shows a state where the IC chip 90 is mounted on the printed wiring board 10 shown in FIG.

As shown in FIG. 6, the printed wiring board 10
The chip capacitor 20 includes a core substrate 30 that houses the chip capacitor 20, and an interlayer resin insulation layer 60 that forms the build-up layers 80A and 80B. Core substrate 30
Are a housing layer 31 for housing the capacitor 20 and a connection layer 40
Consists of Via holes 46 and conductor circuits 48 are formed in the connection layer 40, and via holes 66 and conductor circuits 68 are formed in the interlayer resin insulation layer 60. In the present embodiment, the build-up layer has one interlayer resin insulation layer 6.
However, the build-up layer may include a plurality of interlayer resin insulation layers.

As shown in FIG. 14A, the chip capacitor 20 includes a first electrode 21 and a second electrode 22, and a dielectric 23 sandwiched between the first and second electrodes.
A first conductive film 24 connected to the first electrode 21 side;
A plurality of second conductive films 25 connected to the second electrode 22 side are arranged facing each other. A conductive paste 26 covers the surfaces of the first electrode 21 and the second electrode.

Here, the first electrode 21 and the second electrode 22
Consists of metallization of Ni, Pb or Ag metal. The conductive paste 26 is made of a paste containing metal particles such as Cu, Ni or Ag. Here, the particle size of the metal particles is preferably 0.1 to 10 μm, particularly 1 to 5 μm.
Is optimal. As the conductive paste, metal particles,
An organic conductive paste to which a thermosetting resin such as an epoxy resin or a polyphenylene sulfide (PPS) resin is added is desirable. The thickness of the conductive paste 26 is 1 to 30.
μm is desirable. If the thickness is less than 1 μm, unevenness on the electrode surface cannot be eliminated, while if it exceeds 30 μm, the effect is not particularly improved. Here, a thickness of 5 to 20 μm is most desirable. Note that a paste containing two or more types of particles having different diameters can be used, and further, two or more types of different metal pastes can be coated.

The electrodes 21 and 22 of the chip capacitor are made of metallized and have irregularities on the surface. Therefore, when the metal layer is used in a state where the metal layer is exposed, the resin may remain on the unevenness in the step of forming the non-through hole 43 in the interlayer resin insulating layer 40 by laser. In this case, the connection between the first and second electrodes 21 and 22 and the via hole 46 occurs due to the resin residue. In the present embodiment, the surfaces of the first and second electrodes 21 and 22 are smoothed by the conductive paste 26, and when the non-through holes 43 covered on the electrodes are formed, no resin residue remains. Connection reliability with the electrodes 21 and 22 when the via hole 46 is formed can be improved.

Further, a roughened layer 23a is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. Therefore, the chip capacitor 20 made of ceramic, the adhesive 32 made of resin, and the interlayer resin insulation layer 4 are formed.
Therefore, the adhesive 32 and the interlayer resin insulating layer 40 do not peel off at the interface even when the heat cycle test is performed. The roughened layer 23a can be formed by polishing the surface of the chip capacitor 20 after firing, or by performing a roughening process before firing.

As shown in FIG. 7, the upper build-up layer 8
Bumps 76 for connecting to pads 92S1, 92S2, 92P1, and 92P2 of IC chip 90 are formed in via hole 66 of 0A. On the other hand, pads 96S1, 96S2, 96P1, 96P2 of the daughter board 94 are provided in the via holes 66 of the lower buildup layer 80B.
A bump 76 is provided for connection to the substrate. A through hole 36 is formed in the core substrate 30.

Signal pad 92S2 of IC chip 90
Are connected to the signal pad 96S2 of the daughter board 94 via the bump 76, the conductor circuit 68, the via hole 66, the through hole 36, the via hole 66, and the bump 76. On the other hand, the signal pad 9 of the IC chip 90
2S1 is connected to a signal pad 96S1 of the daughter board 94 via a bump 76-via hole 66-through hole 36-via hole 66-bump 76.

Power supply pad 92P1 of IC chip 90
Is connected to the first electrode 21 of the chip capacitor 20 via the bump 76-via hole 66-conductor circuit 48-via hole 46. On the other hand, the power supply pad 96P1 of the daughter board 94 is connected to the bump 76-via hole 66.
-Through hole 36-Conductor circuit 48-Via hole 46
To the first electrode 21 of the chip capacitor 20.

Power supply pad 92P2 of IC chip 90
Is connected to the second electrode 22 of the chip capacitor 20 via a bump 76-via hole 66-conductor circuit 48-via hole 46. On the other hand, the power supply pad 96P2 of the daughter board 94 is connected to the bump 76 and the via hole 66.
-Through hole 36-Conductor circuit 48-Via hole 46
Is connected to the second electrode 22 of the chip capacitor 20 via the.

In the printed wiring board 10 of the present embodiment, I
Since the chip capacitor 20 is disposed immediately below the C chip 90, the distance between the IC chip and the capacitor is shortened, so that power can be instantaneously supplied to the IC chip. That is, the loop length that determines the loop inductance can be reduced.

Further, a through hole 36 is provided between the chip capacitors 20 so that a signal line does not pass through the chip capacitor 20. For this reason, it is possible to prevent reflection due to impedance discontinuity due to the high dielectric substance that occurs when passing through the capacitor, and propagation delay due to passage through the high dielectric substance.

An external board (daughter board) 94 connected to the back side of the printed wiring board and the first terminal 21 and the second terminal 22 of the capacitor 20 are connected to via holes provided in the connection layer 40 on the IC chip side. 46 and through a through hole 36 formed in the core substrate. That is, since a through hole is formed in the housing layer 31 having the core material and which is difficult to process, and the terminal of the capacitor is not directly connected to the external substrate, the connection reliability can be improved.

Further, in this embodiment, as shown in FIG. 6, the lower surface of the through hole 37 of the core substrate 30 and the chip capacitor 20
An adhesive 32 is interposed therebetween, and a resin filler 32 a is filled between the side surface of the through hole 37 and the chip capacitor 20. Here, the thermal expansion coefficients of the adhesive 32 and the resin filler 32a are set to be smaller than those of the core substrate 30 and the adhesive layer 40, that is, close to the chip capacitor 20 made of ceramic. Therefore, in the heat cycle test, the core substrate and the adhesive layer 40 and the chip capacitor 20
Even if internal stress is generated due to the difference in the coefficient of thermal expansion between the core substrate and the adhesive layer 40, cracks, peeling, and the like hardly occur, and high reliability can be achieved. Further, occurrence of migration can be prevented.

The manufacturing process of the printed wiring board according to the first embodiment will be described with reference to FIGS. First, a through hole 37 for accommodating a chip capacitor is formed in a laminated plate 31α formed by laminating four prepregs 35 in which a core material is impregnated with an epoxy resin, and a laminated plate 31β formed by laminating two prepregs 35 is formed. Prepare (FIG. 1A). Here, as the prepreg, a material containing a reinforcing material such as BT, phenol resin or glass cloth other than epoxy can be used. Next, after stacking the laminated plate 31α and the laminated plate 31β to form the accommodation layer 31, FIG.
The chip capacitor 20 described above is accommodated with reference to FIG. 1 (FIG. 1B). Here, it is preferable that the adhesive 32 is interposed between the through hole 37 and the chip capacitor 20. Since the melting point of the resin and the interlayer resin insulating layer used in the present application is 300 ° C. or less, when a temperature exceeding 350 ° C. is applied, the resin is dissolved, softened, or carbonized. Adhesive 3
It is desirable that 2 has a smaller coefficient of thermal expansion than the core substrate.

The core substrate is made of ceramic or AIN.
Such a substrate could not be used. This is because the substrate has poor external formability, and may not be able to accommodate a capacitor, and may cause voids even when filled with resin.

Next, a resin film (connection layer) 40α is laminated on both sides of the laminated layer composed of the laminated plate 31α and the laminated plate 31β for accommodating the chip capacitor 20 (FIG. 1).
(C)). And it presses from both surfaces and makes a surface flat. Thereafter, the core substrate 30 including the housing layer 31 housing the chip capacitor 20 and the connection layer 40 is formed by heating and curing (FIG. 1D). In the present embodiment, the housing layer 31 housing the capacitor 20 and the connection layer 40
The pressure is applied to both surfaces to form the core substrate 30, so that the surface is flattened. Thereby, in a process described later, the interlayer resin insulating layer 6 is formed so as to have high reliability.
0 and the conductor circuit 68 can be stacked.

It is preferable that the side surface of the through hole 37 of the core substrate is filled with the resin filler 32a to improve the airtightness. Desirably, the resin filler 32a has a smaller coefficient of thermal expansion than the core substrate. Also, here, the resin film 4
Although a layer having no metal layer is used for 0α, a resin film (RCC) having a metal layer disposed on one side may be used. That is, a double-sided plate, a single-sided plate, a resin plate having no metal film, and a resin film can be used.

Next, a through hole 33 of 300 to 500 μm for a through hole is drilled in the interlayer resin insulating layer 40, the core substrate and the interlayer resin insulating layer 40 by drilling (FIG. 2).
(A)). Then, the first electrode 21 and the second electrode 21 of the chip capacitor 20 are applied to the interlayer resin insulation layer 40 on the upper surface side by a CO2 laser, a YAG laser, an excimer laser, or a UV laser.
A non-through hole 43 is formed to reach the electrode 22 (see FIG. 2).
(B)). In some cases, an area mask having a through hole may be placed in correspondence with the position of the non-through hole to perform the area processing with a laser. Further, in the case where via holes having different sizes and diameters are formed, they may be formed by a mixed laser. At this time, the conductive paste 26
Accordingly, the surfaces of the electrodes 21 and 22 of the chip capacitor 20 are smooth, so that the resin does not remain on the electrodes.

Thereafter, a desmear process is performed. Continued
After applying the palladium catalyst on the surface, the core substrate 30 is immersed in the electroless plating solution to uniformly deposit the electroless copper plating film 44 (FIG. 2C). A roughened layer can be formed on the surface of the electroless copper plating film 44. The roughened layer has Ra (average roughness height) = 0.01 to 5 μm. Particularly desirable is a range of 0.5 to 3 μm. At this time, since no resin remains on the surfaces of the electrodes 21 and 22 of the chip capacitor 20, the electroless copper plating film 44 can be appropriately formed on the electrodes 21 and 22.

Then, a photosensitive dry film is stuck on the surface of the electroless plating film 44, a mask is placed, and exposure and development are performed to form a resist 51 having a predetermined pattern (FIG. 3A). Here, electroless plating is used, but it is also possible to form a metal film of copper, nickel, or the like by sputtering. Sputtering is disadvantageous in cost, but has the advantage of improving the adhesion to the resin. And
The core substrate 30 is immersed in the electrolytic plating solution, and a current is passed through the electroless plating film 44 to deposit the electrolytic copper plating film 45 (FIG. 3B). Then, the resist 51 is replaced with 5% KOH
Then, the electroless plating film 44 under the resist 51 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, the non-through hole 43 of the interlayer resin insulating layer 40 is provided with the via hole 46, and the surface of the connection layer 40 is provided. In the conductor circuit 48, a through hole 36 is formed in the through hole 33 of the core substrate 30 (FIG. 3C).

A roughened layer is provided on the surface of the conductor layer of the conductor circuit 48, the via hole 46, and the through hole 36. The roughened layer is formed by an oxidation (blackening) -reduction treatment, an electroless plating film of an alloy made of Cu-Ni-P, or an etching treatment of an etching solution containing a cupric complex and an organic acid salt. The roughened layer has Ra (average roughness height) = 0.01 to
5 μm. Particularly desirable is a range of 0.5 to 3 μm. Although the roughened layer is formed here, it is also possible to directly fill the resin and attach a resin film as described later without forming the roughened layer.

Subsequently, the resin layer 3 is formed in the through hole 36.
8 is filled. As the resin layer, either a resin having no conductivity such as a resin such as an epoxy resin as a main component or a conductive resin containing a metal paste such as copper may be used. In this case, the thermosetting epoxy resin is filled with a material such as silica which is included for matching the coefficient of thermal expansion as a resin filler. After filling the through hole 36 with the resin 38,
The resin film 60α is attached (FIG. 4A). Note that a resin may be applied instead of attaching a resin film. After attaching the resin film 60α, the opening diameter 20 is formed in the insulating layer 60α by photo and laser.
A via hole 63 having a thickness of about 250 μm is formed and then thermally cured (FIG. 4B). Thereafter, a catalyst is applied to the core substrate, and the core substrate is immersed in the electroless plating to uniformly deposit an electroless plating film 64 having a thickness of 0.9 μm on the surface of the interlayer resin insulating layer 60. 70 (FIG. 4C).

Immersion in the electrolytic plating solution, the electroless plating film 6
A current is passed through the substrate 4 to form an electrolytic copper plating film 65 on the non-formed portion of the resist 70 (FIG. 5A). Resist 7
Then, the electroless plating film 64 under the plating resist is dissolved and removed, and the conductor circuit 68 including the electroless plating film 64 and the electrolytic copper plating film 65 and the via hole 6 are removed.
6 is obtained (FIG. 5B).

A roughened surface (not shown) was formed on the surfaces of the conductor circuit 68 and the via hole 66 by using an etching solution containing a second copper complex and an organic acid. In addition, Sn on the surface
Substitutions may be made.

A solder bump is formed on the above-mentioned printed wiring board. After applying a solder resist composition to both sides of the substrate and performing a drying process, a photomask film (not shown) on which a circular pattern (mask pattern) is drawn is placed in close contact with the substrate, and is exposed to ultraviolet light. And developing. Further, a heat treatment is further performed to form a solder resist layer (thickness: 20 μm) 72 having an opening 72a in a solder pad portion (including a via hole and a land portion thereof) (FIG. 5C).

Then, the solder paste is filled into the openings 72a of the solder resist layer 72 (not shown). Thereafter, the solder filled in the opening 72a is reflowed at 200 ° C. to form a solder bump (solder body) 76 (see FIG. 6). In order to improve corrosion resistance, a metal layer such as Ni, Au, Ag, or Pd may be formed in the opening 72a by plating or sputtering.

Next, mounting of the IC chip on the printed wiring board and mounting on the daughter board will be described with reference to FIG. Solder pads 92S1, 9 of IC chip 90 are applied to solder bumps 76 of completed printed wiring board 10.
The IC chip 90 is mounted so that the 2S2, 92P1, and 92P2 correspond to each other, and the IC chip 90 is attached by performing reflow. Similarly, the pads 96S1 of the daughter board 94 are attached to the solder bumps 76 of the printed wiring board 10,
By reflowing 96S2, 96P1, 96P2,
The printed wiring board 10 is attached to the daughter board 94.

Next, a printed wiring board according to a modification of the first embodiment of the present invention will be described with reference to FIG. The printed wiring board of the modified example is substantially the same as the above-described first embodiment. However, in the printed wiring board of this modified example, the conductive pins 84 are provided, and are formed so as to be connected to the daughter board via the conductive pins 84.

FIG. 14B shows a cross section of a chip capacitor 20 according to a first modification. In the first embodiment, the surface of the capacitor is subjected to a roughening treatment to improve the adhesiveness with the resin. However, in a modified example, a polyimide film 23b is formed instead to improve the surface wettability. And adhesive 32
Further, the adhesion to the interlayer resin insulating layer 40 is enhanced, and peeling of the interlayer resin insulating layer 40 is prevented. Instead of the polyimide film, the surface of the capacitor may be subjected to a silane coupling treatment.

In the first modification, the conductive paste 2
6, a composite metal film 28 composed of an electroless copper plating film 28a and an electrolytic copper plating film 28b is formed. The thickness of the composite metal film 28 is desirably 0.1 to 10 μm.
５5 μm is optimal. Instead of a composite metal film, it is also possible to form a single-layer metal film.

In the first modified example, the electrode 2 of the capacitor 20
Since the metal layer 28 is provided on the conductive pastes 1 and 22, the occurrence of migration at the electrodes 21 and 22 can be prevented, and the connection resistance can be further reduced. The electrodes 21 and 22 made of metallization have irregularities on the surface. However, by applying a conductive paste 26 and further providing a metal layer 28, the irregularities can be completely eliminated. Adhesion can be enhanced and connection resistance can be reduced.

In the first embodiment described above, only the chip capacitor 20 housed in the core substrate 30 is provided. However, in the first modification, a large-capacity chip capacitor 86 is mounted on the front and back surfaces. I have.

The IC chip instantaneously consumes a large amount of power and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in the first modified example, the chip capacitor 20 and the chip capacitor 8 for power supply are mounted on the printed wiring board.
6 is provided. The effect of this chip capacitor will be described with reference to FIG.

FIG. 15 shows the voltage supplied to the IC chip on the vertical axis and the time on the horizontal axis. Here, the two-dot chain line C
Indicates voltage fluctuation of a printed wiring board without a power supply capacitor. When the power supply capacitor is not provided, the voltage greatly decreases. A broken line A indicates a voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. Although the voltage does not drop much as compared with the two-dot chain line C, the rate-limiting power supply cannot be performed sufficiently because the loop length is long. That is, the voltage drops at the start of power supply. A two-dot chain line B indicates a voltage drop of the printed wiring board including the chip capacitor described above with reference to FIG. Although the loop length has been shortened,
Since a large-capacity chip capacitor cannot be accommodated in the core substrate 30, the voltage fluctuates. here,
A solid line E indicates the voltage fluctuation of the printed wiring board of the first modification in which the chip capacitor 20 in the core substrate described above with reference to FIG. 8 and the large-capacity chip capacitor 86 are mounted on the surface. By providing the chip capacitor 20 near the IC chip and the chip capacitor 86 having a large capacity (and a relatively large inductance), voltage fluctuation is minimized.

Next, a printed wiring board according to a second modification of the first embodiment of the present invention will be described with reference to FIG. The printed wiring board of the second modified example is almost the same as the above-described first embodiment. However, in the first embodiment, the connection layers 40 are provided on both sides of the core substrate 30 of the housing layer 31, but in the second embodiment, the connection layers 40 are provided only on the upper surface of the housing layer 31. . In addition, the conductive paste and the electrode of the chip capacitor are provided in the same manner as in the first embodiment.
Alternatively, similarly to the first modification of the first embodiment, the conductive paste and the composite metal layer are formed.

The manufacturing process of the printed wiring board according to the second modification of the first embodiment will be described with reference to FIGS. First, a through hole 37 for accommodating a chip capacitor is formed in a laminated plate 31α formed by laminating four prepregs 35 impregnated with epoxy resin, and a laminated plate 31β formed by laminating two prepregs 35 is prepared. (FIG. 9
(A)). Next, the chip capacitor 20 is mounted on the laminated plate 31β via the adhesive 32 so as to correspond to the through hole forming position of the laminated plate 31α (FIG. 9B). And the laminate 3
1α and the laminated plate 31β are overlapped to form the housing layer 31 of the chip capacitor 20 (FIG. 9C).

Next, a resin film (connection layer) 40α is laminated on the upper surface of the accommodation layer 31 composed of the laminate 31α and the laminate 31β accommodating the chip capacitor 20 (FIG. 9D). And it presses from both surfaces and makes a surface flat. Thereafter, the core substrate 30 including the housing layer 31 housing the chip capacitor 20 and the connection layer 40 is formed by heating and curing (FIG. 10A). In the present embodiment, the housing layer 31 housing the capacitor 20 and the connection layer 40 are bonded to each other by applying pressure to both surfaces to form the core substrate 30, so that the surface is flattened. Thereby, the interlayer resin insulating layer 60 and the conductor circuit 68 can be laminated so as to have high reliability.

Next, a through hole 33 of 300 to 500 μm for a through hole is formed in the interlayer resin insulating layer 40, the core substrate and the interlayer resin insulating layer 40 by drilling (FIG. 10).
(B)). Then, the first electrode 21 and the second electrode 21 of the chip capacitor 20 are applied to the interlayer resin insulation layer 40 on the upper surface side by a CO2 laser, a YAG laser, an excimer laser, or a UV laser.
A non-through hole 43 leading to the electrode 22 is formed (FIG. 10).
(C)). Subsequent steps are the same as in the first embodiment described above with reference to FIGS.

Next, a printed wiring board according to a third modification of the first embodiment of the present invention will be described with reference to FIG. The printed wiring board of the second modification is substantially the same as the second modification of the above-described first embodiment. However, the second
In the modified example, the via hole 46 is provided only on the IC chip side of the core substrate 30, but in the third modified example, the via hole 46 is provided not only on the IC chip side but also on the daughter board side.
Are arranged. A conductive paste is formed on the electrode of the chip capacitor as in the first embodiment, or a conductive paste and a composite metal layer are formed as in the first modification of the first embodiment.

In the third modification, since the via hole 46 is provided also on the back surface side, the wiring length between the chip capacitor 20 and the daughter board can be shortened.

A manufacturing process of a printed wiring board according to the third modification will be described with reference to FIG. First, through holes 37 for accommodating chip capacitors are formed in a laminated plate 31α formed by laminating four prepregs 35 impregnated with epoxy resin. On the other hand, a through-hole 39 leading to an electrode is formed at a chip capacitor mounting position of a laminated plate 31β formed by laminating two prepregs 35 (FIG. 12A). Next, the laminated plate 31β
Of the adhesive 3 corresponding to the through hole forming position of the laminated plate 31α.
The chip capacitor 20 is placed via the second capacitor 2 (FIG. 12).
(B)). Then, the laminated plate 31α and the laminated plate 31β are overlapped to form the accommodation layer 31 (FIG. 12C).

Next, a resin film (connection layer) 40α is laminated on the upper surface of the housing layer 31 (FIG. 12D). And it presses from both surfaces and makes a surface flat. Thereafter, the core substrate 30 including the housing layer 31 housing the chip capacitor 20 and the connection layer 40 is formed by heating and curing (see FIG. 13). Subsequent steps are the same as in the first embodiment described above with reference to FIGS.

Next, the configuration of the printed wiring board according to the second embodiment of the present invention will be described with reference to FIG. The configuration of the printed wiring board of the second embodiment is substantially the same as that of the above-described first embodiment. However, the core substrate 3
The chip capacitors 20 housed to 0 are different. Figure 1
6 shows a plan view of the chip capacitor. FIG.
(A) shows a chip capacitor for multi-piece cutting before cutting, and a dashed line in the drawing shows a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are provided on the side edges of the chip capacitor as shown in the plan view of FIG. FIG. 16 (C)
Shows a chip capacitor for multi-cavity before cutting according to the second embodiment, and a dashed line in the drawing indicates a cutting line. In the printed wiring board of the second embodiment, FIG.
As shown in the plan view, a first electrode 21 and a second electrode 22 are provided inside the side edge of the chip capacitor. In addition,
A conductive paste is formed on the electrode of the chip capacitor as in the first embodiment, or a conductive paste and a composite metal layer are formed as in the first modification of the first embodiment.
In the printed wiring board of the second embodiment, since the chip capacitor 20 having the electrode formed inside the outer edge is used,
A chip capacitor having a large capacity can be used.

Subsequently, a printed wiring board according to a first modification of the second embodiment will be described with reference to FIG.
FIG. 17 is a plan view of the chip capacitor 20 housed in the core substrate of the printed wiring board according to the first modification. In the above-described first embodiment, a plurality of small-capacity chip capacitors are housed in the core substrate. In the first modification, a large-capacity large-format chip capacitor 20 is housed in the core substrate. Here, the chip capacitor 20 is
The electrode 21, the second electrode 22, the dielectric 23, and the first electrode 2
1, a second conductive film 25 connected to the second electrode 22 side, and upper and lower surfaces of a chip capacitor not connected to the first conductive film 24 and the second conductive film 25. And a connection electrode 27. The IC chip side and the daughter board side are connected via the electrodes 27. A conductive paste is formed on the electrode of the chip capacitor as in the first embodiment, or a conductive paste and a composite metal layer are formed as in the first modification of the first embodiment.

In the printed wiring board of the first modified example, since the large-sized chip capacitor 20 is used, a large-capacity chip capacitor can be used. Further, since the large chip capacitor 20 is used, the printed wiring board does not warp even if the heat cycle is repeated.

A printed wiring board according to a second modification will be described with reference to FIG. FIG. 18A shows a chip capacitor before cutting for multi-cavity cutting, in which a dashed line indicates a normal cutting line, and FIG. 18B shows a plan view of the chip capacitor. . As shown in FIG. 18B, in the second modification, a plurality of chip capacitors (three in the example in the figure) for multi-cavity are connected and used in a large format. The first electrode of the chip capacitor
A conductive paste and a composite metal layer are formed as in the embodiment, or as in the first modification of the first embodiment.

In the second modification, a large-sized chip capacitor 20 is used, so that a large-capacity chip capacitor can be used. Further, since the large chip capacitor 20 is used, the printed wiring board does not warp even if the heat cycle is repeated.

In the above-described embodiment, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, it is also possible to use a plate-like capacitor in which a conductive film is provided on a ceramic plate.

Here, with respect to the printed wiring board of the first embodiment, the chip capacitor 20 embedded in the core substrate is used.
And the inductance of the chip capacitor mounted on the back surface of the printed wiring board (the surface on the daughter board side) are shown. In case of single capacitor Embedded type 137pH Backside mounted type 287pH When 8 capacitors are connected in parallel Embedded type 60pH Backside mounted type 72pH As shown above, when using a single capacitor, it is connected in parallel to increase the capacity In addition, the inductance can be reduced by incorporating a chip capacitor.

Next, the results of the reliability test will be described. Here, the rate of change of the capacitance of one chip capacitor in the printed wiring board of the first embodiment was measured. Capacitance change rate (measuring frequency 100Hz) (measuring frequency 1kHz) Steam 168 hours: 0.3% 0.4% HAST 100 hours: -0.9% -0.9% TS 1000cycles: 1.1% 1.3%

In the steam test, the humidity was adjusted to 100% by exposure to steam. In the HAST test, the relative humidity was 100%,
It was left at an applied voltage of 1.3 V and a temperature of 121 ° C. for 100 hours. In the TS test, 30 minutes at -125 ° C and 30 minutes at 55 ° C
The test of standing for 1000 minutes was repeated 1000 times.

In the above reliability test, it was found that a printed wiring board having a built-in chip capacitor could achieve the same reliability as an existing capacitor surface mount type. As described above, in the TS test,
Due to the difference in the coefficient of thermal expansion between the ceramic capacitor and the resin core substrate and interlayer resin insulation layer, even if internal stress occurs, disconnection between the chip capacitor terminal and the via hole, chip capacitor and interlayer resin It has been found that high reliability can be achieved for a long period without peeling from the insulating layer or cracking in the interlayer resin insulating layer.

[0109]

According to the structure of the present invention, the electric characteristics caused by the inductance do not decrease. Further, since the conductive paste is applied to the surfaces of the electrodes of the capacitor, the surface becomes completely flat. Therefore, when an opening is formed in the resin layer by laser, the resin does not remain on the surface of the electrode, and the connection reliability between the electrode and the via hole by plating can be improved. Further, since the resin is filled between the core substrate and the capacitor, even if stress caused by the capacitor or the like is generated, the stress is reduced and migration does not occur. Therefore, there is no influence such as peeling or melting of the connection portion between the electrode of the capacitor and the via hole. Therefore, desired performance can be maintained even if a reliability test is performed. Also, even when the electrodes of the capacitor are covered with copper, the occurrence of migration can be prevented.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view of the printed wiring board according to the first embodiment.

FIG. 7 is a cross-sectional view of the printed wiring board according to the first embodiment.

FIG. 8 is a cross-sectional view of a printed wiring board according to a first modification of the first embodiment.

FIG. 9 is a manufacturing process diagram of a printed wiring board according to a second modification of the first embodiment.

FIG. 10 is a manufacturing process diagram of the printed wiring board according to the second modified example of the first embodiment.

FIG. 11 is a cross-sectional view of a printed wiring board according to a second modification of the first embodiment.

FIG. 12 is a manufacturing process diagram of the printed wiring board according to the third modified example of the first embodiment.

FIG. 13 is a cross-sectional view of a printed wiring board according to a third modification of the first embodiment.

FIG. 14A is a cross-sectional view of a chip capacitor according to the first embodiment, and FIG. 14B is a cross-sectional view of a chip capacitor according to a first modification of the first embodiment.

FIG. 15 is a graph showing changes in supply voltage to an IC chip and time.

FIGS. 16A, 16B, 16C, and 16D are plan views of a chip capacitor of a printed wiring board according to a second embodiment.

FIG. 17 is a plan view of a chip capacitor of a printed wiring board according to a first modification of the second embodiment.

FIGS. 18A and 18B are plan views of a chip capacitor of a printed wiring board according to a second modification of the second embodiment.

FIGS. 19A and 19B are explanatory diagrams of a loop inductance of a printed wiring board according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Printed wiring board 20 Chip capacitor 21 First electrode 22 Second electrode 23 Dielectric 23a Roughened surface 23b Polyimide film 26 Conductive paste 28a Electroless copper plating film 28b Electrolytic copper plating film 28 Composite metal film 30 Core substrate 31 Housing layer 36 Through hole 37 Through hole 39 Through hole 40 Connection layer 43 Non-through hole 46 Via hole 48 Conductor circuit 60 Interlayer resin insulation layer 66 Via hole 68 Conductor circuit 84 Conductive pin 90 IC chip 94 Daughter board

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E336 AA04 AA08 AA16 BB03 BB15 BC02 BC26 CC32 CC36 CC43 CC53 CC55 DD28 EE07 EE08 EE17 GG05 GG09 GG11 GG16 5E346 AA12 AA15 AA32 AA43 AA51 BB16 BB20 CC33 EE EE DD EE FF04 FF07 FF13 FF14 FF17 FF18 FF45 GG15 GG17 GG18 GG19 GG22 GG27 GG28 HH02 HH31

Claims (19)

[Claims] 1. A printed wiring board comprising a resin insulating layer and a conductive circuit laminated on a core substrate, wherein the core substrate comprises a connection layer formed of at least one or more insulating resin layers, and a capacitor. And a housing layer made of two or more resin layers housed therein.
A printed wiring board to which a conductive paste is applied. 2. A printed wiring board comprising a resin insulating layer and a conductor circuit laminated on a core substrate, wherein the core substrate includes a connection layer formed of at least one or more insulating resin layers, and a capacitor. It is composed of an encasing layer composed of two or more resin layers that are accommodated and formed on both sides with vias to be connected to the capacitor.
A printed wiring board to which a conductive paste is applied. 3. The printed wiring board according to claim 1, wherein a metal layer is provided on the conductive paste of the electrodes of the capacitor. 4. The capacitor according to claim 1, wherein the surface of the capacitor is subjected to a roughening treatment.
Printed wiring board. 5. The capacitor according to claim 1, wherein the surface of the capacitor is subjected to a surface wettability improving treatment.
Any one of the printed wiring boards. 6. The printed wiring board according to claim 1, wherein the via hole formed in the core substrate is made of a metal film selected from plating, sputtering, and vapor deposition. 7. The printed wiring board according to claim 1, wherein the housing layer and the capacitor are joined with an insulating adhesive. 8. The printed wiring according to claim 1, wherein a plurality of the capacitors are accommodated, and a wiring for connecting an IC chip and an external substrate is provided between the capacitors. Board. 9. The printed circuit board according to claim 1, wherein a capacitor is mounted on a surface of the printed wiring board.
A printed wiring board according to claim 1. 10. The printed wiring board according to claim 9, wherein the capacitance of the chip capacitor on the front surface is equal to or larger than the capacitance of the chip capacitor in the inner layer. 11. The printed wiring board according to claim 9, wherein the inductance of the chip capacitor on the surface is equal to or greater than the inductance of the chip capacitor in the inner layer. 12. The printed wiring board according to claim 1, wherein a chip capacitor having an electrode formed inside an outer edge is used as the capacitor. 13. The printed wiring board according to claim 1, wherein a chip capacitor having electrodes formed in a matrix is used as said capacitor. 14. The printed wiring board according to claim 1, wherein a plurality of chip capacitors for multi-cavity are connected and used as said capacitor. 15. The printed wiring board according to claim 4, wherein the insulating adhesive has a lower coefficient of thermal expansion than the housing layer. 16. A method for producing a printed wiring board, comprising at least the following steps (a) to (e): (a) a capacitor containing resin in a core material in a first resin material; Forming a through-hole; (b) attaching a second resin material to the first resin material having the through-hole to form a housing layer having a capacitor housing portion; (E) a step of housing a capacitor having a conductive paste applied on the metallized electrode in the housing layer; (d) a step of attaching a third insulating resin layer to the housing layer in the step (c) to form a core substrate; Forming a via hole in the third insulating resin layer to reach an electrode of the capacitor; 17. A method of manufacturing a printed wiring board, comprising at least the following steps (a) to (e): (a) a capacitor material is contained in a first resin material having a core material containing a resin; (B) disposing a capacitor in which a conductive paste is applied on a metallized electrode at a position corresponding to a capacitor accommodating portion of the first resin material in a second resin material; (C) a step of pasting the first resin material having undergone the step (a) and the second resin material having undergone the step (b) to form a housing layer housing the capacitor; and (d) the housing layer. (E) forming an opening to the electrode of the capacitor in the third insulating resin layer to form a via hole. 18. A method for manufacturing a printed wiring board, comprising at least the following steps (a) to (f): (a) A capacitor is contained in a first resin material having a core material containing a resin. (B) forming a through hole as a via hole in the second resin material, and forming a conductive paste on the metallized electrode at a position corresponding to the capacitor housing portion of the first resin material; (C) adhering the first resin material having passed through the step (a) and the second resin material having passed through the step (b) to form a housing layer containing the capacitor (D) attaching a third insulating resin layer to the housing layer to form a core substrate; (e) providing an opening to the capacitor electrode in the third insulating resin layer; (f) Of the first resin material Forming a conductive film in the through hole and the opening of the third resin material to form a via hole; 19. The method according to claim 16, wherein pressure is applied to both surfaces of the substrate during the attaching in the step (d).
A method for manufacturing a printed wiring board according to claim 1.