JP2001339165A - Multilayer printed wiring board and package board - Google Patents

Multilayer printed wiring board and package board

Info

Publication number
JP2001339165A
JP2001339165A JP2000388457A JP2000388457A JP2001339165A JP 2001339165 A JP2001339165 A JP 2001339165A JP 2000388457 A JP2000388457 A JP 2000388457A JP 2000388457 A JP2000388457 A JP 2000388457A JP 2001339165 A JP2001339165 A JP 2001339165A
Authority
JP
Japan
Prior art keywords
resin
chip
printed wiring
layer
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000388457A
Other languages
Japanese (ja)
Other versions
JP4854845B2 (en
Inventor
Hajime Sakamoto
一 坂本
Sunao Sugiyama
直 杉山
Touto O
東冬 王
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP2000388457A priority Critical patent/JP4854845B2/en
Publication of JP2001339165A publication Critical patent/JP2001339165A/en
Application granted granted Critical
Publication of JP4854845B2 publication Critical patent/JP4854845B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board in which electrical connection can be made directly with an IC chip not through a lead part. SOLUTION: The multilayer printed wiring board previously incorporates an IC chip 20 in a core substrate 30 and a transition layer 38 is arranged on the die pad 24 of the IC chip 20. Consequently, electrical connection can be made between the IC chip and the multilayer printed wiring board without requiring any lead part or sealing resin. Since the transition layer 38 is provided on the die pad 24, a build-up layer can be stacked even if the die pad 24 has a fine pitch (150 μm) and/or a small size (20 μm or less) while enhancing connectability and reliability of the die pad 24 and via holes 60.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ビルドアップ多層
プリント配線板に関し、特にＩＣチップなどの電子部品
を内蔵する多層プリント配線板及びパッケージ基板に関
するのもである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a build-up multilayer printed wiring board, and more particularly to a multilayer printed wiring board and a package substrate in which electronic components such as IC chips are built.

【０００２】[0002]

【従来の技術】ＩＣチップは、ワイヤーボンディング、
ＴＡＢ、フリップチップなどの実装方法によって、プリ
ント配線板との電気的接続を取っていた。ワイヤーボン
ディングは、プリント配線板にＩＣチップを接着剤によ
りダイボンディングさせて、該プリント配線板のパッド
とＩＣチップのパッドとを金線などのワイヤーで接続さ
せた後、ＩＣチップ並びにワイヤーを守るために熱硬化
性樹脂あるいは熱可塑性樹脂などの封止樹脂を施してい
た。ＴＡＢは、ＩＣチップのバンプとプリント配線板の
パッドとをリードと呼ばれる線を半田などによって一括
して接続させた後、樹脂による封止を行っていた。フリ
ップチップは、ＩＣチップとプリント配線板のパッド部
とをバンプを介して接続させて、バンプとの隙間に樹脂
を充填させることによって行っていた。2. Description of the Related Art IC chips are manufactured by wire bonding,
The electrical connection with the printed wiring board has been established by a mounting method such as TAB or flip chip. Wire bonding is to bond the IC chip to the printed wiring board with an adhesive and connect the pad of the printed wiring board and the pad of the IC chip with a wire such as a gold wire, and then to protect the IC chip and the wire. To a sealing resin such as a thermosetting resin or a thermoplastic resin. In TAB, after a wire called a lead is collectively connected between a bump of an IC chip and a pad of a printed wiring board by soldering or the like, sealing with resin is performed. The flip chip has been performed by connecting an IC chip and a pad portion of a printed wiring board via a bump, and filling a gap between the bump and the resin with a resin.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、それぞ
れの実装方法は、ＩＣチップとプリント配線板の間に接
続用のリード部品（ワイヤー、リード、バンプ）を介し
て電気的接続を行っている。それらの各リード部品は、
切断、腐食し易く、これにより、ＩＣチップとの接続が
途絶えたり、誤作動の原因となることがあった。また、
それぞれの実装方法は、ＩＣチップを保護するためにエ
ポキシ樹脂等の熱可塑性樹脂によって封止を行っている
が、その樹脂を充填する際に気泡を含有すると、気泡が
起点となって、リード部品の破壊やＩＣパッドの腐食、
信頼性の低下を招いてしまう。熱可塑性樹脂による封止
は、それぞれの部品に合わせて樹脂装填用プランジャ
ー、金型を作成する必要が有り、また、熱硬化性樹脂で
あってもリード部品、ソルダーレジストなどの材質など
を考慮した樹脂を選定しなくては成らないために、それ
ぞれにおいてコスト的にも高くなる原因にもなった。However, in each mounting method, an electrical connection is made between the IC chip and the printed wiring board via a connecting lead component (wire, lead, bump). Each of those lead components
They are easily cut and corroded, which may cause the connection with the IC chip to be interrupted or cause a malfunction. Also,
In each mounting method, sealing is performed with a thermoplastic resin such as epoxy resin to protect the IC chip. However, if the resin is filled with air bubbles, the air bubbles become a starting point, and the lead component becomes Damage, IC pad corrosion,
This leads to a decrease in reliability. For sealing with thermoplastic resin, it is necessary to create a resin loading plunger and mold according to each part, and even for thermosetting resin, consider materials such as lead parts and solder resist Since it is necessary to select a suitable resin, the cost of each resin is also increased.

【０００４】本発明は上述した課題を解決するためにな
されたものであり、その目的とするところは、リード部
品を介さないで、ＩＣチップと直接電気的接続し得る多
層プリント配線板及びパッケージ基板を提案することを
目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a multilayer printed wiring board and a package board which can be directly electrically connected to an IC chip without using lead components. The purpose is to propose.

【０００５】[0005]

【課題を解決するための手段】本発明者は鋭意研究した
結果、樹脂絶縁性基板に開口部、通孔やザグリ部を設け
てＩＣチップなどの電子部品を予め内蔵させて、層間絶
縁層を積層し、該ＩＣチップのパッド上に、フォトエッ
チングあるいはレーザにより、ビアを設けて、導電層で
ある導体回路を形成させた後、更に、層間絶縁層と導電
層を繰り返して、多層プリント配線板を設けることによ
って、封止樹脂を用いず、リードレス、バンプレスによ
ってＩＣチップとの電気的接続を取ることができる構造
を案出した。Means for Solving the Problems As a result of earnest study, the present inventors have provided an opening, a through hole and a counterbore portion in a resin insulating substrate to previously incorporate electronic components such as IC chips, and to form an interlayer insulating layer. After laminating and providing vias on the pads of the IC chip by photoetching or laser to form a conductive circuit as a conductive layer, the interlayer insulating layer and the conductive layer are further repeated to form a multilayer printed wiring board. By devising such a structure, a structure was devised in which electrical connection with an IC chip can be established by a leadless or bumpless method without using a sealing resin.

【０００６】更に、本発明者は、樹脂絶縁性基板に開口
部、通孔やザグリ部を設けてＩＣチップなどの電子部品
を予め内蔵させて、層間絶縁層を積層し、該ＩＣチップ
のパッド上に、フォトエッチングあるいはレーザによ
り、ビアを設けて、導電層である導体回路を形成させた
後、更に、層間絶縁層と導電層を繰り返して、多層プリ
ント配線板の表層にもＩＣチップ、コンデンサなどの電
子部品を実装させた構造を提案した。それによって、封
止樹脂を用いず、リードレス、バンプレスによってＩＣ
チップとの電気的接続を取ることができる。また、それ
ぞれの機能が異なるＩＣチップ、コンデンサなどの電子
部品を実装させることができ、より高機能な多層プリン
ト配線板を得ることができる。具体例として、内蔵ＩＣ
チップとして演算機能を有するＩＣチップを埋め込み、
表層には、キャシュメモリ、コンデンサを実装させるこ
とによって、ＩＣチップとキャシュメモリ、コンデンサ
とを近接して配置することが可能になる。Further, the inventor of the present invention has provided an opening, a through-hole, and a counterbore portion in a resin insulating substrate to previously incorporate an electronic component such as an IC chip, laminated an interlayer insulating layer, and provided a pad for the IC chip. Vias are formed on the upper surface by photoetching or laser to form a conductive circuit that is a conductive layer. Then, the interlayer insulating layer and the conductive layer are repeated, and an IC chip and a capacitor are also formed on the surface layer of the multilayer printed wiring board. We have proposed a structure in which electronic components such as are mounted. As a result, ICs can be formed by leadless and bumpless without using sealing resin.
An electrical connection with the chip can be established. Further, electronic components such as IC chips and capacitors having different functions can be mounted, and a higher-performance multilayer printed wiring board can be obtained. As a specific example, built-in IC
Embedding an IC chip having an arithmetic function as a chip,
By mounting a cache memory and a capacitor on the surface layer, the IC chip and the cache memory and the capacitor can be arranged close to each other.

【０００７】また更に、本発明者は、鋭意研究した結
果、樹脂絶縁性基板に開口部、通孔やザグリ部を設けて
ＩＣチップなどの電子部品を予め収容させて、該ＩＣチ
ップのパッドには導電層からなるトラジション層を形成
させることを案出した。トラジション層の上層には層間
絶縁層を積層し、該トラジション層上に、フォトエッチ
ングあるいはレーザにより、ビアを設けて、導電層であ
る導体回路を形成させた後、更に、層間絶縁層と導電層
を繰り返して、多層プリント配線板を設けることによっ
て、封止樹脂を用いず、リードレス、バンプレスによっ
てＩＣチップとの電気的接続を取ることができる。ま
た、ＩＣチップ部分にトラジション層が形成されている
ことから、ＩＣチップ部分には平坦化されるので、上層
の層間絶縁層も平坦化されて、膜厚みも均一になる。更
に、前述のトラジション層によって、上層のビアを形成
する際も、形状の安定性を保つことができる。Further, as a result of diligent research, the present inventor has provided an opening, a through hole, and a counterbore portion in a resin insulating substrate to accommodate electronic components such as an IC chip in advance, and to attach the electronic component to a pad of the IC chip. Devised to form a transition layer composed of a conductive layer. An interlayer insulating layer is stacked on the transition layer, a via is provided on the transition layer by photoetching or laser, and a conductive circuit as a conductive layer is formed. By providing the multilayer printed wiring board by repeating the conductive layer, electrical connection with the IC chip can be obtained by leadless or bumpless without using a sealing resin. Further, since the transition layer is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer is also flattened and the film thickness becomes uniform. Further, the above-mentioned transition layer can maintain the shape stability even when an upper via is formed.

【０００８】本発明で定義されるトランジション層につ
いて説明する。トランジション層は、従来のＩＣチップ
実装技術を用いることなく、半導体素子であるＩＣチッ
プとプリント配線板と直接接続を取るために設けられた
中間の仲介層を意味する。特徴としては、２層以上の金
属層で形成され、半導体素子であるＩＣチップのダイパ
ッドよりも大きくさせることにある。それによって、電
気的接続や位置合わせ性を向上させるものであり、か
つ、ダイパッドにダメージを与えることなくレーザやフ
ォトエッチングによるバイアホール加工を可能にするも
のである。そのため、プリント配線板へのＩＣチップの
埋め込み、収容、収納や接続を確実にすることができ
る。また、トランジション層上には、直接、プリント配
線板の導体層である金属を形成することを可能にする。
その導体層の一例としては、層間樹脂絶縁層のバイアホ
ールや基板上のスルーホールなどがある。The transition layer defined in the present invention will be described. The transition layer means an intermediate mediation layer provided for directly connecting an IC chip as a semiconductor element and a printed wiring board without using a conventional IC chip mounting technique. It is characterized in that it is formed of two or more metal layers and is larger than a die pad of an IC chip as a semiconductor element. Thereby, electrical connection and alignment are improved, and via holes can be formed by laser or photoetching without damaging the die pad. Therefore, embedding, accommodation, accommodation, and connection of the IC chip in the printed wiring board can be ensured. In addition, it is possible to directly form a metal which is a conductor layer of a printed wiring board on the transition layer.
Examples of the conductor layer include via holes in an interlayer resin insulating layer and through holes on a substrate.

【０００９】ＩＣチップのパッドにトラジション層を設
ける理由は、次の通りである。第１にダイパッドがファ
インかつ小サイズになると、ビアを形成する際のアライ
メントが困難になるので、トラジション層を設けてアラ
イメントをし易くする。トラジション層を設ければ、ダ
イパッドピッチ１５０μｍ以下、パッドサイズ２０μｍ
以下でもビルドアップ層が安定して形成できる。トラジ
ション層を形成させていないダイパッドのままで、フォ
トエッチングにより層間絶縁層のビアを形成させると、
ビア径がダイパッド径よりも大きいと、ビア底残査除
去、層間樹脂絶縁層表面粗化処理として行うデスミア処
理時に、ダイパッド表面の保護層であるポリイミド層を
溶解、損傷する。一方、レーザの場合、ビア径がダイパ
ッド径より大きいときには、ダイパッド及びパシベーシ
ョン、ポリミド層（ＩＣの保護膜）がレーザによって破
壊される。更に、ＩＣチップのパッドが非常に小さく、
ビア径がダイパッドサイズより大きくなると、フォトエ
ッチング法でも、レーザ法でも位置合わせが非常に困難
であり、ダイパッドとビアとの接続不良が多発する。The reason why the transition layer is provided on the pad of the IC chip is as follows. First, when the die pad is fine and small, alignment becomes difficult when forming vias. Therefore, a transition layer is provided to facilitate alignment. If a transition layer is provided, the die pad pitch is 150 μm or less, and the pad size is 20 μm.
Even in the case below, the build-up layer can be formed stably. When the via of the interlayer insulating layer is formed by photoetching with the die pad without forming the transition layer,
If the via diameter is larger than the die pad diameter, the polyimide layer, which is the protective layer on the die pad surface, is dissolved and damaged during the desmear process performed as the via bottom residue removal and interlayer resin insulating layer surface roughening processes. On the other hand, in the case of laser, when the via diameter is larger than the die pad diameter, the die pad, passivation, and polyimide layer (protective film of IC) are destroyed by the laser. Furthermore, the pads of the IC chip are very small,
If the via diameter is larger than the die pad size, it is very difficult to align the photo-etching method and the laser method, and connection failure between the die pad and the via frequently occurs.

【００１０】これに対して、ダイパッド上にトラジショ
ン層を設けることで、ダイパッドピッチ１５０μｍ以
下、パッドサイズ２０μｍ以下になってもダイパッド上
にビアを確実に接続させることができ、パッドとビアと
の接続性や信頼性を向上させる。更に、ＩＣチップのパ
ッド上により大きな径のトラジション層を介在させるこ
とで、デスミヤ、めっき工程などの後工程の際に、酸や
エッチング液に浸漬させたり、種々のアニール工程を経
ても、ダイパッド及びＩＣの保護膜（パシベーション、
ポリミド層）を溶解、損傷する危険がなくなる。On the other hand, by providing the transition layer on the die pad, even if the die pad pitch becomes 150 μm or less and the pad size becomes 20 μm or less, the via can be reliably connected on the die pad, and the connection between the pad and the via Improve connectivity and reliability. Furthermore, by interposing a larger diameter transition layer on the pad of the IC chip, the die pad can be immersed in an acid or an etching solution during a post-process such as desmearing or a plating process, or subjected to various annealing processes. And IC protective film (passivation,
The risk of dissolving and damaging the polyimide layer) is eliminated.

【００１１】それぞれに多層プリント配線板だけで機能
を果たしてもいるが、場合によっては半導体装置として
のパッケージ基板としての機能させるために外部基板で
あるマザーボードやドーターボードとの接続のため、Ｂ
ＧＡ、半田バンプやＰＧＡ（導電性接続ピン）を配設さ
せてもよい。また、この構成は、従来の実装方法で接続
した場合よりも配線長を短くできて、ループインダクタ
ンスも低減できる。[0011] Each of them can function only by a multilayer printed wiring board. However, in some cases, in order to function as a package substrate as a semiconductor device, B is used for connection to an external substrate such as a motherboard or a daughter board.
GAs, solder bumps or PGAs (conductive connection pins) may be provided. In addition, with this configuration, the wiring length can be made shorter than in the case where the connection is made by the conventional mounting method, and the loop inductance can be reduced.

【００１２】本願発明に用いられるＩＣチップなどの電
子部品を内蔵させる樹脂製基板としては、エポキシ樹
脂、ＢＴ樹脂、フェノール樹脂などにガラスエポキシ樹
脂などの補強材や心材を含浸させた樹脂、エポキシ樹脂
を含浸させたプリプレグを積層させたものなどが用いら
れるが、一般的にプリント配線板で使用されるものを用
いることができる。それ以外にも両面銅張積層板、片面
板、金属膜を有しない樹脂板、樹脂フィルムを用いるこ
とができる。The resin substrate for incorporating electronic components such as an IC chip used in the present invention may be a resin in which a reinforcing material such as a glass epoxy resin or a core material is impregnated into an epoxy resin, a BT resin, a phenol resin, or the like, or an epoxy resin. A laminate of prepregs impregnated with is used, but those generally used for printed wiring boards can be used. In addition, a double-sided copper-clad laminate, a single-sided plate, a resin plate having no metal film, and a resin film can be used.

【００１３】ＩＣチップを内蔵させたコア基板の全面に
蒸着、スパッタリングなどの物理的な蒸着を行い、全面
に導電性の金属膜を形成させる。その金属としては、ス
ズ、クロム、チタン、ニッケル、亜鉛、コバルト、金、
銅などの金属を１層以上形成させるものがよい。厚みと
しては、０．００１〜２．０μｍの間で形成させるのが
よい。特に、０．０１〜１．０μｍが望ましい。A conductive metal film is formed on the entire surface of the core substrate in which the IC chip is built by physical vapor deposition such as evaporation or sputtering. The metals include tin, chromium, titanium, nickel, zinc, cobalt, gold,
It is preferable to form one or more layers of a metal such as copper. The thickness is preferably between 0.001 and 2.0 μm. In particular, 0.01 to 1.0 μm is desirable.

【００１４】また、セミアディテブプロセスでトラジシ
ョン層を形成する場合には、ＩＣチップ及びコア基板の
上に形成した金属膜上にドライフィルムレジストを形成
してトラジション層に該当する部分を除去させて、電解
めっきによって厚付けした後、レジストを剥離してエッ
チング液によって、同様にＩＣチップのパッド上にトラ
ジション層を形成させることもできる。When forming a transition layer by a semi-additive process, a dry film resist is formed on a metal film formed on an IC chip and a core substrate, and a portion corresponding to the transition layer is removed. Then, after thickening by electrolytic plating, the resist is peeled off, and a transition layer can be similarly formed on the pad of the IC chip with an etching solution.

【００１５】一方、サブトラプロセスでトラジション層
を形成する場合には、金属膜上に、無電解あるいは電解
めっきにより、厚付けさせる。形成されるメッキの種類
としては銅、ニッケル、金、銀、亜鉛、鉄などがある。
電気特性、経済性、また、後程で形成されるビルドアッ
プである導体層は主に銅であることから、銅を用いるこ
とがよい。その厚みは１〜２０μｍの範囲で行うのがよ
い。それより厚くなると、エッチングの際にアンダーカ
ットが起こってしまい、形成されるトラジション層とビ
アと界面に隙間が発生することがある。その後、エッチ
ングレジストを形成して、露光、現像してトラジション
層以外の部分の金属を露出させてエッチングを行い、Ｉ
Ｃチップのパッド上にトラジション層を形成させる。On the other hand, when the transition layer is formed by a sub process, the metal layer is formed thick by electroless or electrolytic plating. Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron.
It is preferable to use copper because the electrical characteristics, economy, and the conductor layer, which is a build-up formed later, are mainly copper. The thickness is preferably in the range of 1 to 20 μm. If the thickness is larger than that, an undercut occurs at the time of etching, and a gap may be generated at the interface between the formed transition layer and the via. Thereafter, an etching resist is formed, exposed and developed to expose the metal other than the transition layer, and the etching is performed.
A transition layer is formed on pads of the C chip.

【００１６】[0016]

【発明の実施の形態】以下、本発明の実施形態について
図を参照して説明する。先ず、本発明の第１実施形態に
係る多層プリント配線板の構成について、多層プリント
配線板１０の断面を示す図６を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the multilayer printed wiring board according to the first embodiment of the present invention will be described with reference to FIG.

【００１７】図６に示すように多層プリント配線板１０
は、ＩＣチップ２０を収容するコア基板３０と、層間樹
脂絶縁層５０、層間樹脂絶縁層１５０とからなる。層間
樹脂絶縁層５０には、ビア６０および導体回路５８が形
成され、層間樹脂絶縁層１５０には、ビア１６０および
導体回路１５８が形成されている。As shown in FIG. 6, the multilayer printed wiring board 10
Comprises a core substrate 30 for accommodating the IC chip 20, an interlayer resin insulation layer 50, and an interlayer resin insulation layer 150. Vias 60 and conductor circuits 58 are formed in interlayer resin insulation layer 50, and vias 160 and conductor circuits 158 are formed in interlayer resin insulation layer 150.

【００１８】ＩＣチップ２０には、ＩＣ保護膜（パッシ
ベーション＋ポリイミド）２２が被覆され、該ＩＣ保護
膜２２の開口内に入出力端子を構成するダイパッド２４
が配設されている。パッド２４の上には、ダイトラジシ
ョン層３８が形成されている。The IC chip 20 is covered with an IC protection film (passivation + polyimide) 22, and a die pad 24 forming an input / output terminal is formed in an opening of the IC protection film 22.
Are arranged. A die transition layer 38 is formed on the pad 24.

【００１９】層間樹脂絶縁層１５０の上には、ソルダー
レジスト層７０が配設されている。ソルダーレジスト層
７０の開口部７１下の導体回路１５８には、図示しない
ドータボード、マザーボード等の外部基板と接続するた
めの半田バンプ７６、又は、図示しない導電性接続ピン
が設けられている。On the interlayer resin insulating layer 150, a solder resist layer 70 is provided. The conductor circuit 158 below the opening 71 of the solder resist layer 70 is provided with a solder bump 76 for connecting to an external substrate such as a daughter board or motherboard (not shown) or a conductive connection pin (not shown).

【００２０】本実施形態の多層プリント配線板１０で
は、コア基板３０にＩＣチップ２０を予め内蔵させて、
該ＩＣチップ２０のパッド２４にはトラジション層を３
８を配設させている。このため、ビアを形成する際のア
ライメントが行い易く、ダイパッドピッチ１５０μｍ以
下、パッドサイズ２０μｍ以下でもビルドアップ層が安
定して形成できる。トラジション層を形成させていない
ダイパッドのままで、フォトエッチングにより層間絶縁
層のビアを形成させると、ビア径がダイパッド径よりも
大きいと、ビア底残査除去、層間樹脂絶縁層表面粗化処
理として行うデスミア処理時にダイパッド表面の保護層
であるポリイミド層を溶解、損傷する。一方、レーザの
場合、ビア径がダイパッド径より大きいときには、ダイ
パッド及びパシベーション、ポリミド層（ＩＣの保護
膜）がレーザによって破壊される。更に、ＩＣチップの
パッドが非常に小さく、ビア径がダイパッドサイズより
大きくなると、フォトエッチング法でも、レーザ法でも
位置合わせが非常に困難であり、ダイパッドとビアとの
接続不良が多発する。In the multi-layer printed wiring board 10 of the present embodiment, the IC chip 20 is built in the core substrate 30 in advance.
The pad 24 of the IC chip 20 has three transition layers.
8 are arranged. For this reason, alignment at the time of forming a via is easy, and a build-up layer can be stably formed even if the die pad pitch is 150 μm or less and the pad size is 20 μm or less. When the via of the interlayer insulating layer is formed by photoetching with the die pad without forming the transition layer, if the via diameter is larger than the die pad diameter, the residue at the bottom of the via is removed and the surface of the interlayer resin insulating layer is roughened. Dissolves and damages the polyimide layer which is a protective layer on the surface of the die pad during the desmearing process. On the other hand, in the case of laser, when the via diameter is larger than the die pad diameter, the die pad, passivation, and polyimide layer (protective film of IC) are destroyed by the laser. Furthermore, if the pad of the IC chip is very small and the via diameter is larger than the die pad size, it is very difficult to align the position by the photo-etching method or the laser method, and connection failure between the die pad and the via frequently occurs.

【００２１】これに対して、ダイパッド上にトラジショ
ン層を設けることで、ダイパッドピッチ１５０μｍ以
下、パッドサイズ２０μｍ以下になってもダイパッド上
にビアを確実に接続させることができ、パッドとビアと
の接続性や信頼性を向上させる。更に、ＩＣチップのパ
ッド上により大きな径のトラジション層を介在させるこ
とで、デスミヤ、めっき工程などの後工程の際に、酸や
エッチング液に浸漬させたり、種々のアニール工程を経
ても、ダイパッド及びＩＣの保護膜（パシベーション、
ポリミド層）を溶解、損傷する危険がなくなる。On the other hand, by providing the transition layer on the die pad, even if the die pad pitch becomes 150 μm or less and the pad size becomes 20 μm or less, the via can be securely connected on the die pad, and the connection between the pad and the via Improve connectivity and reliability. Furthermore, by interposing a larger diameter transition layer on the pad of the IC chip, the die pad can be immersed in an acid or an etching solution during a post-process such as desmearing or a plating process, or subjected to various annealing processes. And IC protective film (passivation,
The risk of dissolving and damaging the polyimide layer) is eliminated.

【００２２】引き続き、図６を参照して上述した多層プ
リント配線板の製造方法について、図１〜図５を参照し
て説明する。Next, a method of manufacturing the multilayer printed wiring board described above with reference to FIG. 6 will be described with reference to FIGS.

【００２３】（１）先ず、ガラスクロス等の心材にエポ
キシ等の樹脂を含浸させたプリプレグを積層した絶縁樹
脂基板（コア基板）３０を出発材料とする（図１（Ａ）
参照）。次に、コア基板３０の片面に、ザグリ加工でＩ
Ｃチップ収容用の凹部３２を形成する（図１（Ｂ）参
照）。ここでは、ザグリ加工により凹部を設けている
が、開口を設けた絶縁樹脂基板と開口を設けない樹脂絶
縁基板とを張り合わせることで、収容部を備えるコア基
板を形成できる。(1) First, an insulating resin substrate (core substrate) 30 in which a prepreg obtained by impregnating a resin such as epoxy into a core material such as glass cloth is used as a starting material (FIG. 1A).
reference). Next, on one surface of the core substrate 30,
A concave portion 32 for accommodating the C chip is formed (see FIG. 1B). Here, the concave portion is formed by counterboring, but a core substrate having an accommodating portion can be formed by laminating an insulating resin substrate having an opening and a resin insulating substrate having no opening.

【００２４】（２）その後、凹部３２に、印刷機を用い
て接着材料３４を塗布する。このとき、塗布以外にも、
ポッティングなどをしてもよい。次に、ＩＣチップ２０
を接着材料３４上に載置する（図１（Ｃ）参照）。(2) Thereafter, an adhesive material 34 is applied to the recess 32 using a printing machine. At this time, besides coating,
Potting may be performed. Next, the IC chip 20
Is placed on the adhesive material 34 (see FIG. 1C).

【００２５】（３）そして、ＩＣチップ２０の上面を押
す、もしくは叩いて凹部３２内に完全に収容させる（図
１（Ｄ）参照）。これにより、コア基板３０を平滑にす
ることができる。(3) Then, the upper surface of the IC chip 20 is pushed or hit to completely accommodate the IC chip 20 in the recess 32 (see FIG. 1D). Thereby, the core substrate 30 can be smoothed.

【００２６】（４）その後、ＩＣチップ２０を収容させ
たコア基板３０の全面に蒸着、スパッタリングなどの物
理的な蒸着を行い、全面に導電性の金属膜３３を形成さ
せる（図２（Ａ））。その金属としては、スズ、クロ
ム、チタン、ニッケル、亜鉛、コバルト、金、銅などの
金属を１層以上形成させるものがよい。厚みとしては、
０．００１〜２．０μｍの間で形成させるのがよい。特
に、０．０１〜１．０μｍが望ましい。特に、ニッケ
ル、クロム、チタンで形成するのがよい。界面から湿分
の侵入がなく、金属密着性に優れるからである。クロム
の厚みは、スパッタ層にクラックが入らず、かつ銅スパ
ッタ層との密着が十分とれる厚みにする。(4) Thereafter, physical vapor deposition such as vapor deposition or sputtering is performed on the entire surface of the core substrate 30 accommodating the IC chip 20 to form a conductive metal film 33 on the entire surface (FIG. 2A). ). As the metal, it is preferable to form one or more layers of a metal such as tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper. As the thickness,
It is preferred that the thickness be formed between 0.001 and 2.0 μm. In particular, 0.01 to 1.0 μm is desirable. In particular, it is preferable to use nickel, chromium, or titanium. This is because there is no penetration of moisture from the interface and the metal adhesion is excellent. The thickness of the chromium is set to a thickness that does not cause cracks in the sputtered layer and allows sufficient adhesion with the copper sputtered layer.

【００２７】金属膜３３上に、無電解めっきにより、め
っき膜３６を形成させてもよい（図２（Ｂ））。形成さ
れるメッキの種類としてはニッケル、銅、金、銀などが
ある。電気特性、経済性、また、後程で形成されるビル
ドアップである導体層は主に銅であることから、銅を用
いるとよい。その厚みは０．０１〜５μｍの範囲で行う
のがよい。特に、０．１〜３μｍが望ましい。なお、望
ましい第１薄膜層と第２薄膜層との組み合わせは、クロ
ム−銅、クロム−ニッケル、チタン−銅、チタン−ニッ
ケルである。金属との接合性や電気伝達性という点で他
の組み合わせよりも優れる。A plating film 36 may be formed on the metal film 33 by electroless plating (FIG. 2B). The types of plating to be formed include nickel, copper, gold, silver and the like. It is preferable to use copper because the electrical characteristics, economy, and the conductor layer, which is a build-up formed later, are mainly copper. The thickness is preferably in the range of 0.01 to 5 μm. In particular, 0.1 to 3 μm is desirable. Desirable combinations of the first thin film layer and the second thin film layer are chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of bonding to metals and electrical conductivity.

【００２８】（５）その後、レジストを塗布、あるい
は、感光性フィルムをラミネートし、露光、現像してＩ
Ｃチップのパッドの上部に開口を設けるようにメッキレ
ジスト３５を設け、電解めっき膜３７を設ける（図２
（Ｃ））。電解めっき膜３７の厚みは１〜２０μｍ程度
がよい。電解めっき膜は、ニッケル、銅、金、銀、亜
鉛、鉄で形成できる。メッキレジスト３５を除去した
後、メッキレジスト３５下の無電解めっき膜３６、金属
膜３３をエッチングで除去することで、ＩＣチップのパ
ッド２４上にトラジション層３８を形成する（図２
（Ｄ））。ここでは、メッキレジストによりトラジショ
ン層を形成したが、無電解めっき膜３６の上に電解めっ
き膜を均一に形成した後、エッチングレジストを形成し
て、露光、現像してトラジション層以外の部分の金属を
露出させてエッチングを行い、ＩＣチップのパッド上に
トラジション層を形成させることも可能である。この場
合、電解めっき膜の厚みは１〜２０μｍの範囲がよい。
それより厚くなると、エッチングの際にアンダーカット
が起こってしまい、形成されるトラジション層とビアと
界面に隙間が発生することがあるからである。(5) Thereafter, a resist is applied or a photosensitive film is laminated, exposed and developed to
A plating resist 35 is provided so as to provide an opening above the pad of the C chip, and an electrolytic plating film 37 is provided.
(C)). The thickness of the electrolytic plating film 37 is preferably about 1 to 20 μm. The electrolytic plating film can be formed of nickel, copper, gold, silver, zinc, and iron. After removing the plating resist 35, the electroless plating film 36 and the metal film 33 under the plating resist 35 are removed by etching to form a transition layer 38 on the pad 24 of the IC chip (FIG. 2).
(D)). Here, the transition layer is formed by a plating resist, but after an electrolytic plating film is uniformly formed on the electroless plating film 36, an etching resist is formed, and exposure and development are performed to obtain portions other than the transition layer. It is also possible to form a transition layer on the pads of the IC chip by exposing the metal to the etching. In this case, the thickness of the electrolytic plating film is preferably in the range of 1 to 20 μm.
If the thickness is larger than that, an undercut occurs at the time of etching, and a gap may be generated at the interface between the formed transition layer and the via.

【００２９】（６）次に、基板にエッチング液をスプレ
イで吹きつけ、トラジション層３８の表面をエッチング
することにより粗化面３８αを形成する（図３（Ａ）参
照）。無電解めっきや酸化還元処理を用いて粗化面を形
成することもできる。(6) Next, an etching solution is sprayed on the substrate by spraying, and the surface of the transition layer 38 is etched to form a roughened surface 38α (see FIG. 3A). The roughened surface can be formed by using electroless plating or oxidation-reduction treatment.

【００３０】（７）上記工程を経た基板に、厚さ３０〜
５０μｍの熱硬化型シクロオレフィン系樹脂シートを温
度５０〜１５０℃まで昇温しながら圧力５ｋｇ／ｃｍ2
で真空圧着ラミネートし、シクロオレフィン系樹脂から
なる層間樹脂絶縁層５０を設ける（図３（Ｂ）参照）。
真空圧着時の真空度は、１０ｍｍＨｇである。または、
液状絶縁樹脂をスピンコートなどによって塗布し、絶縁
層を形成してもよい。(7) A thickness of 30 to
A pressure of 5 kg / cm 2 is applied to a 50 μm thermosetting cycloolefin resin sheet while the temperature is raised to a temperature of 50 to 150 ° C.
To form an interlayer resin insulation layer 50 made of a cycloolefin-based resin (see FIG. 3B).
The degree of vacuum during vacuum compression is 10 mmHg. Or
A liquid insulating resin may be applied by spin coating or the like to form an insulating layer.

【００３１】（８）次に、ＣＯ2ガスレーザにて層間樹
脂絶縁層５０にビア用開口４８を設ける（図３（Ｃ）参
照）。クロム酸を用いて、開口４８内の樹脂残りを除去
する。ダイパッド２４上に銅製のトラジション層３８を
設けることで、ビアを形成する際のアライメントをし易
くし、ダイパッド２４上にビアを確実に接続させ、パッ
ドとビアとの接続性や信頼性を向上させる。これによ
り、ビルドアップ層が安定して形成できる。ＩＣチップ
のパッド上により大きな径のトラジション層を介在させ
ることで、ビア底残査除去、層間樹脂絶縁層表面粗化処
理として行うデスミア処理時、めっき工程などの後工程
の際に酸やエッチング液に浸漬させたり、種々のアニー
ル工程を経ても、ダイパッド２４及びＩＣの保護膜（パ
シベーション、ポリミド層）２２を溶解、損傷する危険
がなくなる。なお、ここでは、過マンガン酸を用いて樹
脂残さを除去したが、酸素プラズマを用いてデスミア処
理を行うことも可能である。(8) Next, a via opening 48 is provided in the interlayer resin insulating layer 50 by using a CO 2 gas laser (see FIG. 3C). The residual resin in the opening 48 is removed using chromic acid. By providing the copper transition layer 38 on the die pad 24, alignment at the time of forming a via is facilitated, the via is securely connected on the die pad 24, and the connectivity and reliability between the pad and the via are improved. Let it. Thereby, a build-up layer can be formed stably. By inserting a larger diameter transition layer on the IC chip pad, it removes residues from the bottom of the via, removes acid during etching such as desmearing performed as a surface roughening treatment of the interlayer resin insulation layer, and plating and other post-processing. There is no danger of dissolving or damaging the die pad 24 and the protective film (passivation, polyimide layer) 22 of the IC even when immersed in a liquid or through various annealing processes. Here, the resin residue is removed using permanganic acid, but it is also possible to perform desmear treatment using oxygen plasma.

【００３２】（９）次に、層間樹脂絶縁層５０の表面を
粗化し、粗化面５０αを形成する（図３（Ｄ）参照）。
なお、この粗化工程は省略することもできる。(9) Next, the surface of the interlayer resin insulating layer 50 is roughened to form a roughened surface 50α (see FIG. 3D).
This roughening step can be omitted.

【００３３】（１０）次に、層間樹脂絶縁層５０の表面
にパラジウム触媒を付与した後、無電解めっき液に基板
を浸漬し、無電解めっき膜５２を層間樹脂絶縁層５０の
表面に形成する（図４（Ａ）参照）。(10) Next, after applying a palladium catalyst to the surface of the interlayer resin insulation layer 50, the substrate is immersed in an electroless plating solution to form an electroless plating film 52 on the surface of the interlayer resin insulation layer 50. (See FIG. 4A).

【００３４】（１１）上記処理を終えた基板３０に、市
販の感光性ドライフィルムを貼り付け、クロムガラスマ
スクを載置して、４０ｍＪ／ｃｍ2で露光した後、０．
８％炭酸ナトリウムで現像処理し、厚さ２５μｍのめっ
きレジスト５４を設ける。次に、以下の条件で電解めっ
きを施して、厚さ１８μｍの電解めっき膜５６を形成す
る（図４（Ｂ）参照）。なお、電解めっき水溶液中の添
加剤は、アトテックジャパン社製のカパラシドＨＬであ
る。(11) A commercially available photosensitive dry film is affixed to the substrate 30 that has been subjected to the above processing, a chrome glass mask is placed on the substrate 30 and exposed at 40 mJ / cm 2 .
Develop with 8% sodium carbonate to provide a plating resist 54 having a thickness of 25 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 56 having a thickness of 18 μm (see FIG. 4B). The additive in the electrolytic plating aqueous solution is Capparaside HL manufactured by Atotech Japan.

【００３５】 〔電解めっき水溶液〕 硫酸 ２．２４ ｍｏｌ／ｌ 硫酸銅 ０．２６ ｍｏｌ／ｌ 添加剤（アトテックジャパン製、カパラシドＨＬ） １９．５ ｍｌ／ｌ 〔電解めっき条件〕 電流密度 １Ａ／dm２ 時間 ６５分 温度 ２２±２℃[Aqueous electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (captoside HL, manufactured by Atotech Japan) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm 2 Time 65 minutes Temperature 22 ± 2 ℃

【００３６】（１２）めっきレジスト５４を５％ＮａＯ
Ｈで剥離除去した後、そのめっきレジスト下の無電解め
っき膜５２を硝酸および硫酸と過酸化水素の混合液を用
いるエッチングにて溶解除去し、無電解めっき膜５２と
電解めっき膜５６からなる厚さ１６μｍの導体回路５８
及びビア６０を形成し、第二銅錯体と有機酸とを含有す
るエッチング液によって、粗化面５８α、６０αを形成
する（図４（Ｃ）参照）。(12) The plating resist 54 is made of 5% NaO
After removing with H, the electroless plating film 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the thickness of the electroless plating film 52 and the electrolytic plating film 56 is reduced. 16 μm conductor circuit 58
And vias 60 are formed, and roughened surfaces 58α and 60α are formed with an etching solution containing a cupric complex and an organic acid (see FIG. 4C).

【００３７】（１３）次いで、上記（８）〜（１３）の
工程を、繰り返すことにより、さらに上層の層間樹脂絶
縁層１５０及び導体回路１５８（ビア１６０を含む）を
形成する（図５（Ａ）参照）。(13) Next, the above steps (8) to (13) are repeated to form a further upper interlayer resin insulation layer 150 and a conductor circuit 158 (including a via 160) (FIG. 5A )reference).

【００３８】（１４）次に、ジエチレングリコールジメ
チルエーテル（ＤＭＤＧ）に６０重量％の濃度になるよ
うに溶解させた、クレゾールノボラック型エポキシ樹脂
（日本化薬社製）のエポキシ基５０％をアクリル化した
感光性付与のオリゴマー（分子量４０００）４６．６７
重量部、メチルエチルケトンに溶解させた８０重量％の
ビスフェノールＡ型エポキシ樹脂（油化シェル社製、商
品名：エピコート１００１）１５重量部、イミダゾール
硬化剤（四国化成社製、商品名：２Ｅ４ＭＺ−ＣＮ）
１．６重量部、感光性モノマーである多官能アクリルモ
ノマー（共栄化学社製、商品名：Ｒ６０４）３重量部、
同じく多価アクリルモノマー（共栄化学社製、商品名：
ＤＰＥ６Ａ）１．５重量部、分散系消泡剤（サンノプコ
社製、商品名：Ｓ−６５）０．７１重量部を容器にと
り、攪拌、混合して混合組成物を調整し、この混合組成
物に対して光重量開始剤としてベンゾフェノン（関東化
学社製）２．０重量部、光増感剤としてのミヒラーケト
ン（関東化学社製）０．２重量部を加えて、粘度を２５
℃で２．０Ｐａ・ｓに調整したソルダーレジスト組成物
（有機樹脂絶縁材料）を得る。なお、粘度測定は、Ｂ型
粘度計（東京計器社製、ＤＶＬ−Ｂ型）で６０ｒｐｍの
場合はローターNo.４、６ｒｐｍの場合はローターNo.３
によった。(14) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight was sensitized with 50% of epoxy groups being acrylated. Oligomer for imparting properties (molecular weight 4000) 46.67
15 parts by weight of a bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) of 80% by weight dissolved in methyl ethyl ketone, imidazole hardener (trade name: 2E4MZ-CN manufactured by Shikoku Chemicals)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., trade name: R604) as a photosensitive monomer,
Similarly, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name:
1.5 parts by weight of DPE6A) and 0.71 part by weight of a dispersant antifoaming agent (manufactured by San Nopco, trade name: S-65) are placed in a container, stirred and mixed to prepare a mixed composition. Of benzophenone (manufactured by Kanto Kagaku) and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to give a viscosity of 25.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at ° C is obtained. The viscosity was measured using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm and rotor No. 4 at 6 rpm.
According to

【００３９】（１５）次に、基板３０に、上記ソルダー
レジスト組成物を２０μｍの厚さで塗布し、７０℃で２
０分間、７０℃で３０分間の条件で乾燥処理を行った
後、ソルダーレジストレジスト開口部のパターンが描画
された厚さ５ｍｍのフォトマスクをソルダーレジスト層
７０に密着させて１０００ｍＪ／ｃｍ2の紫外線で露光
し、ＤＭＴＧ溶液で現像処理し、ランド径６２０μｍ、
開口径４６０μｍの開口７１を形成する（図５（Ｂ）参
照）。(15) Next, the above-mentioned solder resist composition is applied to the substrate 30 at a thickness of 20 μm,
After performing a drying process at 70 ° C. for 30 minutes for 0 minute, a 5 mm-thick photomask on which a pattern of the opening of the solder resist resist is drawn is brought into close contact with the solder resist layer 70, and an ultraviolet ray of 1000 mJ / cm 2 is applied. And developed with a DMTG solution, a land diameter of 620 μm,
An opening 71 having an opening diameter of 460 μm is formed (see FIG. 5B).

【００４０】（１６）次に、ソルダーレジスト層（有機
樹脂絶縁層）７０を形成した基板を、塩化ニッケル
（２．３×１０-1ｍｏｌ／ｌ）、次亞リン酸ナトリウム
（２．８×１０-1ｍｏｌ／ｌ）、クエン酸ナトリウム
（１．６×１０-1ｍｏｌ／ｌ）を含むｐＨ＝４．５の無
電解ニッケルめっき液に２０分間浸漬して、開口部７１
に厚さ５μｍのニッケルめっき層７２を形成する。さら
に、その基板を、シアン化金カリウム（７．６×１０-3
ｍｏｌ／ｌ）、塩化アンモニウム（１．９×１０-1ｍｏ
ｌ／ｌ）、クエン酸ナトリウム（１．２×１０-1ｍｏｌ
／ｌ）、次亜リン酸ナトリウム（１．７×１０-1ｍｏｌ
／ｌ）を含む無電解めっき液に８０℃の条件で７．５分
間浸漬して、ニッケルめっき層７２上に厚さ０．０３μ
ｍの金めっき層７４を形成することで、導体回路１５８
に半田パッド７５を形成する（図５（Ｃ）参照）。(16) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed is coated with nickel chloride (2.3 × 10 -1 mol / l) and sodium hypophosphite (2.8 × 10 -1 mol / l) and an electroless nickel plating solution having a pH of 4.5 containing sodium citrate (1.6 × 10 -1 mol / l) for 20 minutes.
Then, a nickel plating layer 72 having a thickness of 5 μm is formed. Further, the substrate was subjected to potassium gold cyanide (7.6 × 10 −3).
mol / l), ammonium chloride (1.9 × 10 -1 mo)
1 / l), sodium citrate (1.2 × 10 -1 mol)
/ L), sodium hypophosphite (1.7 × 10 -1 mol)
/ L) is immersed for 7.5 minutes at 80 ° C. in an electroless plating solution containing
By forming the gold plating layer 74 of the length m, the conductor circuit 158 can be formed.
Then, a solder pad 75 is formed (see FIG. 5C).

【００４１】（１７）この後、ソルダーレジスト層７０
の開口部７１に、はんだペーストを印刷して、２００℃
でリフローすることにより、半田バンプ７６を形成す
る。これにより、ＩＣチップ２０を内蔵し、半田バンプ
７６を有する多層プリント配線板１０を得ることができ
る（図６参照）。なお、半田ペーストを印刷して導電性
接続ピンを配置することもできる。(17) Thereafter, the solder resist layer 70
The solder paste is printed on the opening 71 of
To form the solder bumps 76. Thereby, the multilayer printed wiring board 10 having the IC chip 20 built-in and having the solder bumps 76 can be obtained (see FIG. 6). The conductive connection pins can be arranged by printing a solder paste.

【００４２】上述した実施形態では、層間樹脂絶縁層５
０、１５０に熱硬化型シクロオレフィン系樹脂シートを
用いた。この代わりに、層間樹脂絶縁層５０にエポキシ
系樹脂を用いることができる。このエポキシ系樹脂に
は、難溶性樹脂、可溶性粒子、硬化剤、その他の成分が
含有されている。それぞれについて以下に説明する。In the above embodiment, the interlayer resin insulating layer 5
Thermosetting cycloolefin resin sheets were used for Nos. 0 and 150. Instead, an epoxy resin can be used for the interlayer resin insulation layer 50. This epoxy resin contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each is described below.

【００４３】本発明の製造方法において使用し得るエポ
キシ系樹脂は、酸または酸化剤に可溶性の粒子（以下、
可溶性粒子という）が酸または酸化剤に難溶性の樹脂
（以下、難溶性樹脂という）中に分散したものである。
なお、本発明で使用する「難溶性」「可溶性」という語
は、同一の酸または酸化剤からなる溶液に同一時間浸漬
した場合に、相対的に溶解速度の早いものを便宜上「可
溶性」と呼び、相対的に溶解速度の遅いものを便宜上
「難溶性」と呼ぶ。The epoxy resin that can be used in the production method of the present invention includes particles soluble in an acid or an oxidizing agent (hereinafter referred to as particles).
(Hereinafter referred to as "soluble particles") dispersed in a resin that is hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a hardly soluble resin).
The terms “sparingly soluble” and “soluble” as used in the present invention, when immersed in a solution containing the same acid or oxidizing agent for the same time, have a relatively high dissolution rate and are called “soluble” for convenience. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

【００４４】上記可溶性粒子としては、例えば、酸また
は酸化剤に可溶性の樹脂粒子（以下、可溶性樹脂粒
子）、酸または酸化剤に可溶性の無機粒子（以下、可溶
性無機粒子）、酸または酸化剤に可溶性の金属粒子（以
下、可溶性金属粒子）等が挙げられる。これらの可溶性
粒子は、単独で用いても良いし、２種以上併用してもよ
い。Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

【００４５】上記可溶性粒子の形状は特に限定されず、
球状、破砕状等が挙げられる。また、上記可溶性粒子の
形状は、一様な形状であることが望ましい。均一な粗さ
の凹凸を有する粗化面を形成することができるからであ
る。The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

【００４６】上記可溶性粒子の平均粒径としては、０．
１〜１０μｍが望ましい。この粒径の範囲であれば、２
種類以上の異なる粒径のものを含有してもよい。すなわ
ち、平均粒径が０．１〜０．５μｍの可溶性粒子と平均
粒径が１〜３μｍの可溶性粒子とを含有する等である。
これにより、より複雑な粗化面を形成することができ、
導体回路との密着性にも優れる。なお、本発明におい
て、可溶性粒子の粒径とは、可溶性粒子の一番長い部分
の長さである。The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

【００４７】上記可溶性樹脂粒子としては、熱硬化性樹
脂、熱可塑性樹脂等からなるものが挙げられ、酸あるい
は酸化剤からなる溶液に浸漬した場合に、上記難溶性樹
脂よりも溶解速度が速いものであれば特に限定されな
い。上記可溶性樹脂粒子の具体例としては、例えば、エ
ポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ポリフ
ェニレン樹脂、ポリオレフィン樹脂、フッ素樹脂等から
なるものが挙げられ、これらの樹脂の一種からなるもの
であってもよいし、２種以上の樹脂の混合物からなるも
のであってもよい。Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

【００４８】また、上記可溶性樹脂粒子としては、ゴム
からなる樹脂粒子を用いることもできる。上記ゴムとし
ては、例えば、ポリブタジエンゴム、エポキシ変性、ウ
レタン変性、（メタ）アクリロニトリル変性等の各種変
性ポリブタジエンゴム、カルボキシル基を含有した（メ
タ）アクリロニトリル・ブタジエンゴム等が挙げられ
る。これらのゴムを使用することにより、可溶性樹脂粒
子が酸あるいは酸化剤に溶解しやすくなる。つまり、酸
を用いて可溶性樹脂粒子を溶解する際には、強酸以外の
酸でも溶解することができ、酸化剤を用いて可溶性樹脂
粒子を溶解する際には、比較的酸化力の弱い過マンガン
酸塩でも溶解することができる。また、クロム酸を用い
た場合でも、低濃度で溶解することができる。そのた
め、酸や酸化剤が樹脂表面に残留することがなく、後述
するように、粗化面形成後、塩化パラジウム等の触媒を
付与する際に、触媒が付与されなたかったり、触媒が酸
化されたりすることがない。As the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

【００４９】上記可溶性無機粒子としては、例えば、ア
ルミニウム化合物、カルシウム化合物、カリウム化合
物、マグネシウム化合物およびケイ素化合物からなる群
より選択される少なくとも一種からなる粒子等が挙げら
れる。Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

【００５０】上記アルミニウム化合物としては、例え
ば、アルミナ、水酸化アルミニウム等が挙げられ、上記
カルシウム化合物としては、例えば、炭酸カルシウム、
水酸化カルシウム等が挙げられ、上記カリウム化合物と
しては、炭酸カリウム等が挙げられ、上記マグネシウム
化合物としては、マグネシア、ドロマイト、塩基性炭酸
マグネシウム等が挙げられ、上記ケイ素化合物として
は、シリカ、ゼオライト等が挙げられる。これらは単独
で用いても良いし、２種以上併用してもよい。The aluminum compound includes, for example, alumina and aluminum hydroxide. The calcium compound includes, for example, calcium carbonate,
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

【００５１】上記可溶性金属粒子としては、例えば、
銅、ニッケル、鉄、亜鉛、鉛、金、銀、アルミニウム、
マグネシウム、カルシウムおよびケイ素からなる群より
選択される少なくとも一種からなる粒子等が挙げられ
る。また、これらの可溶性金属粒子は、絶縁性を確保す
るために、表層が樹脂等により被覆されていてもよい。The soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

【００５２】上記可溶性粒子を、２種以上混合して用い
る場合、混合する２種の可溶性粒子の組み合わせとして
は、樹脂粒子と無機粒子との組み合わせが望ましい。両
者とも導電性が低くいため樹脂フィルムの絶縁性を確保
することができるとともに、難溶性樹脂との間で熱膨張
の調整が図りやすく、樹脂フィルムからなる層間樹脂絶
縁層にクラックが発生せず、層間樹脂絶縁層と導体回路
との間で剥離が発生しないからである。When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin film can be ensured, and thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

【００５３】上記難溶性樹脂としては、層間樹脂絶縁層
に酸または酸化剤を用いて粗化面を形成する際に、粗化
面の形状を保持できるものであれば特に限定されず、例
えば、熱硬化性樹脂、熱可塑性樹脂、これらの複合体等
が挙げられる。また、これらの樹脂に感光性を付与した
感光性樹脂であってもよい。感光性樹脂を用いることに
より、層間樹脂絶縁層に露光、現像処理を用いてビア用
開口を形成することできる。これらのなかでは、熱硬化
性樹脂を含有しているものが望ましい。それにより、め
っき液あるいは種々の加熱処理によっても粗化面の形状
を保持することができるからである。The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed on the interlayer resin insulating layer using an acid or an oxidizing agent. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, a via opening can be formed in the interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

【００５４】上記難溶性樹脂の具体例としては、例え
ば、エポキシ樹脂、フェノール樹脂、フェノキシ樹脂、
ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン
樹脂、フッ素樹脂等が挙げられる。これらの樹脂は単独
で用いてもよいし、２種以上を併用してもよい。熱硬化
性樹脂、熱可塑性樹脂、それらの複合体であってもよ
い。さらには、１分子中に、２個以上のエポキシ基を有
するエポキシ樹脂がより望ましい。前述の粗化面を形成
することができるばかりでなく、耐熱性等にも優れてる
ため、ヒートサイクル条件下においても、金属層に応力
の集中が発生せず、金属層の剥離などが起きにくいから
である。Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. It may be a thermosetting resin, a thermoplastic resin, or a composite thereof. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

【００５５】上記エポキシ樹脂としては、例えば、クレ
ゾールノボラック型エポキシ樹脂、ビスフェノールＡ型
エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、フェ
ノールノボラック型エポキシ樹脂、アルキルフェノール
ノボラック型エポキシ樹脂、ビフェノールＦ型エポキシ
樹脂、ナフタレン型エポキシ樹脂、ジシクロペンタジエ
ン型エポキシ樹脂、フェノール類とフェノール性水酸基
を有する芳香族アルデヒドとの縮合物のエポキシ化物、
トリグリシジルイソシアヌレート、脂環式エポキシ樹脂
等が挙げられる。これらは、単独で用いてもよく、２種
以上を併用してもよい。それにより、耐熱性等に優れる
ものとなる。Examples of the epoxy resin include cresol novolak type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenol F type epoxy resin, and naphthalene type epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

【００５６】本発明で用いる樹脂フィルムにおいて、上
記可溶性粒子は、上記難溶性樹脂中にほぼ均一に分散さ
れていることが望ましい。均一な粗さの凹凸を有する粗
化面を形成することができ、樹脂フィルムにビアやスル
ーホールを形成しても、その上に形成する導体回路の金
属層の密着性を確保することができるからである。ま
た、粗化面を形成する表層部だけに可溶性粒子を含有す
る樹脂フィルムを用いてもよい。それによって、樹脂フ
ィルムの表層部以外は酸または酸化剤にさらされること
がないため、層間樹脂絶縁層を介した導体回路間の絶縁
性が確実に保たれる。In the resin film used in the present invention, the soluble particles are desirably substantially uniformly dispersed in the hardly-soluble resin. A roughened surface having unevenness with a uniform roughness can be formed, and even when a via or a through hole is formed in a resin film, the adhesion of a metal layer of a conductive circuit formed thereon can be secured. Because. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby, since the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

【００５７】上記樹脂フィルムにおいて、難溶性樹脂中
に分散している可溶性粒子の配合量は、樹脂フィルムに
対して、３〜４０重量％が望ましい。可溶性粒子の配合
量が３重量％未満では、所望の凹凸を有する粗化面を形
成することができない場合があり、４０重量％を超える
と、酸または酸化剤を用いて可溶性粒子を溶解した際
に、樹脂フィルムの深部まで溶解してしまい、樹脂フィ
ルムからなる層間樹脂絶縁層を介した導体回路間の絶縁
性を維持できず、短絡の原因となる場合がある。In the above resin film, the amount of the soluble particles dispersed in the poorly soluble resin is desirably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, the soluble particles may be dissolved using an acid or an oxidizing agent. In addition, there is a case where the resin film is melted to a deep portion of the resin film and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

【００５８】上記樹脂フィルムは、上記可溶性粒子、上
記難溶性樹脂以外に、硬化剤、その他の成分等を含有し
ていることが望ましい。上記硬化剤としては、例えば、
イミダゾール系硬化剤、アミン系硬化剤、グアニジン系
硬化剤、これらの硬化剤のエポキシアダクトやこれらの
硬化剤をマイクロカプセル化したもの、トリフェニルホ
スフィン、テトラフェニルホスフォニウム・テトラフェ
ニルボレート等の有機ホスフィン系化合物等が挙げられ
る。The resin film desirably contains a curing agent, other components, and the like, in addition to the soluble particles and the poorly soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and microcapsules of these curing agents, and organic materials such as triphenylphosphine, tetraphenylphosphonium, and tetraphenylborate. Phosphine compounds and the like can be mentioned.

【００５９】上記硬化剤の含有量は、樹脂フィルムに対
して０．０５〜１０重量％であることが望ましい。０．
０５重量％未満では、樹脂フィルムの硬化が不十分であ
るため、酸や酸化剤が樹脂フィルムに侵入する度合いが
大きくなり、樹脂フィルムの絶縁性が損なわれることが
ある。一方、１０重量％を超えると、過剰な硬化剤成分
が樹脂の組成を変性させることがあり、信頼性の低下を
招いたりしてしまうことがある。The content of the curing agent is desirably 0.05 to 10% by weight based on the resin film. 0.
If the amount is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidizing agent into the resin film is increased, and the insulating property of the resin film may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

【００６０】上記その他の成分としては、例えば、粗化
面の形成に影響しない無機化合物あるいは樹脂等のフィ
ラーが挙げられる。上記無機化合物としては、例えば、
シリカ、アルミナ、ドロマイト等が挙げられ、上記樹脂
としては、例えば、ポリイミド樹脂、ポリアクリル樹
脂、ポリアミドイミド樹脂、ポリフェニレン樹脂、メラ
ニン樹脂、オレフィン系樹脂等が挙げられる。これらの
フィラーを含有させることによって、熱膨脹係数の整合
や耐熱性、耐薬品性の向上などを図り多層プリント配線
板の性能を向上させることができる。Examples of the other components include fillers such as inorganic compounds or resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the multilayer printed wiring board can be improved by matching thermal expansion coefficients, improving heat resistance and chemical resistance, and the like.

【００６１】また、上記樹脂フィルムは、溶剤を含有し
ていてもよい。上記溶剤としては、例えば、アセトン、
メチルエチルケトン、シクロヘキサノン等のケトン類、
酢酸エチル、酢酸ブチル、セロソルブアセテートやトル
エン、キシレン等の芳香族炭化水素等が挙げられる。こ
れらは単独で用いてもよいし、２種類以上併用してもよ
い。ただし、これらの層間樹脂絶縁層は、３５０℃以上
の温度を加えると溶解、炭化をしてしまう。The resin film may contain a solvent. As the solvent, for example, acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers are dissolved and carbonized when a temperature of 350 ° C. or more is applied.

【００６２】上記樹脂フィルムを張り付けた後、レーザ
で開口させて、層間樹脂絶縁層にビアを開口させる。そ
の後、酸あるいは酸化剤に浸漬させて、層間樹脂絶縁層
に粗化層を形成する。酸としては、硫酸、リン酸、塩
酸、蟻酸などの強酸を用いることができ、酸化剤として
はクロム酸、クロム硫酸、過マンガン塩酸などを用いる
ことができる。それにより、可溶性粒子を溶解あるいは
脱落させることによって層間樹脂絶縁層の表面に粗化層
を形成させる。その粗化層の形成された層間樹脂絶縁層
に、Ｐｂなどの触媒を付与させた後、無電解めっきを施
す。無電解めっき膜上にレジストを施して露光、現像を
経てめっきレジストの非形成部を形成させる。該非形成
部に電解めっきを施してレジストを剥離、エッチングに
よって層間樹脂絶縁層上の無電解めっき膜を除去してビ
アと導体回路を形成させた。After the resin film is attached, the resin film is opened by a laser to open a via in the interlayer resin insulating layer. Then, it is immersed in an acid or an oxidizing agent to form a roughened layer on the interlayer resin insulating layer. As the acid, a strong acid such as sulfuric acid, phosphoric acid, hydrochloric acid, or formic acid can be used, and as the oxidizing agent, chromic acid, chromic sulfuric acid, permanganate hydrochloride, or the like can be used. Thereby, the roughened layer is formed on the surface of the interlayer resin insulating layer by dissolving or dropping the soluble particles. After applying a catalyst such as Pb to the interlayer resin insulating layer on which the roughened layer is formed, electroless plating is performed. A resist is applied on the electroless plating film, and exposed and developed to form a non-formed portion of the plating resist. The non-formed portion was subjected to electrolytic plating to remove the resist, and the electroless plated film on the interlayer resin insulating layer was removed by etching to form a via and a conductive circuit.

【００６３】図７（Ａ）は、第１実施形態に係る多層プ
リント配線板１０の斜視図であり、図７（Ｂ）は、該多
層プリント配線板１０の一部を拡大して示す説明図であ
る。第１実施形態の多層プリント配線板１０の表面に
は、千鳥格子状に半田バンプ（ボールグリットアレー）
７６が基板全面に配設されている。第１実施形態では、
ＩＣチップ２０上にも半田バンプ７６を形成すること
で、ＩＣチップ２０からの配線長さを短縮することがで
きる。FIG. 7A is a perspective view of the multilayer printed wiring board 10 according to the first embodiment, and FIG. 7B is an explanatory view showing a part of the multilayer printed wiring board 10 in an enlarged manner. It is. On the surface of the multilayer printed wiring board 10 according to the first embodiment, solder bumps (ball grid array) are arranged in a staggered lattice pattern.
Reference numeral 76 is provided on the entire surface of the substrate. In the first embodiment,
By forming the solder bumps 76 on the IC chip 20 as well, the length of wiring from the IC chip 20 can be reduced.

【００６４】図８（Ａ）は、第１実施形態の改変例に係
る多層プリント配線板１０の斜視図であり、図８（Ｂ）
は、該多層プリント配線板１０の一部を拡大して示す説
明図である。改変例の多層プリント配線板１０の表面に
は、千鳥格子状に半田バンプ（ボールグリットアレー）
７６がＩＣチップ２０上を除く四隅に配設されている。
この改変例では、ＩＣチップ２０上を避けることで、Ｉ
Ｃチップからの熱的、電磁的影響を半田バンプ７６が受
け難い利点がある。FIG. 8A is a perspective view of a multilayer printed wiring board 10 according to a modification of the first embodiment, and FIG.
FIG. 2 is an explanatory diagram showing a part of the multilayer printed wiring board 10 in an enlarged manner. On the surface of the multilayer printed wiring board 10 of the modified example, solder bumps (ball grit array)
Reference numerals 76 are provided at the four corners except on the IC chip 20.
In this modified example, by avoiding on the IC chip 20,
There is an advantage that the solder bumps 76 are less susceptible to thermal and electromagnetic effects from the C chip.

【００６５】引き続き、本発明の第１実施形態の別改変
例に係る多層プリント配線板について、図９を参照して
説明する。上述した第１実施形態では、ＢＧＡを配設し
た場合で説明した。第２実施形態では、第１実施形態と
ほぼ同様であるが、図９に示すように導電性接続ピン９
６を介して接続を取るＰＧＡ方式に構成されている。Next, a multilayer printed wiring board according to another modification of the first embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, the case where the BGA is provided has been described. The second embodiment is almost the same as the first embodiment, but as shown in FIG.
The PGA system is used to establish a connection via the PGA 6.

【００６６】次に、本発明の第２実施形態に係る多層プ
リント配線板について、図１０を参照して説明する。上
述した第１実施形態では、コア基板３０にザグリで設け
た凹部３２にＩＣチップを収容した。これに対して、第
２実施形態では、コア基板３０に形成した通孔３２にＩ
Ｃチップ２０を収容してある。この第２実施形態では、
ＩＣチップ２０の裏面側にヒートシンクを直接取り付け
ることができるため、ＩＣチップ２０を効率的に冷却で
きる利点がある。Next, a multilayer printed wiring board according to a second embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, the IC chip is accommodated in the recess 32 provided in the core substrate 30 with a counterbore. On the other hand, in the second embodiment, the through holes 32 formed in the core substrate 30 have I through holes.
The C chip 20 is accommodated. In the second embodiment,
Since the heat sink can be directly attached to the back side of the IC chip 20, there is an advantage that the IC chip 20 can be cooled efficiently.

【００６７】引き続き、本発明の第３実施形態に係る多
層プリント配線板について、図１１を参照して説明す
る。上述した第１実施形態では、ＩＣチップ２０のパッ
ド２４上にトラジション層３８を形成し、該トラジショ
ン層３８に層間樹脂絶縁層５０のビア６０を接続した。
これに対して、第３実施形態では、トラジション層を設
けることなくビア６０をパッド２４へ直接接続してあ
る。この第３実施形態は、第１実施形態と比較して工程
を削減できるため、廉価に構成できる利点がある。Next, a multilayer printed wiring board according to a third embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, the transition layer 38 is formed on the pad 24 of the IC chip 20, and the via 60 of the interlayer resin insulating layer 50 is connected to the transition layer 38.
On the other hand, in the third embodiment, the via 60 is directly connected to the pad 24 without providing a transition layer. The third embodiment has an advantage that the number of steps can be reduced as compared with the first embodiment, so that it can be configured at a low cost.

【００６８】次に、本発明の第４実施形態に係る多層プ
リント配線板について、図１２を参照して説明する。上
述した第１実施形態では、多層プリント配線板内にＩＣ
チップを収容した。これに対して、第４実施形態では、
多層プリント配線板内にＩＣチップ２０を収容すると共
に、表面にＩＣチップ１２０を載置してある。内蔵のＩ
Ｃチップ２０として演算用のＣＰＵが収容され、表面の
ＩＣチップ１２０としてキャシュメモリが載置されてい
る。Next, a multilayer printed wiring board according to a fourth embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, the IC is mounted in the multilayer printed wiring board.
Housed chips. On the other hand, in the fourth embodiment,
The IC chip 20 is accommodated in the multilayer printed wiring board, and the IC chip 120 is mounted on the surface. Built-in I
An arithmetic CPU is accommodated as the C chip 20, and a cache memory is mounted as the IC chip 120 on the surface.

【００６９】ＩＣチップ２０のパッド２４と、ＩＣチッ
プ１２０のパッド１２４とは、トラジション層３８−ビ
ア６０−導体回路５８−ビア１６０−導体回路１５８−
半田バンプ７６Ｕを介して接続されている。一方、ＩＣ
チップ１２０のパッド１２４と、ドータボード９０のパ
ッド９２とは、半田バンプ７６Ｕ−導体回路１５８−ビ
ア１６０−導体回路５８−ビア６０−スルーホール１３
６−ビア６０−導体回路５８−ビア１６０−導体回路１
５８−半田バンプ７６Ｕを介して接続されている。The pad 24 of the IC chip 20 and the pad 124 of the IC chip 120 are connected to the transition layer 38-via 60-conductor circuit 58-via 160-conductor circuit 158-
They are connected via solder bumps (76U). On the other hand, IC
The pad 124 of the chip 120 and the pad 92 of the daughter board 90 are connected to the solder bump 76U, the conductor circuit 158, the via 160, the conductor circuit 58, the via 60, and the through hole 13.
6-via 60-conductor circuit 58-via 160-conductor circuit 1
58-connected via solder bumps 76U.

【００７０】第４実施形態では、歩留まりの低いキャシ
ュメモリ１２０をＣＰＵ用のＩＣチップ２０と別に製造
しながら、ＩＣチップ２０とキャシュメモリ１２０とを
近接して配置することができ、ＩＣチップの高速動作が
可能となる。この第４実施形態では、ＩＣチップを内蔵
すると共に表面に載置することで、それぞれの機能が異
なるＩＣチップなどの電子部品を実装させることがで
き、より高機能な多層プリント配線板を得ることができ
る。なお、図示しないが、コンデンサを表面に実装する
こともできる。これにより、ＩＣチップ２０とキャシュ
メモリ１２０とコンデンサとを近接して配置することが
でき、ＩＣチップの高速動作が可能となる。In the fourth embodiment, the IC chip 20 and the cache memory 120 can be arranged close to each other while manufacturing the cache memory 120 with a low yield separately from the IC chip 20 for the CPU. Operation becomes possible. In the fourth embodiment, an electronic component such as an IC chip having a different function can be mounted by incorporating the IC chip and mounting the IC chip on the surface, thereby obtaining a multifunctional printed wiring board having a higher function. Can be. Although not shown, a capacitor can be mounted on the surface. Thereby, the IC chip 20, the cache memory 120, and the capacitor can be arranged close to each other, and high-speed operation of the IC chip can be performed.

【００７１】[0071]

【発明の効果】本発明の構造により、リード部品を介さ
ずに、ＩＣチップとプリント配線板との接続を取ること
ができる。そのため、樹脂封止も不要となる。更に、ま
た、ダイパッド上にトラジション層を設けることで、ダ
イパッドがファインピッチ（１５０μｍ）かつ／または
小サイズ（２０μｍ以下）になっても、ビルドアップ層
を積むことが可能になり、かつ、ダイパッドとバイアホ
ールとの接続性や信頼性を向上させる。更に、従来のＩ
Ｃチップの実装方法に比べて、ＩＣチップ〜基板〜外部
基板までの配線長も短くできて、ループインダクタンス
を低減できる効果もある。According to the structure of the present invention, the connection between the IC chip and the printed wiring board can be established without the intervention of a lead component. Therefore, resin sealing is not required. Furthermore, by providing a transition layer on the die pad, even if the die pad has a fine pitch (150 μm) and / or a small size (20 μm or less), a build-up layer can be stacked, and To improve the connectivity and reliability with the via holes. Furthermore, the conventional I
Compared with the mounting method of the C chip, the wiring length from the IC chip to the substrate to the external substrate can be shortened, and there is an effect that the loop inductance can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】図１（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発
明の第１実施形態に係る多層プリント配線板の製造工程
図である。FIGS. 1A, 1B, 1C, and 1D are manufacturing process diagrams of a multilayer printed wiring board according to a first embodiment of the present invention.

【図２】図２（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発
明の第１実施形態に係る多層プリント配線板の製造工程
図である。FIGS. 2A, 2B, 2C, and 2D are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

【図３】図３（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発
明の第１実施形態に係る多層プリント配線板の製造工程
図である。FIGS. 3A, 3B, 3C, and 3D are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

【図４】図４（Ａ）、（Ｂ）、（Ｃ）は、本発明の第１
実施形態に係る多層プリント配線板の製造工程図であ
る。FIGS. 4A, 4B and 4C show a first embodiment of the present invention.
It is a manufacturing process figure of the multilayer printed wiring board concerning an embodiment.

【図５】図５（Ａ）、（Ｂ）、（Ｃ）は、本発明の第１
実施形態に係る多層プリント配線板の製造工程図であ
る。FIGS. 5A, 5B and 5C show a first embodiment of the present invention.
It is a manufacturing process figure of the multilayer printed wiring board concerning an embodiment.

【図６】本発明の第１実施形態に係る多層プリント配線
板の断面図である。FIG. 6 is a sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

【図７】図７（Ａ）は、第１実施形態に係る多層プリン
ト配線板の斜視図であり、図７（Ｂ）は、該多層プリン
ト配線板の一部を拡大して示す説明図である。FIG. 7A is a perspective view of the multilayer printed wiring board according to the first embodiment, and FIG. 7B is an explanatory view showing a part of the multilayer printed wiring board in an enlarged manner. is there.

【図８】図８（Ａ）は、第１実施形態の改変例に係る多
層プリント配線板の斜視図であり、図８（Ｂ）は、該多
層プリント配線板の一部を拡大して示す説明図である。FIG. 8A is a perspective view of a multilayer printed wiring board according to a modification of the first embodiment, and FIG. 8B is an enlarged view of a part of the multilayer printed wiring board. FIG.

【図９】本発明の第１実施形態の別改変例に係る多層プ
リント配線板の断面図である。FIG. 9 is a cross-sectional view of a multilayer printed wiring board according to another modification of the first embodiment of the present invention.

【図１０】本発明の第２実施形態に係る多層プリント配
線板の断面図である。FIG. 10 is a sectional view of a multilayer printed wiring board according to a second embodiment of the present invention.

【図１１】本発明の第３実施形態に係る多層プリント配
線板の断面図である。FIG. 11 is a sectional view of a multilayer printed wiring board according to a third embodiment of the present invention.

【図１２】本発明の第４実施形態に係る多層プリント配
線板の断面図である。FIG. 12 is a sectional view of a multilayer printed wiring board according to a fourth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

２０ ＩＣチップ（電子部品） ２４ パッド ３０ コア基板 ３２ 凹部 ３６ 樹脂層 ３８ トラジション層 ５０ 層間樹脂絶縁層 ５８ 導体回路 ６０ ビア ７０ ソルダーレジスト層 ７６ 半田バンプ（端子） ９０ ドータボード（外部基板） ９６ 導電性接続ピン（端子） ９７ 導電性接着剤 １２０ ＩＣチップ（電子部品） １５０ 層間樹脂絶縁層 １５８ 導体回路 １６０ ビア Reference Signs List 20 IC chip (electronic component) 24 pad 30 core substrate 32 concave portion 36 resin layer 38 transition layer 50 interlayer resin insulating layer 58 conductive circuit 60 via 70 solder resist layer 76 solder bump (terminal) 90 daughter board (external substrate) 96 conductivity Connection pin (terminal) 97 conductive adhesive 120 IC chip (electronic component) 150 interlayer resin insulation layer 158 conductive circuit 160 via

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 23/12 Ｆ (72)発明者 王 東冬 岐阜県揖斐郡揖斐川町北方１−１ イビデ ン株式会社大垣北工場内 Ｆターム(参考） 5E346 AA43 FF45 HH07 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 23/12 F (72) Inventor Wang East winter 1-1 Ibikawa-cho, Ibi-gun, Ibi-gun, Gifu Prefecture Ibiden Co., Ltd. F-term (reference) in Ogaki north factory 5E346 AA43 FF45 HH07

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 基板上に層間絶縁層と導体層とが繰り返
し形成され、該層間絶縁層には、ビアが形成され、該ビ
アを介して電気的接続される多層プリント配線板におい
て、 前記基板には、電子部品が内蔵されていることを特徴と
する多層プリント配線板。1. A multilayer printed wiring board in which an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate, a via is formed in the interlayer insulating layer, and the substrate is electrically connected through the via. A multi-layer printed wiring board characterized by incorporating electronic components therein. 【請求項２】 表面に電子部品が実装されていることを
特徴とする請求項１に記載の多層プリント配線板。2. The multilayer printed wiring board according to claim 1, wherein an electronic component is mounted on the surface. 【請求項３】 前記基板には、外部基板と接続する端子
が配設されていることを特徴とする請求項１または２に
記載の多層プリント配線板。3. The multilayer printed wiring board according to claim 1, wherein a terminal connected to an external substrate is provided on the substrate. 【請求項４】 基板上に層間絶縁層と導体層とが繰り返
し形成され、該層間絶縁層には、ビアが形成され、該ビ
アを介して電気的接続される多層プリント配線板におい
て、 前記基板には、電子部品が内蔵され、 前記該電子部品のダイパッド上部には、最下層の層間絶
縁層のビアと接続させるためのトラジション層が形成さ
れていることを特徴とする多層プリント配線板。4. A multilayer printed wiring board in which an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate, a via is formed in the interlayer insulating layer, and the substrate is electrically connected via the via. Wherein a transition layer for connecting to a via of a lowermost interlayer insulating layer is formed above a die pad of the electronic component. 【請求項５】 前記基板は、パッケージ基板であること
を特徴とする請求項１〜４に記載の多層プリント配線
板。5. The multilayer printed wiring board according to claim 1, wherein the substrate is a package substrate.
JP2000388457A 2000-02-25 2000-12-21 Multilayer printed circuit board Expired - Lifetime JP4854845B2 (en)

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JP2000049121 2000-02-25
JP2000-78206 2000-02-25
JP2000049121 2000-02-25
JP2000078206 2000-03-21
JP2000078206 2000-03-21
JP2000-49121 2000-05-24
JP2000388457A JP4854845B2 (en) 2000-02-25 2000-12-21 Multilayer printed circuit board

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JP2002270991A (en) * 2001-03-13 2002-09-20 Ibiden Co Ltd Printed wiring board and manufacturing method therefor
JP2004247706A (en) * 2003-01-23 2004-09-02 Shinko Electric Ind Co Ltd Electronic component packaging structure and manufacturing method therefor
JP2005142466A (en) * 2003-11-10 2005-06-02 Casio Comput Co Ltd Semiconductor device, and manufacturing method thereof
JP2005158999A (en) * 2003-11-26 2005-06-16 Casio Comput Co Ltd Semiconductor device
JP2006080540A (en) * 2004-01-26 2006-03-23 Marvell World Trade Ltd Interconnection structure having two or more wings
WO2007043714A1 (en) 2005-10-14 2007-04-19 Ibiden Co., Ltd. Multilayer printed wiring board and method for manufacturing same
JP2007250595A (en) * 2006-03-13 2007-09-27 Nec Corp Semiconductor device and its manufacturing process
US7368813B2 (en) 2003-11-10 2008-05-06 Casio Computer Co., Ltd. Semiconductor device including semiconductor element surrounded by an insulating member and wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof
WO2009018586A2 (en) * 2007-07-31 2009-02-05 Occam Portfolio Llc Electronic assemblies without solder and methods for their manufacture
US7544537B2 (en) 2005-09-28 2009-06-09 Tdk Corporation Semiconductor IC-embedded substrate and method for manufacturing same
US7547975B2 (en) 2003-07-30 2009-06-16 Tdk Corporation Module with embedded semiconductor IC and method of fabricating the module
US7608480B2 (en) 2004-03-31 2009-10-27 Casio Computer Co., Ltd. Method of fabricating a semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion
US7615411B2 (en) 2003-06-03 2009-11-10 Casio Computer Co., Ltd. Semiconductor package including connected upper and lower interconnections, and manufacturing method thereof
US7868464B2 (en) 2004-09-16 2011-01-11 Tdk Corporation Multilayer substrate and manufacturing method thereof
US7929313B2 (en) 2005-12-16 2011-04-19 Ibiden Co., Ltd. Method of manufacturing multilayer printed circuit board
US7960833B2 (en) 2003-10-22 2011-06-14 Marvell World Trade Ltd. Integrated circuits and interconnect structure for integrated circuits
KR101063608B1 (en) * 2003-09-08 2011-09-07 엘지이노텍 주식회사 Printed circuit board and manufacturing method thereof
US8168893B2 (en) 2008-01-25 2012-05-01 Ibiden, Co., Ltd. Multilayer wiring board with concave portion for accomodating electronic component
US8188375B2 (en) 2005-11-29 2012-05-29 Tok Corporation Multilayer circuit board and method for manufacturing the same
US8304915B2 (en) 2008-07-23 2012-11-06 Nec Corporation Semiconductor device and method for manufacturing the same
US8692135B2 (en) 2008-08-27 2014-04-08 Nec Corporation Wiring board capable of containing functional element and method for manufacturing same
US8710639B2 (en) 2010-04-08 2014-04-29 Nec Corporation Semiconductor element-embedded wiring substrate
US8766440B2 (en) 2010-03-04 2014-07-01 Nec Corporation Wiring board with built-in semiconductor element
US20150245548A1 (en) * 2014-02-26 2015-08-27 Sparton Corporation Control of electric field effects in a printed circuit board assembly using embedded nickel-metal composite materials
JP2016531437A (en) * 2013-08-21 2016-10-06 インテル・コーポレーション Bumpless die-package interface for bumpless buildup layer (BBUL)
CN111725177A (en) * 2019-03-22 2020-09-29 奥特斯奥地利科技与系统技术有限公司 Interposer-type component carrier and method for manufacturing the same
US11716816B2 (en) 2003-09-18 2023-08-01 Imberatek, Llc Method for manufacturing an electronic module and electronic module
US11792941B2 (en) 2005-06-16 2023-10-17 Imberatek, Llc Circuit board structure and method for manufacturing a circuit board structure
USRE49970E1 (en) 2009-05-19 2024-05-14 Imberatek, Llc Manufacturing method and electronic module with new routing possibilities

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04154197A (en) * 1990-10-18 1992-05-27 Nippon Chemicon Corp Component built-in multilayer substrate
JPH05160588A (en) * 1991-12-04 1993-06-25 Hitachi Ltd Semiconductor module device
JPH08255855A (en) * 1995-03-17 1996-10-01 Nec Corp Multi-chip cooling device
JPH09321408A (en) * 1996-05-31 1997-12-12 Nec Corp High density mounting structure of electronic circuit board
JPH10189635A (en) * 1998-01-07 1998-07-21 Casio Comput Co Ltd Bonding of semiconductor device
JPH10321634A (en) * 1997-05-22 1998-12-04 Citizen Watch Co Ltd Manufacture of bump electrode
JPH11145174A (en) * 1997-11-10 1999-05-28 Sony Corp Semiconductor and manufacture of the same
JPH11220262A (en) * 1997-11-25 1999-08-10 Matsushita Electric Ind Co Ltd Circuit part built-in module and manufacture thereof
JPH11233678A (en) * 1998-02-16 1999-08-27 Sumitomo Metal Electronics Devices Inc Manufacture of ic package

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04154197A (en) * 1990-10-18 1992-05-27 Nippon Chemicon Corp Component built-in multilayer substrate
JPH05160588A (en) * 1991-12-04 1993-06-25 Hitachi Ltd Semiconductor module device
JPH08255855A (en) * 1995-03-17 1996-10-01 Nec Corp Multi-chip cooling device
JPH09321408A (en) * 1996-05-31 1997-12-12 Nec Corp High density mounting structure of electronic circuit board
JPH10321634A (en) * 1997-05-22 1998-12-04 Citizen Watch Co Ltd Manufacture of bump electrode
JPH11145174A (en) * 1997-11-10 1999-05-28 Sony Corp Semiconductor and manufacture of the same
JPH11220262A (en) * 1997-11-25 1999-08-10 Matsushita Electric Ind Co Ltd Circuit part built-in module and manufacture thereof
JPH10189635A (en) * 1998-01-07 1998-07-21 Casio Comput Co Ltd Bonding of semiconductor device
JPH11233678A (en) * 1998-02-16 1999-08-27 Sumitomo Metal Electronics Devices Inc Manufacture of ic package

Cited By (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002270991A (en) * 2001-03-13 2002-09-20 Ibiden Co Ltd Printed wiring board and manufacturing method therefor
JP2004247706A (en) * 2003-01-23 2004-09-02 Shinko Electric Ind Co Ltd Electronic component packaging structure and manufacturing method therefor
JP4489411B2 (en) * 2003-01-23 2010-06-23 新光電気工業株式会社 Manufacturing method of electronic component mounting structure
US7573135B2 (en) 2003-01-23 2009-08-11 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film
US7709942B2 (en) 2003-06-03 2010-05-04 Casio Computer Co., Ltd. Semiconductor package, including connected upper and lower interconnections
US7615411B2 (en) 2003-06-03 2009-11-10 Casio Computer Co., Ltd. Semiconductor package including connected upper and lower interconnections, and manufacturing method thereof
US7547975B2 (en) 2003-07-30 2009-06-16 Tdk Corporation Module with embedded semiconductor IC and method of fabricating the module
KR101063608B1 (en) * 2003-09-08 2011-09-07 엘지이노텍 주식회사 Printed circuit board and manufacturing method thereof
US11716816B2 (en) 2003-09-18 2023-08-01 Imberatek, Llc Method for manufacturing an electronic module and electronic module
US8026550B2 (en) 2003-10-22 2011-09-27 Marvell World Trade Ltd. Integrated circuits and interconnect structure for integrated circuits
US7982280B2 (en) 2003-10-22 2011-07-19 Marvell World Trade Ltd. Integrated circuits and interconnect structure for integrated circuits
US7960833B2 (en) 2003-10-22 2011-06-14 Marvell World Trade Ltd. Integrated circuits and interconnect structure for integrated circuits
US7368813B2 (en) 2003-11-10 2008-05-06 Casio Computer Co., Ltd. Semiconductor device including semiconductor element surrounded by an insulating member and wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof
US7563640B2 (en) 2003-11-10 2009-07-21 Casio Computer Co., Ltd. Semiconductor device including semiconductor element surrounded by an insulating member and wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof
JP2005142466A (en) * 2003-11-10 2005-06-02 Casio Comput Co Ltd Semiconductor device, and manufacturing method thereof
US7692282B2 (en) 2003-11-10 2010-04-06 Casio Computer Co., Ltd Semiconductor device including semiconductor element surrounded by an insulating member wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof
USRE43380E1 (en) 2003-11-10 2012-05-15 Teramikros, Inc. Semiconductor device including semiconductor element surrounded by an insulating member and wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof
JP2005158999A (en) * 2003-11-26 2005-06-16 Casio Comput Co Ltd Semiconductor device
JP2006080540A (en) * 2004-01-26 2006-03-23 Marvell World Trade Ltd Interconnection structure having two or more wings
US7608480B2 (en) 2004-03-31 2009-10-27 Casio Computer Co., Ltd. Method of fabricating a semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion
US7868464B2 (en) 2004-09-16 2011-01-11 Tdk Corporation Multilayer substrate and manufacturing method thereof
US11792941B2 (en) 2005-06-16 2023-10-17 Imberatek, Llc Circuit board structure and method for manufacturing a circuit board structure
US7544537B2 (en) 2005-09-28 2009-06-09 Tdk Corporation Semiconductor IC-embedded substrate and method for manufacturing same
EP1945013A4 (en) * 2005-10-14 2010-08-18 Ibiden Co Ltd Multilayer printed wiring board and method for manufacturing same
US8973259B2 (en) 2005-10-14 2015-03-10 Ibiden Co., Ltd. Method for manufacturing a multilayered circuit board
US8912451B2 (en) 2005-10-14 2014-12-16 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US8692132B2 (en) 2005-10-14 2014-04-08 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
WO2007043714A1 (en) 2005-10-14 2007-04-19 Ibiden Co., Ltd. Multilayer printed wiring board and method for manufacturing same
EP1945013A1 (en) * 2005-10-14 2008-07-16 Ibiden Co., Ltd. Multilayer printed wiring board and method for manufacturing same
US9027238B2 (en) 2005-10-14 2015-05-12 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US8101868B2 (en) 2005-10-14 2012-01-24 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US8530752B2 (en) 2005-11-29 2013-09-10 Tdk Corporation Multilayer circuit board and method for manufacturing the same
US8188375B2 (en) 2005-11-29 2012-05-29 Tok Corporation Multilayer circuit board and method for manufacturing the same
US7929313B2 (en) 2005-12-16 2011-04-19 Ibiden Co., Ltd. Method of manufacturing multilayer printed circuit board
US8320135B2 (en) 2005-12-16 2012-11-27 Ibiden Co., Ltd. Multilayer printed circuit board
US7957154B2 (en) 2005-12-16 2011-06-07 Ibiden Co., Ltd. Multilayer printed circuit board
US8705248B2 (en) 2005-12-16 2014-04-22 Ibiden Co., Ltd. Multilayer printed circuit board
JP2007250595A (en) * 2006-03-13 2007-09-27 Nec Corp Semiconductor device and its manufacturing process
US7926173B2 (en) 2007-07-05 2011-04-19 Occam Portfolio Llc Method of making a circuit assembly
WO2009018586A2 (en) * 2007-07-31 2009-02-05 Occam Portfolio Llc Electronic assemblies without solder and methods for their manufacture
WO2009018586A3 (en) * 2007-07-31 2009-05-28 Occam Portfolio Llc Electronic assemblies without solder and methods for their manufacture
US8168893B2 (en) 2008-01-25 2012-05-01 Ibiden, Co., Ltd. Multilayer wiring board with concave portion for accomodating electronic component
US8304915B2 (en) 2008-07-23 2012-11-06 Nec Corporation Semiconductor device and method for manufacturing the same
US8692135B2 (en) 2008-08-27 2014-04-08 Nec Corporation Wiring board capable of containing functional element and method for manufacturing same
USRE49970E1 (en) 2009-05-19 2024-05-14 Imberatek, Llc Manufacturing method and electronic module with new routing possibilities
US8766440B2 (en) 2010-03-04 2014-07-01 Nec Corporation Wiring board with built-in semiconductor element
US8710639B2 (en) 2010-04-08 2014-04-29 Nec Corporation Semiconductor element-embedded wiring substrate
KR101863462B1 (en) * 2013-08-21 2018-05-31 인텔 코포레이션 Bumpless die-package interface for bumpless build-up layer (bbul)
JP2016531437A (en) * 2013-08-21 2016-10-06 インテル・コーポレーション Bumpless die-package interface for bumpless buildup layer (BBUL)
US20150245548A1 (en) * 2014-02-26 2015-08-27 Sparton Corporation Control of electric field effects in a printed circuit board assembly using embedded nickel-metal composite materials
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