JP5505433B2 - Printed wiring board - Google Patents

Description

The present invention relates to a printed wiring board on which an electronic component such as an IC chip is placed, and more particularly to a printed wiring board with a built-in capacitor.

Currently, in a printed wiring board for a package substrate, a chip capacitor is sometimes surface-mounted in order to reduce loop inductance from a power source to a power source / ground of an IC chip. However, the reactance component of the loop inductance depends on the frequency. For this reason, as the driving frequency of the IC chip increases, even if a chip capacitor is mounted, the reactance of the loop inductance cannot be reduced as much as required in terms of performance.

For this reason, this inventor had the idea of accommodating a chip capacitor in a printed wiring board. As a technique for embedding a capacitor in a substrate, JP-A-6-326472, JP-A-7-263619, JP-A-10-256429, JP-A-11-45955, JP-A-11-126978, and JP-A-11-31868 are disclosed. Etc.

Japanese Patent Application Laid-Open No. 6-326472 discloses a technique of embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, it is possible to reduce power supply noise, eliminate the need for a space for mounting a chip capacitor, and reduce the size of the insulating substrate. Japanese Patent Application Laid-Open No. 7-263619 discloses a technique for embedding a capacitor in a substrate such as ceramic or alumina. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.

JP-A-6-326472 JP-A-7-263619 JP-A-10-256429 JP 11-45955 A JP-A-11-126978 JP 11-31868 A JP-A-6-326472 JP-A-7-263619

However, the above-described technology cannot reduce the distance from the IC chip to the capacitor so much, and in the further high frequency region of the IC chip, the inductance cannot be reduced as currently required. In particular, in the resin-made multilayer build-up wiring board, due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and the interlayer resin insulation layer, the disconnection between the terminal of the chip capacitor and the via hole, Peeling occurred between the chip capacitor and the interlayer resin insulation layer, and cracks occurred in the interlayer resin insulation layer, and high reliability could not be achieved over a long period of time.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board capable of reducing loop inductance.

Another object of the present invention is to provide a printed wiring board that has a built-in capacitor and can achieve high reliability.

The invention according to claim 1 includes a housing layer having a through hole, a chip capacitor housed in the through hole, and a connection layer formed on both surfaces of the housing layer and the chip capacitor. A printed wiring board,
The chip capacitor is provided with a dielectric, and first and second electrodes provided on the dielectric and extending from the connection layer side on one surface of the encasing layer to the connection layer side on the other surface, respectively. Have
The connecting layer on one surface of the accommodating layer, the via holes are connected to the first and second electrodes are formed,
The connecting layer on the other surface of the accommodating layer, the via holes are connected to the first and second electrodes are formed,
The through hole is formed immediately below the IC mounting area where the IC chip is mounted,
The IC chip is technically characterized in that it is connected to the first and second electrodes through the via holes formed in the connection layer on the IC chip side .

In the printed wiring board of the present invention, since the capacitor is arranged in the printed wiring board, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced. Further, since the capacitor is accommodated in the thick core substrate, the printed wiring board is not thickened even if the interlayer resin insulating layer and the conductor circuit are laminated on the core substrate.

It is desirable to fill the voids with resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if stress originating from the capacitor is generated, it can be relaxed by the filled resin. The resin also has an effect of reducing adhesion and migration between the capacitor and the core substrate.

In a preferred embodiment, electrical connection is established with via holes formed by plating on the electrodes of the chip capacitor formed with the metal film. Here, the electrode of the chip capacitor is made of metallization and has an uneven surface, but the surface is smoothed by the metal film, and a via hole is formed, so when a through hole is formed in the resin coated on the electrode The resin residue does not remain, and the connection reliability between the via hole and the electrode can be improved. Furthermore, since via holes are formed by plating on the plated electrodes, the connectivity between the electrodes and via holes is high, and disconnection between the electrodes and via holes may occur even when a heat cycle test is performed. Absent.

In a preferred embodiment, since a chip capacitor having an electrode formed inside the outer edge is used, even if conduction is made through a via hole, the external electrode can be made large, and the allowable range of alignment is widened, so that connection failure is eliminated.

In a preferred embodiment, a plurality of chip capacitors are used in a connected manner, that is, a large chip capacitor is used, so that a chip capacitor having a large capacity can be used. Further, even after various thermal histories, the printed wiring board is hardly warped.

In a preferred embodiment, since the metal film is formed on the electrode of the chip capacitor and the surface is smoothed, when the through hole is formed in the resin accommodated in the printed wiring board and coated on the electrode, the resin residue is not removed. Since it does not remain, the connection reliability between the via hole and the electrode can be improved.

It is a manufacturing process figure of the printed wiring board concerning the 1st reference example . It is a manufacturing process figure of the printed wiring board concerning the 1st reference example . It is a manufacturing process figure of the printed wiring board concerning the 1st reference example . It is a manufacturing process figure of the printed wiring board concerning the 1st reference example . It is a manufacturing process figure of the printed wiring board concerning the 1st reference example . It is sectional drawing of the printed wiring board which concerns on a 1st reference example . It is sectional drawing of the printed wiring board which concerns on a 1st reference example . It is a cross-sectional view of a printed wiring board according to the first embodiment form state. (A), (B) is sectional drawing of the chip capacitor of a 1st reference example , (C) is sectional drawing of the chip capacitor of 1st Embodiment . It is sectional drawing of the printed wiring board which concerns on a 2nd reference example . It is sectional drawing of the chip capacitor of (A), (B) and the 2nd reference example . It is sectional drawing of the printed wiring board which concerns on 2nd Embodiment . (A), (B), (C), (D) is a top view of a chip capacitor. It is sectional drawing of the printed wiring board which concerns on 3rd Embodiment of this invention. It is a top view of the chip capacitor of the printed wiring board concerning a 3rd embodiment . It is sectional drawing of the printed wiring board which concerns on 4th Embodiment . It is a top view of the chip capacitor of the printed wiring board concerning a 4th embodiment . It is a graph which shows the change of the supply voltage to IC chip, and time. It is sectional drawing of the printed wiring board which concerns on a 3rd reference example .

[ First Reference Example ]
Hereinafter, the first reference example will be described with reference to the drawings.
First, the configuration of the printed wiring board according to the first reference example will be described with reference to FIGS. 6 shows a cross section of the printed wiring board 10, and FIG. 7 shows a state in which the IC chip 90 is mounted on the printed wiring board 10 shown in FIG. 6 and attached to the daughter board 94 side.

As shown in FIG. 6, the printed wiring board 10 includes a chip capacitor 20, a core substrate 30 that houses the chip capacitor 20, and an interlayer resin insulating layer 60 that constitutes the buildup layers 80 </ b> A and 80 </ b> B. The core substrate 30 includes an accommodation layer 31 that accommodates the capacitor 20 and a connection layer 40. A via hole 46 and a conductor circuit 48 are formed in the connection layer 40, and a via hole 66 and a conductor circuit 68 are formed in the interlayer resin insulation layer 60. In the present embodiment, the buildup layer is composed of one interlayer resin insulation layer 60, but the buildup layer can be composed of a plurality of interlayer resin insulation layers.

As shown in FIG. 9A, the chip capacitor 20 includes a first electrode 21, a second electrode 22, and a dielectric 23 sandwiched between the first and second electrodes. A plurality of first conductive films 24 connected to the first electrode 21 side and a plurality of second conductive films 25 connected to the second electrode 22 side are arranged to face each other. In the first electrode 21 and the second electrode 22, a metal layer 26 made of copper metallization is covered with a coating layer 28 such as solder. In the first reference example , the first electrode 21 and the second electrode 22 are connected by a via hole 46 made of plating. In the printed wiring board of the first reference example , as shown in FIG. 9B, the metal layer 26 is exposed from the covering layer 28 on the top surfaces of the first electrode 21 and the second electrode 22 of the chip capacitor 20. For this reason, as shown in FIG. 6, the connectivity between the first and second electrodes 21 and 22 and the via hole 46 made of plating is improved, and the connection resistance can be reduced.

Further, a roughened layer 23 a is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. For this reason, the adhesiveness between the ceramic chip capacitor 20 and the adhesive layer 40 made of resin is high, and even if a heat cycle test is performed, the adhesive layer 40 does not peel off at the interface. The roughened layer 23a can be formed by polishing the surface of the chip capacitor 20 after firing, or by performing a roughening treatment before firing.

As shown in FIG. 7, bumps 76 for connecting to pads 92S1, 92S2, 92P1, and 92P2 of the IC chip 90 are formed in the via holes 66 of the upper buildup layer 80A. On the other hand, in the via hole 66 of the lower buildup layer 80B, bumps 76 for connecting to the pads 96S1, 96S2, 96P1, and 96P2 of the daughter board 94 are disposed. A through hole 36 is formed in the core substrate 30.

The signal pad 92S2 of the IC chip 90 is connected to the signal pad 96S2 of the daughter board 94 via the bump 76-conductor circuit 68-via hole 66-through hole 36-via hole 66-bump 76. On the other hand, the signal pad 92S1 of the IC chip 90 is connected to the signal pad 96S1 of the daughter board 94 via the bump 76-via hole 66-through hole 36-via hole 66-bump 76.

The power supply pad 92P1 of the IC chip 90 is connected to the first electrode 21 of the chip capacitor 20 via the bump 76-via hole 66-conductor circuit 48-via hole 46. On the other hand, the power supply pad 96P1 of the daughter board 94 is connected to the first electrode 21 of the chip capacitor 20 via the bump 76-via hole 66-through hole 36-conductor circuit 48-via hole 46.

The power supply pad 92P2 of the IC chip 90 is connected to the second electrode 22 of the chip capacitor 20 via the bump 76, the via hole 66, the conductor circuit 48, and the via hole 46. On the other hand, the power supply pad 96P2 of the daughter board 94 is connected to the second electrode 22 of the chip capacitor 20 via the bump 76-via hole 66-through hole 36-conductor circuit 48-via hole 46.

In the printed wiring board 10 of the first reference example , since the chip capacitor 20 is disposed directly under the IC chip 90, the distance between the IC chip and the capacitor is shortened, and power can be instantaneously supplied to the IC chip side. become. That is, the loop length that determines the loop inductance can be shortened.

Further, a through hole 36 is provided between the chip capacitor 20 and the chip capacitor 20 so that the signal line does not pass through the chip capacitor 20. For this reason, it is possible to prevent reflection due to impedance discontinuity due to the high dielectric material generated when the capacitor is passed and propagation delay due to passage through the high dielectric material.

Further, an external board (daughter board) 94 connected to the back side of the printed wiring board and the first terminal 21 and the second terminal 22 of the capacitor 20 include a via hole 46 and a core provided in the connection layer 40 on the IC chip side. The connection is made through a through hole 36 formed in the substrate. That is, since the through hole is formed in the containing layer 31 that is provided with the core material and is difficult to process and the capacitor terminal and the external substrate are not directly connected, the connection reliability can be improved.

In the first reference example , as shown in FIG. 6, an adhesive 32 is interposed between the lower surface of the through-hole 37 of the core substrate 30 and the chip capacitor 20, and the gap between the side surface of the through-hole 37 and the chip capacitor 20. Is filled with a resin filler 32a. Here, the thermal expansion coefficients of the adhesive 32 and the resin filler 32a are set to be smaller than that of the core substrate 30 and the adhesive layer 40, that is, close to the chip capacitor 20 made of ceramic. For this reason, in the heat cycle test, even if an internal stress is generated due to the difference in thermal expansion coefficient between the core substrate and the adhesive layer 40 and the chip capacitor 20, cracks, peeling, etc. are hardly generated in the core substrate and the adhesive layer 40 High reliability can be achieved. In addition, the occurrence of migration can be prevented.

The manufacturing process of the printed wiring board of the first reference example will be described with reference to FIGS.
First, a through hole 37 for accommodating a chip capacitor is formed in a laminated plate 31α formed by laminating four prepregs 35 impregnated with epoxy resin in a core material, while a laminated plate 31β formed by laminating two prepregs 35 is formed. Prepare (FIG. 1A). Here, as the prepreg, a material containing a reinforcing material such as BT, a phenol resin, or glass cloth other than epoxy can be used. However, a substrate such as ceramic or AIN cannot be used as the core substrate. This is because the substrate has poor external formability and cannot accommodate a capacitor, and even if it is filled with resin, voids are generated. Next, after stacking the laminated plate 31α and the laminated plate 31β to form the accommodating layer 31, the upper surfaces of the first and second electrodes 21 and 22 in the through hole 37 as described above with reference to FIG. The chip capacitor 20 having the coating 28 peeled off is accommodated (FIG. 1B). Here, an adhesive 32 is preferably interposed between the through hole 37 and the chip capacitor 20. The resin and the interlayer resin insulating layer used in the present application have a melting point of 300 ° C. or lower, and when a temperature of 350 ° C. or higher is applied, dissolution, softening or carbonization occurs.

Next, the resin film (connection layer) 40α is laminated on both surfaces of the accommodation layer composed of the laminate 31α and the laminate 31β that accommodate the chip capacitor 20 (FIG. 1C). Then, the surface is flattened by pressing from both sides. Thereafter, by heating and curing, the core substrate 30 including the accommodation layer 31 that accommodates the chip capacitor 20 and the connection layer 40 is formed (FIG. 1D). In the first reference example , the housing layer 31 housing the capacitor 20 and the connection layer 40 are bonded together to form the core substrate 30 by applying pressure to both surfaces, and thus the surface is flattened. Thereby, the interlayer resin insulation layer 60 and the conductor circuit 68 can be laminated so as to have high reliability in a process described later.

In addition, it is preferable to fill the side surface of the through hole 37 of the core substrate with the resin filler 32a to improve the airtightness. Further, here, the resin film 40α is laminated using a film having no metal layer, but a resin film (RCC) having a metal layer disposed on one side may be used. That is, a double-sided plate, a single-sided plate, a resin plate without a metal film, or a resin film can be used.

Next, through holes 33 of 300 to 500 μm for through holes are drilled in the interlayer resin insulating layer 40, the core substrate, and the interlayer resin insulating layer 40 (FIG. 2A). Then, non-through holes 43 reaching the first electrode 21 and the second electrode 22 of the chip capacitor 20 are formed in the interlayer resin insulating layer 40 on the upper surface side by CO2 laser, YAG laser, excimer laser or UV laser (FIG. 2 ( B)). Depending on the case, an area mask with through holes formed corresponding to the positions of the non-through holes may be placed and area processing may be performed with a laser. Furthermore, when forming the thing from which the magnitude | size and diameter of a via hole differ, you may form by the laser of mixing.

Thereafter, desmear processing is performed. Subsequently, after the surface palladium catalyst is applied, the core substrate 30 is immersed in the electroless plating solution to deposit the electroless copper plating film 44 uniformly (FIG. 2C). A roughened layer can also be formed on the surface of the electroless copper plating film 44. The roughened layer has Ra (average roughness height) = 0.01 to 5 μm. Particularly desirable is a range of 0.5 to 3 μm.

Then, a photosensitive dry film is attached to the surface of the electroless plating film 44, a mask is placed, and exposure / development processing is performed to form a resist 51 having a predetermined pattern (FIG. 3A). Here, electroless plating is used, but a metal film such as copper or nickel can be formed by sputtering. Sputtering is disadvantageous in terms of cost, but has an advantage of improving adhesion with the resin. Then, the core substrate 30 is immersed in the electrolytic plating solution, and an electric current is passed through the electroless plating film 44 to deposit the electrolytic copper plating film 45 (FIG. 3B). Then, after removing the resist 51 with 5% KOH, the electroless plating film 44 under the resist 51 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and a via is formed in the non-through hole 43 of the interlayer resin insulating layer 40. The conductor circuit 48 is formed on the surface of the hole 46 and the connection layer 40, and the through hole 36 is formed in the through hole 33 of the core substrate 30 (FIG. 3C).

A roughening layer is provided on the surface of the conductor layer of the conductor circuit 48, the via hole 46 and the through hole 36. The roughening layer is applied by an oxidation (blackening) -reduction treatment, an electroless plating film such as an alloy made of Cu-Ni-P, or an etching treatment such as an etching solution made of a cupric complex and an organic acid salt. The roughened layer has Ra (average roughness height) = 0.01 to 5 μm. Particularly desirable is a range of 0.5 to 3 μm. Although the roughened layer is formed here, it is also possible to directly fill the resin and attach the resin film as described later without forming the roughened layer.

Subsequently, the resin layer 38 is filled into the through hole 36. The resin layer may be either a non-conductive resin containing a resin such as an epoxy resin as a main component or a conductive resin containing a metal paste such as copper. In this case, what is contained in the thermosetting epoxy resin to match the coefficient of thermal expansion such as silica is filled as a resin filler. After filling the through hole 36 with the resin 38, the resin film 60α is attached (FIG. 4A). In addition, it is also possible to apply | coat resin instead of sticking a resin film. After the resin film 60α is attached, a via hole 63 having an opening diameter of 20 to 250 μm is formed in the insulating layer 60α by photo or laser and then thermally cured (FIG. 4B). Thereafter, a catalyst is applied to the core substrate and immersed in electroless plating to deposit a 0.9 μm-thick electroless plating film 64 uniformly on the surface of the interlayer resin insulation layer 60, and then a predetermined pattern is resisted 70 (FIG. 4C).

It is immersed in an electrolytic plating solution, and an electric current is passed through the electroless plating film 64 to form an electrolytic copper plating film 65 in a portion where the resist 70 is not formed (FIG. 5A). After the resist 70 is peeled and removed, the electroless plating film 64 under the plating resist is dissolved and removed to obtain a conductor circuit 68 and a via hole 66 composed of the electroless plating film 64 and the electrolytic copper plating film 65 (FIG. 5B )).

A roughened surface (not shown) may be formed on the surfaces of the conductor circuit 68 and the via hole 66 by an etching solution containing a second copper complex and an organic acid, and Sn substitution may be performed on the surface.

Solder bumps are formed on the printed wiring board described above. After applying a solder resist composition on both sides of the substrate and performing a drying process, a photomask film (not shown) on which a circular pattern (mask pattern) is drawn is placed in close contact, and exposed to ultraviolet rays. Develop. Further, heat treatment is performed to form a solder resist layer (thickness 20 μm) 72 having an opening 72a of a solder pad portion (including a via hole and its land portion) (FIG. 5C).

Then, a solder paste is filled in the opening 72a of the solder resist layer 72 (not shown). Thereafter, the solder filled in the opening 72a is reflowed at 200 ° C. to form solder bumps (solder bodies) 76 (see FIG. 6). In order to improve the corrosion resistance, a metal layer such as Ni, Au, Ag, or Pd can be formed on the opening 72a by plating or sputtering.

Next, placement of the IC chip on the printed wiring board and attachment to the daughter board will be described with reference to FIG. The IC chip 90 is mounted so that the solder pads 92S1, 92S2, 92P1, and 92P2 of the IC chip 90 correspond to the solder bumps 76 of the completed printed wiring board 10, and the IC chip 90 is attached by performing reflow. Do. Similarly, the printed wiring board 10 is attached to the daughter board 94 by reflowing the pads 96S1, 96S2, 96P1, and 96P2 of the daughter board 94 to the solder bumps 76 of the printed wiring board 10.

The resin film described above contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.

The resin film used in the production method of the present invention is a resin film in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are dispersed in a resin that is hardly soluble in an acid or oxidizing agent (hereinafter referred to as a poorly soluble resin). It is.
As used herein, the terms “poorly soluble” and “soluble” refer to those having a relatively fast dissolution rate as “soluble” for convenience when immersed in a solution of the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as “slightly soluble” for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.

The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present invention, the particle size of the soluble particles is the length of the longest part of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluorine resin, and the like, and may be composed of one of these resins. And it may consist of a mixture of two or more resins.

Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified various modified polybutadiene rubber, carboxyl group-containing (meth) acrylonitrile-butadiene rubber, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.

Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.

Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.

When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted between the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.

The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via hole opening can be formed in the interlayer resin insulating layer by exposure and development.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more.
Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.

Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.

In the resin film used in the present invention, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface with unevenness of uniform roughness can be formed, and even if a via hole or a through hole is formed in a resin film, the adhesion of the metal layer of the conductor circuit formed thereon can be secured. Because it can. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. As a result, since the portion other than the surface layer portion of the resin film is not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is reliably maintained.

In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin film is melted to the deep part of the resin film, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.

The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.

Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By containing these fillers, it is possible to improve the performance of the printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.

Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more.

The printed wiring board according to the first embodiment of the present invention will be described with reference to FIG. The printed wiring board 10 according to the first embodiment is provided with conductive pins 84 and is connected to the daughter board via the conductive pins 84. The core substrate 30 includes a housing layer 31 having through holes 37 and connection layers 40 disposed on both surfaces of the housing layer 31. Via holes 46 connected to the electrodes 21 and 22 of the chip capacitor 20 are provided in the connection layers 40 provided on both surfaces of the housing layer 31, and connected to the IC chip 90 and the conductive pins 84. Yes. In the first embodiment , as shown in FIG. 9C, the covering of the electrodes 21 and 22 of the chip capacitor 20 is completely removed.

In the first reference example described above, only the chip capacitor 20 accommodated in the core substrate 30 is provided. However, in the first embodiment , large-capacity chip capacitors 86 are mounted on the front surface and the back surface.

An IC chip consumes a large amount of power instantaneously and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in the first embodiment , the chip capacitor 20 for power supply and the chip capacitor 86 are provided on the printed wiring board. The effect of this chip capacitor will be described with reference to FIG.

In FIG. 18, the vertical axis indicates the voltage supplied to the IC chip, and the horizontal axis indicates time. Here, an alternate long and two short dashes line C indicates a voltage fluctuation of a printed wiring board that does not include a power supply capacitor. When the power supply capacitor is not provided, the voltage is greatly attenuated. A broken line A indicates voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. The voltage does not drop much as compared with the two-dot chain line C, but the loop length becomes long, so the rate-determining power supply cannot be sufficiently performed. That is, the voltage drops at the start of power supply. A two-dot chain line B indicates a voltage drop of the printed wiring board containing the chip capacitor described above with reference to FIG. Although the loop length can be shortened, the voltage fluctuates because a large-capacity chip capacitor cannot be accommodated in the core substrate 30. Here, the solid line E shows the voltage fluctuation of the printed wiring board of the first embodiment in which the chip capacitor 20 in the core substrate described above with reference to FIG. 8 and the large-capacity chip capacitor 86 are mounted on the surface. Yes. By providing the chip capacitor 20 in the vicinity of the IC chip and the chip capacitor 86 having a large capacity (and relatively large inductance), voltage fluctuation is minimized.

Next, a printed wiring board according to a second reference example will be described with reference to FIGS.
The configuration of the second reference example is substantially the same as the first reference example described above. However, in the first reference example described above, the coating of the electrodes 21 and 22 of the chip capacitor 20 was partially peeled to expose the surface of the metal layer 26. On the other hand, in the second reference example , after the chip capacitor 20 completely peels off the coating of the metal layer 26 as shown in FIG. 11A, the metal layer 26 as shown in FIG. A copper plating film 29 is coated on the surface. The coating of the plating film is formed by plating such as electrolytic plating or electroless plating. Then, as shown in FIG. 10, the first and second electrodes 21 and 22 coated with the copper plating film 29 are electrically connected by via holes 46 made of copper plating. Here, the electrodes 21 and 22 of the chip capacitor are made of metallization and have irregularities on the surface. For this reason, in the step of forming the non-through hole 43 in the connection layer 40 shown in FIG. 2B of the first reference example , the resin may remain on the unevenness. At this time, the resin residue may cause a connection failure between the first and second electrodes 21 and 22 and the via hole 46. On the other hand, in the second reference example , the surfaces of the first and second electrodes 21 and 22 are smoothed by the copper plating film 29, and when the non-through holes 43 are formed in the connection layer 40 covered on the electrodes, Residue of the resin does not remain, and connection reliability with the electrodes 21 and 22 when the via hole 46 is formed can be improved.

Furthermore, since the via hole 46 is formed by plating on the electrodes 21 and 22 on which the copper plating film 29 is formed, the connectivity between the electrodes 21 and 22 and the via hole 46 is high, and even if a heat cycle test is performed, No disconnection occurs between the electrodes 21 and 22 and the via hole 46.

Here, the coating layer 28 is removed and the copper plating film 29 is provided at the stage of accommodation in the printed wiring board, but the copper plating film 29 is directly formed on the metal layer 26 at the stage of manufacturing the chip capacitor 20. It is also possible to coat. That is, in the second reference example , an opening reaching the copper plating film 29 of the electrode is provided by a laser, and then desmear processing is performed to form a via hole by copper plating. Therefore, even if an oxide film is formed on the surface of the copper plating film 29, the oxide film can be removed by the laser and desmear treatment, so that a proper connection can be established.

Further, a roughened layer 23 a is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. For this reason, the adhesiveness between the ceramic chip capacitor 20 and the adhesive layer 40 made of resin is high, and even if a heat cycle test is performed, the adhesive layer 40 does not peel off at the interface.

Next, the configuration of the printed wiring board according to the second embodiment will be described with reference to FIGS.
The configuration of the printed wiring board 10 of the second embodiment is substantially the same as that of the first reference example described above. However, the chip capacitor 120 accommodated in the core substrate 30 is different. FIG. 13 shows a plan view of the chip capacitor. FIG. 13A shows a chip capacitor before cutting for multi-piece taking, and a one-dot chain line in the drawing indicates a cutting line. In the printed wiring board of the first reference example described above, the first electrode 21 and the second electrode 22 are disposed on the side edge of the chip capacitor as shown in the plan view of FIG. FIG. 13C shows the chip capacitor before cutting for multi-piece fabrication according to the second embodiment , and the alternate long and short dash line in the drawing indicates the cutting line. In the printed wiring board of the second embodiment , the first electrode 21 and the second electrode 22 are disposed inside the side edge of the chip capacitor as shown in the plan view of FIG.

In the printed wiring board according to the second embodiment, since the chip capacitor 120 having electrodes formed inside the outer edge is used, a chip capacitor having a large capacity can be used. In the second embodiment as well, the surface of the chip capacitor is roughened.

Next, the configuration of the printed wiring board according to the third embodiment of the present invention will be described with reference to FIGS.
FIG. 14 shows a cross section of the printed wiring board 10 of the third embodiment , and FIG. 15 shows a plan view of the chip capacitor 220 accommodated in the core substrate 30 of the printed wiring board 10. In the first reference example described above, a plurality of small-capacity chip capacitors are accommodated in the core substrate. However, in the third embodiment , a large-capacity large-sized chip capacitor 220 in which electrodes are formed in a matrix is provided on the core substrate 30. It is housed. Here, the chip capacitor 220 includes a first electrode 21, a second electrode 22, a dielectric 23, a first conductive film 24 connected to the first electrode 21, and a second electrode connected to the second electrode 22 side. The conductive film 25 and the connection electrodes 27 on the upper and lower surfaces of the chip capacitor not connected to the first conductive film 24 and the second conductive film 25 are formed. The IC chip side and the daughter board side are connected via this electrode 27.

Since the large-sized chip capacitor 220 is used in the printed wiring board of the third embodiment , a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 220 is used, the printed wiring board 10 is not warped even when the heat cycle is repeated. In the third embodiment , the surface of the chip capacitor is also roughened.

A printed wiring board according to the fourth embodiment will be described with reference to FIGS. 16 and 17. FIG. 16 shows a cross section of the printed wiring board. FIG. 17A shows a chip capacitor before cutting for multi-piece cutting. In the drawing, a one-dot chain line shows a normal cutting line, and FIG. 17B shows a plan view of the chip capacitor. . As shown in FIG. 17B, in the fourth embodiment , a plurality of chip capacitors (three in the example in the figure) are connected and used in a large format.

In the fourth embodiment , since a large chip capacitor 20 is used, a chip capacitor having a large capacity can be used. Further, since the large-sized chip capacitor 20 is used, the printed wiring board 10 is not warped even when the heat cycle is repeated. In the fourth embodiment as well, the surface of the chip capacitor is roughened.

A printed wiring board according to a third reference example will be described with reference to FIG. FIG. 19 shows a cross section of the printed wiring board. In the first reference example described above with reference to FIG. 6, one chip capacitor 20 is accommodated in the recess 32 of the core substrate 30. On the other hand, in the third reference example , a plurality of chip capacitors 20 are accommodated in the recesses 32. In the third reference example , chip capacitors can be built in with high density. In the third reference example , the surface of the chip capacitor is also roughened.

In the embodiment described above, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, a plate-like capacitor in which a conductive film is provided on a ceramic plate can be used. In the above-described embodiment, the surface of the capacitor is roughened to improve the adhesion with the resin. Alternatively, a silane coupling process can be applied to the surface of the capacitor.

Here, with respect to the printed wiring board of the second reference example , values obtained by measuring the inductance of the chip capacitor 20 embedded in the core substrate and the inductance of the chip capacitor mounted on the back surface (surface on the daughter board side) of the printed wiring board are as follows. Show.
In the case of a single capacitor, embedded type 137pH
Back mounting type 287pH

Embedded type 60pH when 8 capacitors are connected in parallel
Back mounting type 72pH
As described above, even when the capacitor is used alone, the inductance can be reduced by incorporating the chip capacitor even when they are connected in parallel to increase the capacitance.

Next, the results of the reliability test will be described. Here, in the printed wiring board of the second reference example , the change rate of the capacitance of one chip capacitor was measured.
Capacitance change rate
(Measurement frequency 100Hz) (Measurement frequency 1kHz)
Steam 168 hours: 0.3% 0.4%
HAST 100 hours: -0.9% -0.9%
TS 1000cycles: 1.1% 1.3%

The steam test was kept at 100% humidity by exposure to steam. In the HAST test, the sample was left for 100 hours at a relative humidity of 100%, an applied voltage of 1.3 V, and a temperature of 121 ° C. In the TS test, a test that was allowed to stand at -125 ° C for 30 minutes and at 55 ° C for 30 minutes was repeated 1000 lines.

In the above reliability test, it was found that a printed wiring board with a built-in chip capacitor can achieve the same reliability as the existing capacitor surface mount type. Further, as described above, in the TS test, even if internal stress occurs due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and the interlayer resin insulation layer, the chip capacitor terminals and via holes It was proved that high reliability can be achieved over a long period of time without disconnection, peeling between the chip capacitor and the interlayer resin insulation layer, and no crack in the interlayer resin insulation layer.

With the structure of the present invention, the electrical characteristics due to inductance are not deteriorated.
Further, even under reliability conditions, it does not cause peeling or cracking in the electrical characteristics or the printed wiring board. This is because no trouble occurs between the capacitor and the via hole.
In addition, since the resin is filled between the core substrate and the capacitor, even if a stress caused by the capacitor or the like is generated, the stress is alleviated and no migration occurs. Therefore, there is no influence of peeling or dissolution on the connection portion between the capacitor electrode and the via hole. Therefore, the desired performance can be maintained even if the reliability test is performed.
Also, migration can be prevented when the capacitor is covered with copper.

DESCRIPTION OF SYMBOLS 10 Printed wiring board 20 Chip capacitor 21 1st electrode 22 2nd electrode 26 Metal layer 28 Cover layer 29 Copper plating film 30 Core board 31 Housing layer 36 Through-hole 37 Through-hole 40 Connection layer 43 Non-through-hole 46 Via hole 48 Conductor circuit 60 Interlayer resin insulation layer 66 Via hole 68 Conductor circuit 84 Conductive pin 90 IC chip 94 Daughter board

Claims (6)

A printed wiring board having a housing layer having a through hole, a chip capacitor housed in the through hole, and a connection layer formed on both sides of the housing layer and the chip capacitor,
The chip capacitor is provided with a dielectric, and first and second electrodes provided on the dielectric and extending from the connection layer side on one surface of the encasing layer to the connection layer side on the other surface, respectively. Have
The connecting layer on one surface of the accommodating layer, the via holes are connected to the first and second electrodes are formed,
The connecting layer on the other surface of the accommodating layer, the via holes are connected to the first and second electrodes are formed,
The through hole is formed immediately below the IC mounting area where the IC chip is mounted,
The printed circuit board , wherein the IC chip is connected to the first and second electrodes through the via holes formed in the connection layer on the IC chip side . The printed wiring board according to claim 1, wherein the housing layer is formed by impregnating a core material with a resin . The printed wiring board according to claim 1 , wherein a resin filler is filled between a side surface of the through hole and the chip capacitor . The via hole is made of a plating mainly made of copper, and a metal film made of a plating made mainly of copper is formed on the first and second electrodes of the chip capacitor . The printed wiring board of any one of Claim 3. The printed wiring board according to claim 1 , wherein the via hole is electrically connected to a through hole penetrating the containing layer . 6. The printed wiring board according to claim 1, wherein an interlayer resin insulation layer and a conductor circuit are built up on the connection layer .

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