JP4554790B2 - Printed wiring board and printed wiring board manufacturing method - Google Patents

Description

【０１０３】
Steam試験は、蒸気に当て湿度１００％に保った。また、ＨＡＳＴ試験では、相対湿度１００％、印加電圧１．３Ｖ、温度１２１℃で１００時間放置した。ＴＳ試験では、−１２５℃で３０分、５５℃で３０分放置する試験を１０００回線り返した。
【０１０４】
上記信頼性試験において、チップコンデンサを内蔵するプリント配線板においても、既存のコンデンサ表面実装形と同等の信頼性が達成できていることが分かった。また、上述したように、ＴＳ試験において、セラミックから成るコンデンサと、樹脂からなるコア基板及び層間樹脂絶縁層の熱膨張率の違いから、内部応力が発生しても、チップコンデンサの端子とバイアホールとの間に断線、チップコンデンサと層間樹脂絶縁層との間で剥離、層間樹脂絶縁層にクラックが発生せず、長期に渡り高い信頼性を達成できることが判明した。
【０１０５】
【発明の効果】
本願発明の構造により、インダクタンスを起因とする電気特性の低下することはない。
また、コア基板とコンデンサの間に樹脂が充填されているので、コンデンサなどが起因する応力が発生しても緩和されるし、マイグレーションの発生がない。
そのために、コンデンサの電極とバイアホールの接続部への剥離や溶解などの影響がない。そのために、信頼性試験を実施しても所望の性能を保つことができるのである。
また、コンデンサの電極を銅によって被覆している場合にも、マイグレーションの発生を防止することができる。
【図面の簡単な説明】
【図１】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図２】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図３】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図４】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図５】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図６】第１実施形態に係るプリント配線板の断面図である。
【図７】第１実施形態に係るプリント配線板の断面図である。
【図８】第１実施形態の第１改変例に係るプリント配線板の断面図である。
【図９】第１実施形態の第２改変例に係るプリント配線板の製造工程図である。
【図１０】第１実施形態の第２改変例に係るプリント配線板の製造工程図である。
【図１１】第１実施形態の第２改変例に係るプリント配線板の断面図である。
【図１２】第１実施形態の第３改変例に係るプリント配線板の製造工程図である。
【図１３】第１実施形態の第３改変例に係るプリント配線板の断面図である。
【図１４】チップコンデンサの断面図である。
【図１５】ＩＣチップへの供給電圧と時間との変化を示すグラフである。
【図１６】第１実施形態の第４改変例に係るプリント配線板の断面図である。
【図１７】第４改変例のチップコンデンサの断面図である。
【図１８】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第２実施形態のプリント配線板のチップコンデンサの平面図である。
【図１９】第２実施形態の第１改変例に係るプリント配線板のチップコンデンサの平面図である。
【図２０】第２実施形態の第２改変例に係るプリント配線板のチップコンデンサの平面図である。
【図２１】（Ａ）及び（Ｂ）は、従来技術に係るプリント配線板のループインダクタンスの説明図である。
【符号の説明】
１０ プリント配線板
２０ チップコンデンサ
２１ 第１電極
２２ 第２電極
３０ コア基板
３１ 収容層
３６ スルーホール
３７ 通孔
３９ 通孔
４０ 接続層
４３ 非貫通孔
４６ バイアホール
４８ 導体回路
６０ 層間樹脂絶縁層
６６ バイアホール
６８ 導体回路
８４ 導電性ピン
９０ ＩＣチップ
９４ ドータボード[0001]
BACKGROUND OF THE INVENTION
The present invention also relates to a printed wiring board on which an electronic component such as an IC chip is placed, and particularly relates to a printed wiring board with a built-in capacitor.
[0002]
[Prior art]
Usually, in the computer, the wiring distance between the power source and the IC chip is long, and the loop inductance of this wiring portion is very large. For this reason, the fluctuation of the IC drive voltage at the time of high-speed operation becomes large, which may cause an IC malfunction. It is also difficult to stabilize the power supply voltage. For this reason, a capacitor is mounted on the surface of the printed wiring board as an auxiliary to power supply.
[0003]
That is, the loop inductance that causes voltage fluctuation is the wiring length from the power source shown in FIG. 21A to the power source terminal 272P of the IC chip 270 via the power source line in the printed wiring board 300, and the ground terminal of the IC chip 270. It depends on the wiring length from 272E to the power supply through the ground wire in the printed wiring board 300 from the power supply. In addition, the loop inductance can be reduced by narrowing the distance between the power lines and the ground lines, for example, between the wirings through which currents flow in opposite directions.
For this reason, as shown in FIG. 21B, by mounting a chip capacitor 298 on the printed wiring board 300, the inside of the printed wiring board 300 connecting the IC chip 270 and the chip capacitor 292 serving as a power supply source. The loop inductance is reduced by shortening the wiring length between the power line and the grounding wire and reducing the wiring interval.
[0004]
[Problems to be solved by the invention]
However, the magnitude of the voltage drop causing the IC drive voltage fluctuation depends on the frequency. For this reason, as the driving frequency of the IC chip increases, the loop inductance cannot be reduced even if the chip capacitor is mounted on the surface as described above with reference to FIG. It became difficult to keep it down.
[0005]
For this reason, this inventor had the idea of accommodating a chip capacitor in a printed wiring board. As a technique for embedding a capacitor in a substrate, JP-A-6-326472, JP-A-7-263619, JP-A-10-256429, JP-A-11-45955, JP-A-11-126978, and JP-A-11-31868 are disclosed. Etc.
[0006]
Japanese Patent Application Laid-Open No. 6-326472 discloses a technique of embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, it is possible to reduce power supply noise, eliminate the need for a space for mounting a chip capacitor, and reduce the size of the insulating substrate. Japanese Patent Application Laid-Open No. 7-263619 discloses a technique for embedding a capacitor in a substrate such as ceramic or alumina. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.
[0007]
[Problems to be solved by the invention]
However, the above-described technology cannot reduce the distance from the IC chip to the capacitor so much, and in the further high frequency region of the IC chip, the inductance cannot be reduced as currently required. In particular, in the resin-made multilayer build-up wiring board, due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and the interlayer resin insulation layer, the disconnection between the terminal of the chip capacitor and the via hole, Peeling occurred between the chip capacitor and the interlayer resin insulation layer, and cracks occurred in the interlayer resin insulation layer, and high reliability could not be achieved over a long period of time.
[0008]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board that can reduce loop inductance and has high reliability, and a method for manufacturing the same.
[0009]
[Means for Solving the Problems]
In order to solve the above-described problem, in claim 1, a printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate,
The core substrate is composed of a connection layer formed of an insulating resin layer that is at least one layer, and a containing layer that contains a capacitor and contains two or more resin layers ,
The connection layer is disposed on the housing layer and the capacitor,
In the connection layer, a via hole reaching the electrode of the capacitor is formed,
The connecting layer and the technical features that you have been through holes formed through said encasing layer.
[0010]
It means a circuit formed by a build-up method in which an interlayer resin insulation layer is provided on a core substrate, and via holes or through holes are provided in the interlayer resin insulation layer to form a conductor circuit as a conductive layer. For them, either a semi-additive method or a full additive method can be used.
[0011]
According to the first aspect, since the capacitor is arranged in the printed wiring board, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced. In addition, the core substrate includes at least one connection layer and a storage layer that stores the capacitor. Since the capacitor is stored in the thick storage layer, the core substrate does not become thick, and an interlayer resin is formed on the core substrate. Even if the insulating layer and the conductor circuit are laminated, the printed wiring board is not thickened.
[0012]
It is desirable to fill the voids with resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if stress originating from the capacitor is generated, it can be relaxed by the filled resin. The resin also has an effect of reducing adhesion and migration between the capacitor and the core substrate.
[0013]
In Claim 2, it is a printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate,
The core substrate includes a connection layer formed of at least one insulating resin layer and a storage layer that stores a capacitor and includes two or more resin layers, and via holes that connect the capacitor to both surfaces are provided. Formed ,
The connection layer is disposed on the housing layer and the capacitor,
The connecting layer and the technical features that you have been through holes formed through said encasing layer.
[0014]
According to the second aspect, since the capacitor is disposed in the printed wiring board, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced. In addition, the core substrate includes at least one connection layer and a storage layer that stores the capacitor. Since the capacitor is stored in the thick storage layer, the core substrate does not become thick, and an interlayer resin is formed on the core substrate. Even if the insulating layer and the conductor circuit are laminated, the printed wiring board is not thickened. Furthermore, since the vias connected to the capacitor are formed on both sides, the wiring length to the capacitor, the IC chip and the external substrate is shortened.
[0015]
According to the fifth aspect of the present invention, the wiring for connecting the IC chip and the external substrate is disposed between the capacitors, and the signal line does not pass through the capacitor. Therefore, reflection due to impedance discontinuity due to the high dielectric and propagation due to passage through the high dielectric There is no delay. By providing a capacitor for power supply, it is possible to easily supply large power to the IC chip.
By providing the grounding capacitor, it is possible to reduce noise of signal propagation of the printed wiring board.
[0016]
Further, by providing the connection wiring, it is possible to provide the wiring also under the capacitor. Therefore, the degree of freedom of wiring is increased, and the density and size can be reduced.
[0017]
According to the sixth aspect, in addition to the capacitor accommodated in the substrate, a capacitor is disposed on the surface. Since the capacitor is accommodated in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance can be reduced, and power can be supplied instantaneously. Since the capacitor is provided, a large-capacity capacitor can be attached, and a large amount of power can be easily supplied to the IC chip.
[0018]
According to the seventh aspect, since the capacitance of the capacitor on the surface is equal to or larger than the capacitance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and a desired IC chip operation is ensured.
[0019]
According to the eighth aspect of the present invention, since the inductance of the capacitor on the surface is equal to or higher than the inductance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and the desired operation of the IC chip is ensured.
[0020]
According to the ninth and tenth aspects of the present invention, electrical connection is established to the electrode of the chip capacitor formed with the metal film by a via hole formed by plating. Here, the electrode of the chip capacitor is made of metallization and has an uneven surface, but the surface is smoothed by the metal film, and a via hole is formed, so when a through hole is formed in the resin coated on the electrode The resin residue does not remain, and the connection reliability between the via hole and the electrode can be improved. Furthermore, since via holes are formed by plating on the plated electrodes, the connectivity between the electrodes and via holes is high, and disconnection between the electrodes and via holes may occur even when a heat cycle test is performed. Absent.
[0021]
The metal film of the capacitor electrode is preferably provided with any one of copper, nickel, and a noble metal. This is because a layer of tin, zinc or the like in the built-in capacitor tends to induce migration at the connection portion with the via hole. Therefore, the occurrence of migration can also be prevented.
[0022]
Further, the surface of the chip capacitor may be roughened. As a result, the adhesion between the ceramic chip capacitor and the adhesive layer made of resin and the interlayer resin insulation layer is high, and even if the heat cycle test is performed, the adhesion layer and the interlayer resin insulation layer peel off at the interface. There is no.
[0023]
According to the eleventh aspect, at least a part of the chip capacitor electrode coating layer is exposed and accommodated in the printed wiring board, and the electrode exposed from the coating layer is electrically connected. At this time, it is desirable that the metal exposed from the coating layer is mainly composed of Cu. This is because the connection resistance can be reduced.
[0024]
According to the twelfth aspect, since the chip capacitor in which the electrode is formed on the inner side of the outer edge is used, the external electrode can be made large even if conduction is made through the via hole, and the allowable range of alignment is widened.
[0025]
According to the thirteenth aspect, since a capacitor having electrodes formed in a matrix is used, a large chip capacitor can be easily accommodated in the core substrate. As a result, the capacitance can be increased, and the electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is hardly warped.
[0026]
In the fourteenth aspect, a plurality of chip capacitors may be connected to the capacitor. Thereby, the capacitance can be adjusted as appropriate, and the IC chip can be operated appropriately.
[0027]
In the fifteenth aspect, the thermal expansion coefficient of the insulating adhesive is set to be smaller than that of the encasing layer, that is, close to a capacitor made of ceramic. For this reason, in the heat cycle test, even if internal stress is generated due to the difference in thermal expansion coefficient between the housing layer and the capacitor constituting the core substrate, cracks, peeling, etc. are hardly generated in the core substrate, and high reliability is achieved. it can.
[0028]
The method for producing a printed wiring board according to claim 16 is characterized by including at least the following steps (a) to ( f ):
(A) forming a capacitor-accommodating through hole in a first resin material containing a resin in the core;
(B) a step of attaching a second resin material to the first resin material in which the through-holes are formed to form an accommodation layer having a capacitor accommodation portion;
(C) storing the capacitor in the storage layer;
(D) A step of attaching a third insulating resin layer to the containing layer in the step (c) to form a core substrate;
(E) forming a via hole by providing an opening to the capacitor electrode in the third insulating resin layer ;
(F) A step of forming a through hole by providing a through hole penetrating the third insulating resin layer and the containing layer .
[0029]
The method for producing a printed wiring board according to claim 17 has at least the following steps (a) to ( f ) as technical features:
(A) forming a capacitor-accommodating through hole in a first resin material containing a resin in the core;
(B) a step of disposing a capacitor at a position corresponding to the capacitor housing portion of the first resin material in the second resin material;
(C) a step of forming a housing layer containing a capacitor by attaching the first resin material that has undergone the step (a) and the second resin material that has undergone the step (b);
(D) attaching a third insulating resin layer to the containing layer to form a core substrate;
(E) forming a via hole by providing an opening to the capacitor electrode in the third insulating resin layer ;
(F) A step of forming a through hole by providing a through hole penetrating the third insulating resin layer and the containing layer .
[0030]
The method for producing a printed wiring board according to claim 18 is technically characterized by including at least the following steps (a) to ( g ):
(A) forming a capacitor-accommodating through hole in a first resin material containing a resin in the core;
(B) providing a through hole serving as a via hole in the second resin material and disposing the capacitor at a position corresponding to the capacitor housing portion of the first resin material;
(C) a step of forming a housing layer containing a capacitor by attaching the first resin material that has undergone the step (a) and the second resin material that has undergone the step (b);
(D) attaching a third insulating resin layer to the containing layer to form a core substrate;
(E) a step of providing an opening to the capacitor electrode in the third insulating resin layer; (f) forming a conductor film in the through hole of the first resin material and the opening of the third resin material to form a via; Process of making holes ;
(G) A step of forming a through hole by providing a through hole penetrating the third insulating resin layer and the containing layer .
[0031]
In the printed wiring board manufacturing method according to the sixteenth and fourteenth aspects, the chip capacitor can be accommodated in the core substrate, and a printed wiring board with reduced loop inductance can be provided.
[0032]
According to the printed wiring board manufacturing method of the eighteenth aspect, a chip capacitor can be accommodated in the core substrate, and a printed wiring board with reduced loop inductance can be provided. In addition, since via holes are formed on both surfaces of the core substrate, the wiring length to the capacitor, the IC chip, and the external substrate is shortened.
[0033]
In the method for manufacturing a printed wiring board according to claim 19, since the core layer is formed by applying pressure to both sides of the containing layer containing the capacitor and the third resin material, the surface is flattened and high reliability is achieved. An interlayer resin insulation layer and a conductor circuit can be laminated.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. 6 shows a cross section of the printed wiring board 10, and FIG. 7 shows a state in which the IC chip 90 is mounted on the printed wiring board 10 shown in FIG. 6 and attached to the daughter board 94 side.
[0035]
As shown in FIG. 6, the printed wiring board 10 includes a chip capacitor 20, a core substrate 30 that houses the chip capacitor 20, and an interlayer resin insulating layer 60 that constitutes the buildup layers 80 </ b> A and 80 </ b> B. The core substrate 30 includes an accommodation layer 31 that accommodates the capacitor 20 and a connection layer 40. A via hole 46 and a conductor circuit 48 are formed in the connection layer 40, and a via hole 66 and a conductor circuit 68 are formed in the interlayer resin insulation layer 60. In the present embodiment, the buildup layer is composed of one interlayer resin insulation layer 60, but the buildup layer can be composed of a plurality of interlayer resin insulation layers.
[0036]
As shown in FIG. 14, the chip capacitor 20 includes a first electrode 21, a second electrode 22, and a dielectric 23 sandwiched between the first and second electrodes. The dielectric 23 includes a first electrode A plurality of first conductive films 24 connected to the 21 side and second conductive films 25 connected to the second electrode 22 side are arranged to face each other. In the present embodiment, the first electrode 21 and the second electrode 22 are connected via a via hole 46 made of plating. Here, as shown in FIG. 14, the metal (copper) layer 26 is exposed from the coating layer 28 on the upper surfaces of the first electrode 21 and the second electrode 22. For this reason, as shown in FIG. 6, the connectivity with the via hole 46 made of copper plating is improved, and the connection resistance can be reduced.
[0037]
As shown in FIG. 7, bumps 76 for connecting to pads 92S1, 92S2, 92P1, and 92P2 of the IC chip 90 are formed in the via holes 66 of the upper buildup layer 80A. On the other hand, in the via hole 66 of the lower buildup layer 80B, bumps 76 for connecting to the pads 96S1, 96S2, 96P1, and 96P2 of the daughter board 94 are disposed. A through hole 36 is formed in the core substrate 30.
[0038]
The signal pad 92S2 of the IC chip 90 is connected to the signal pad 96S2 of the daughter board 94 via the bump 76-conductor circuit 68-via hole 66-through hole 36-via hole 66-bump 76. On the other hand, the signal pad 92S1 of the IC chip 90 is connected to the signal pad 96S1 of the daughter board 94 via the bump 76-via hole 66-through hole 36-via hole 66-bump 76.
[0039]
The power supply pad 92P1 of the IC chip 90 is connected to the first electrode 21 of the chip capacitor 20 via the bump 76-via hole 66-conductor circuit 48-via hole 46. On the other hand, the power supply pad 96P1 of the daughter board 94 is connected to the first electrode 21 of the chip capacitor 20 via the bump 76-via hole 66-through hole 36-conductor circuit 48-via hole 46.
[0040]
The power supply pad 92P2 of the IC chip 90 is connected to the second electrode 22 of the chip capacitor 20 via the bump 76, the via hole 66, the conductor circuit 48, and the via hole 46. On the other hand, the power supply pad 96P2 of the daughter board 94 is connected to the second electrode 22 of the chip capacitor 20 via the bump 76-via hole 66-through hole 36-conductor circuit 48-via hole 46.
[0041]
In the printed wiring board 10 of the present embodiment, the chip capacitor 20 is disposed immediately below the IC chip 90, so the distance between the IC chip and the capacitor is shortened, and power can be instantaneously supplied to the IC chip side. Become. That is, the loop length that determines the loop inductance can be shortened.
[0042]
Further, a through hole 36 is provided between the chip capacitor 20 and the chip capacitor 20 so that the signal line does not pass through the chip capacitor 20. For this reason, it is possible to prevent reflection due to impedance discontinuity due to the high dielectric material generated when the capacitor is passed and propagation delay due to passage through the high dielectric material.
[0043]
Further, an external board (daughter board) 94 connected to the back side of the printed wiring board and the first terminal 21 and the second terminal 22 of the capacitor 20 include a via hole 46 and a core provided in the connection layer 40 on the IC chip side. The connection is made through a through hole 36 formed in the substrate. That is, since the through hole is formed in the containing layer 31 that is provided with the core material and is difficult to process and the capacitor terminal and the external substrate are not directly connected, the connection reliability can be improved.
[0044]
Furthermore, in this embodiment, as shown in FIG. 6, an adhesive 32 is interposed between the lower surface of the through hole 37 of the core substrate 30 and the chip capacitor 20, and the side surface of the through hole 37 and the chip capacitor 20 are interposed. The resin filler 32a is filled. Here, the thermal expansion coefficients of the adhesive 32 and the resin filler 32a are set to be smaller than that of the core substrate 30 and the adhesive layer 40, that is, close to the chip capacitor 20 made of ceramic. For this reason, in the heat cycle test, even if an internal stress occurs due to a difference in thermal expansion coefficient between the core substrate and the adhesive layer 40 and the chip capacitor 20, cracks, peeling, etc. are unlikely to occur in the core substrate and the adhesive layer 40. High reliability can be achieved. In addition, migration can be prevented.
[0045]
The manufacturing process of the printed wiring board of 1st Embodiment is demonstrated with reference to FIGS.
First, a through hole 37 for accommodating a chip capacitor is formed in a laminated plate 31α formed by laminating four prepregs 35 impregnated with epoxy resin in a core material, while a laminated plate 31β formed by laminating two prepregs 35 is formed. Prepare (FIG. 1A). Here, as the prepreg, a material containing a reinforcing material such as BT, a phenol resin, or glass cloth other than epoxy can be used. Next, after stacking the laminated plate 31α and the laminated plate 31β to form the accommodating layer 31, the coating 28 on the upper surfaces of the first and second electrodes 21 and 22 in the through hole 37 as described above with reference to FIG. Then, the chip capacitor 20 from which is peeled off is accommodated (FIG. 1B). Here, an adhesive 32 is preferably interposed between the through hole 37 and the chip capacitor 20. Since the resin and interlayer resin insulating layer used in the present application have a melting point of 300 ° C. or lower, they are dissolved, softened or carbonized when a temperature exceeding 350 ° C. is applied. The adhesive 32 desirably has a thermal expansion coefficient smaller than that of the core substrate.
[0046]
It should be noted that a ceramic or AIN substrate could not be used as the core substrate. This is because the substrate has poor external formability and cannot accommodate a capacitor, and even if it is filled with resin, voids are generated.
[0047]
Next, the resin film (connection layer) 40α is laminated on both surfaces of the accommodation layer composed of the laminate 31α and the laminate 31β that accommodate the chip capacitor 20 (FIG. 1C). Then, the surface is flattened by pressing from both sides. Thereafter, by heating and curing, the core substrate 30 including the accommodation layer 31 that accommodates the chip capacitor 20 and the connection layer 40 is formed (FIG. 1D). In the present embodiment, the housing layer 31 housing the capacitor 20 and the connection layer 40 are bonded together to form the core substrate 30 by applying pressure to both surfaces, so that the surface is flattened. Thereby, the interlayer resin insulation layer 60 and the conductor circuit 68 can be laminated so as to have high reliability in a process described later.
[0048]
In addition, it is preferable to fill the side surface of the through hole 37 of the core substrate with the resin filler 32a to improve the airtightness. The resin filler 32a desirably has a smaller coefficient of thermal expansion than the core substrate. Further, here, the resin film 40α is laminated using a film having no metal layer, but a resin film (RCC) having a metal layer disposed on one side may be used. That is, a double-sided plate, a single-sided plate, a resin plate without a metal film, or a resin film can be used.
[0049]
Next, through holes 33 of 300 to 500 μm for through holes are drilled in the interlayer resin insulating layer 40, the core substrate, and the interlayer resin insulating layer 40 (FIG. 2A). Then, non-through holes 43 reaching the first electrode 21 and the second electrode 22 of the chip capacitor 20 are formed in the interlayer resin insulating layer 40 on the upper surface side by CO2 laser, YAG laser, excimer laser or UV laser (FIG. 2 ( B)). Depending on the case, an area mask with through holes formed corresponding to the positions of the non-through holes may be placed and area processing may be performed with a laser. Furthermore, when forming the thing from which the magnitude | size and diameter of a via hole differ, you may form by the laser of mixing.
[0050]
Thereafter, desmear processing is performed. Subsequently, after the surface palladium catalyst is applied, the core substrate 30 is immersed in the electroless plating solution to deposit the electroless copper plating film 44 uniformly (FIG. 2C). A roughened layer can be formed on the surface of the electroless copper plating film 44. The roughened layer has Ra (average roughness height) = 0.01 to 5 μm. Particularly desirable is a range of 0.5 to 3 μm.
[0051]
Then, a photosensitive dry film is attached to the surface of the electroless plating film 44, a mask is placed, and exposure / development processing is performed to form a resist 51 having a predetermined pattern (FIG. 3A). Here, electroless plating is used, but a metal film of copper, nickel, or the like can be formed by sputtering. Sputtering is disadvantageous in terms of cost, but has the advantage of improving the adhesion with the resin. Then, the core substrate 30 is immersed in the electrolytic plating solution, and an electric current is passed through the electroless plating film 44 to deposit the electrolytic copper plating film 45 (FIG. 3B). Then, after removing the resist 51 with 5% KOH, the electroless plating film 44 under the resist 51 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and a via is formed in the non-through hole 43 of the interlayer resin insulating layer 40. The conductor circuit 48 is formed on the surface of the hole 46 and the connection layer 40, and the through hole 36 is formed in the through hole 33 of the core substrate 30 (FIG. 3C).
[0052]
A roughening layer is provided on the surface of the conductor layer of the conductor circuit 48, the via hole 46 and the through hole 36. The roughening layer is applied by an oxidation (blackening) -reduction treatment, an electroless plating film such as an alloy made of Cu-Ni-P, or an etching treatment such as an etching solution made of a cupric complex and an organic acid salt. The roughened layer has Ra (average roughness height) = 0.01 to 5 μm. Particularly desirable is a range of 0.5 to 3 μm. Although the roughened layer is formed here, it is also possible to directly fill the resin and attach the resin film as described later without forming the roughened layer.
[0053]
Subsequently, the resin layer 38 is filled into the through hole 36. The resin layer may be either a non-conductive resin containing a resin such as an epoxy resin as a main component or a conductive resin containing a metal paste such as copper. In this case, what is contained in the thermosetting epoxy resin to match the coefficient of thermal expansion such as silica is filled as a resin filler. After filling the through hole 36 with the resin 38, the resin film 60α is attached (FIG. 4A). In addition, it is also possible to apply | coat resin instead of sticking a resin film. After the resin film 60α is attached, a via hole 63 having an opening diameter of 20 to 250 μm is formed in the insulating layer 60α by photo or laser and then thermally cured (FIG. 4B). Thereafter, a catalyst is applied to the core substrate and immersed in electroless plating to deposit a 0.9 μm-thick electroless plating film 64 uniformly on the surface of the interlayer resin insulation layer 60, and then a predetermined pattern is resisted 70 (FIG. 4C).
[0054]
It is immersed in an electrolytic plating solution, and an electric current is passed through the electroless plating film 64 to form an electrolytic copper plating film 65 in a portion where the resist 70 is not formed (FIG. 5A). After the resist 70 is peeled and removed, the electroless plating film 64 under the plating resist is dissolved and removed to obtain a conductor circuit 68 and a via hole 66 composed of the electroless plating film 64 and the electrolytic copper plating film 65 (FIG. 5B )).
[0055]
A roughened surface (not shown) was formed on the surfaces of the conductor circuit 68 and the via hole 66 by an etching solution containing a second copper complex and an organic acid. Furthermore, Sn substitution may be performed on the surface.
[0056]
Solder bumps are formed on the printed wiring board described above. After applying a solder resist composition on both sides of the substrate and performing a drying process, a photomask film (not shown) on which a circular pattern (mask pattern) is drawn is placed in close contact, and exposed to ultraviolet rays. Develop. Further, heat treatment is performed to form a solder resist layer (thickness 20 μm) 72 having an opening 72a of a solder pad portion (including a via hole and its land portion) (FIG. 5C).
[0057]
Then, a solder paste is filled in the opening 72a of the solder resist layer 72 (not shown). Thereafter, the solder filled in the opening 72a is reflowed at 200 ° C. to form solder bumps (solder bodies) 76 (see FIG. 6). In order to improve the corrosion resistance, a metal layer such as Ni, Au, Ag, or Pd can be formed on the opening 72a by plating or sputtering.
[0058]
Next, placement of the IC chip on the printed wiring board and attachment to the daughter board will be described with reference to FIG. The IC chip 90 is mounted so that the solder pads 92S1, 92S2, 92P1, and 92P2 of the IC chip 90 correspond to the solder bumps 76 of the completed printed wiring board 10, and the IC chip 90 is attached by performing reflow. Do. Similarly, the printed wiring board 10 is attached to the daughter board 94 by reflowing the pads 96S1, 96S2, 96P1, and 96P2 of the daughter board 94 to the solder bumps 76 of the printed wiring board 10.
[0059]
The resin film described above contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.
[0060]
The resin film used in the production method of the present invention is a resin film in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are dispersed in a resin that is hardly soluble in an acid or oxidizing agent (hereinafter referred to as a poorly soluble resin). It is.
As used herein, the terms “poorly soluble” and “soluble” refer to those having a relatively fast dissolution rate as “soluble” for convenience when immersed in a solution of the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as “slightly soluble” for convenience.
[0061]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
[0062]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0063]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present invention, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0064]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluorine resin, and the like, and may be composed of one of these resins. And it may consist of a mixture of two or more resins.
[0065]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified various modified polybutadiene rubber, carboxyl group-containing (meth) acrylonitrile-butadiene rubber, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.
[0066]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0067]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0068]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0069]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted between the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.
[0070]
The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via hole opening can be formed in the interlayer resin insulating layer by exposure and development.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.
[0071]
Specific examples of the hardly soluble resin include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more.
Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.
[0072]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0073]
In the resin film used in the present invention, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface with unevenness of uniform roughness can be formed, and even if a via hole or a through hole is formed in a resin film, the adhesion of the metal layer of the conductor circuit formed thereon can be secured. Because it can. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. As a result, since the portion other than the surface layer portion of the resin film is not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is reliably maintained.
[0074]
In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin film is melted to the deep part of the resin film, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.
[0075]
The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0076]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0077]
Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By containing these fillers, it is possible to improve the performance of the printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0078]
Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more.
[0079]
Next, a printed wiring board according to a modification of the first embodiment of the present invention will be described with reference to FIG. The modified printed wiring board is substantially the same as that of the first embodiment described above. However, in the printed wiring board of this modified example, the conductive pin 84 is disposed and formed so as to be connected to the daughter board via the conductive pin 84.
[0080]
In the first embodiment described above, only the chip capacitor 20 accommodated in the core substrate 30 is provided. However, in the first modified example, large-capacity chip capacitors 86 are mounted on the front surface and the back surface.
[0081]
An IC chip consumes a large amount of power instantaneously and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in the first modified example, the printed circuit board is provided with the chip capacitor 20 and the chip capacitor 86 for power supply. The effect of this chip capacitor will be described with reference to FIG.
[0082]
In FIG. 15, the vertical axis indicates the voltage supplied to the IC chip, and the horizontal axis indicates time.
Here, an alternate long and two short dashes line C indicates a voltage fluctuation of a printed wiring board that does not include a power supply capacitor. When the power supply capacitor is not provided, the voltage is greatly attenuated.
A broken line A indicates voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. The voltage does not drop much as compared with the two-dot chain line C, but the loop length becomes long, so the rate-determining power supply cannot be sufficiently performed. That is, the voltage drops at the start of power supply. A two-dot chain line B indicates a voltage drop of the printed wiring board containing the chip capacitor described above with reference to FIG. Although the loop length can be shortened, the voltage fluctuates because a large-capacity chip capacitor cannot be accommodated in the core substrate 30. Here, the solid line E shows the voltage variation of the printed wiring board of the first modified example in which the chip capacitor 20 in the core substrate described above with reference to FIG. 8 and the large-capacity chip capacitor 86 are mounted on the surface. Yes. By providing the chip capacitor 20 in the vicinity of the IC chip and the chip capacitor 86 having a large capacity (and relatively large inductance), voltage fluctuation is minimized.
[0083]
Next, a printed wiring board according to a second modification of the first embodiment of the present invention will be described with reference to FIG. The printed wiring board of the second modification is almost the same as that of the first embodiment described above. However, in the first embodiment, the connection layer 40 is disposed on both surfaces of the core substrate 30 on the housing layer 31. However, in the second embodiment, the connection layer 40 is disposed only on the upper surface of the housing layer 31. .
[0084]
A manufacturing process of the printed wiring board according to the second modification of the first embodiment will be described with reference to FIGS.
First, a through hole 37 for accommodating a chip capacitor is formed in a laminated plate 31α obtained by laminating four prepregs 35 impregnated with an epoxy resin, while a laminated plate 31β obtained by laminating two prepregs 35 is prepared. (FIG. 9A). Next, the chip capacitor 20 is placed through the adhesive 32 so as to correspond to the through hole forming position of the laminated plate 31α of the laminated plate 31β (FIG. 9B). Then, the multilayer plate 31α and the multilayer plate 31β are overlapped to form the accommodating layer 31 of the chip capacitor 20 (FIG. 9C).
[0085]
Next, a resin film (connection layer) 40α is laminated on the upper surface of the containing layer 31 including the laminated plate 31α and the laminated plate 31β that accommodates the chip capacitor 20 (FIG. 9D). Then, the surface is flattened by pressing from both sides. Thereafter, by heating and curing, the core substrate 30 including the accommodation layer 31 that accommodates the chip capacitor 20 and the connection layer 40 is formed (FIG. 10A). In the present embodiment, the housing layer 31 housing the capacitor 20 and the connection layer 40 are bonded together to form the core substrate 30 by applying pressure to both surfaces, so that the surface is flattened. Thereby, the interlayer resin insulation layer 60 and the conductor circuit 68 can be laminated so as to have high reliability.
[0086]
Next, 300 to 500 μm through holes 33 for through holes are drilled in the interlayer resin insulation layer 40, the core substrate, and the interlayer resin insulation layer 40 (FIG. 10B). Then, non-through holes 43 reaching the first electrode 21 and the second electrode 22 of the chip capacitor 20 are formed in the interlayer resin insulating layer 40 on the upper surface side by a CO2 laser, a YAG laser, an excimer laser, or a UV laser (FIG. 10 ( C)). The subsequent steps are the same as those in the first embodiment described above with reference to FIGS.
[0087]
Next, a printed wiring board according to a third modification of the first embodiment of the present invention will be described with reference to FIG. The printed wiring board of the second modified example is substantially the same as the second modified example of the first embodiment described above. However, in the second modified example, the via hole 46 is disposed only on the IC chip side of the core substrate 30, but in the third modified example, the via hole 46 is disposed not only on the IC chip side but also on the daughter board side. It is installed.
[0088]
In the third modified example, since the via hole 46 is also provided on the back side, the wiring length between the chip capacitor 20 and the daughter board can be shortened.
[0089]
A manufacturing process of the printed wiring board according to the third modification will be described with reference to FIG.
First, a through hole 37 for accommodating a chip capacitor is formed in a laminated plate 31α formed by laminating four prepregs 35 impregnated with an epoxy resin. On the other hand, a through-hole 39 that leads to the electrode is formed at the chip capacitor mounting position of the laminated plate 31β obtained by laminating two prepregs 35 (FIG. 12A). Next, the chip capacitor 20 is mounted via the adhesive 32 so as to correspond to the through hole forming position of the laminated plate 31α of the laminated plate 31β (FIG. 12B). Then, the laminated plate 31α and the laminated plate 31β are overlapped to form the containing layer 31 (FIG. 12C).
[0090]
Next, a resin film (connection layer) 40α is laminated on the upper surface of the containing layer 31 (FIG. 12D). Then, the surface is flattened by pressing from both sides. Then, the core board | substrate 30 which consists of the accommodation layer 31 which accommodates the chip capacitor 20, and the connection layer 40 is formed by heating and hardening (refer FIG. 13). The subsequent steps are the same as those in the first embodiment described above with reference to FIGS.
[0091]
Subsequently, a printed wiring board according to a fourth modification of the first embodiment will be described with reference to FIGS. 16 and 17.
The configuration of the fourth modification is the same as that of the first embodiment described above with reference to FIG. However, in the printed wiring board of the fourth modified example, the chip capacitor 20 completely peels off the coating layer 28 (see FIG. 14) of the first and second electrodes 21 and 22 as shown in FIG. It is covered with a film 29. The first and second electrodes 21 and 22 covered with the copper plating film 29 are electrically connected by via holes 46 made of copper plating. Here, the electrodes 21 and 22 of the chip capacitor are made of metallization and have irregularities on the surface. For this reason, if it is used in a state where the metal layer is exposed, the resin may remain on the unevenness in the step of forming the non-through hole 43 in the connection layer 40. At this time, the resin residue may cause a connection failure between the first and second electrodes 21 and 22 and the via hole 46. On the other hand, in the fourth modified example, the surfaces of the first and second electrodes 21 and 22 are smoothed by the copper plating film 29, and the non-through holes 43 are formed in the connection layer 40 covered on the electrodes. At this time, no resin residue remains, and the connection reliability with the electrodes 21 and 22 when the via hole 46 is formed can be improved.
[0092]
Furthermore, since the via hole 46 is formed by plating on the electrodes 21 and 22 on which the copper plating film 29 is formed, the connectivity between the electrodes 21 and 22 and the via hole 46 is high, and even if a heat cycle test is performed, No disconnection occurs between the electrodes 21 and 22 and the via hole 46. There was no migration and no inconvenience at the capacitor via-hole connection.
[0093]
The copper plating film 29 is provided after the nickel / tin layer (coating layer) coated on the surface of the metal layer 26 at the manufacturing stage of the chip capacitor is peeled off at the stage of mounting on the printed wiring board. Alternatively, the copper plating film 29 can be directly coated on the metal layer 26 at the manufacturing stage of the chip capacitor 20. That is, in the fourth modified example, as in the first embodiment, after providing an opening to the copper plating film 29 of the electrode with a laser, a desmear process or the like is performed, and the via hole is formed by copper plating.
Therefore, even if an oxide film is formed on the surface of the copper plating film 29, the oxide film can be removed by the laser and desmear treatment, so that a proper connection can be established.
[0094]
Further, a roughened layer 23 a is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. For this reason, the adhesiveness between the ceramic chip capacitor 20 and the adhesive layer 40 made of resin is high, and even if a heat cycle test is performed, the adhesive layer 40 does not peel off at the interface. The roughened layer 23a can be formed by polishing the surface of the chip capacitor 20 after firing, or by performing a roughening treatment before firing. In the fourth modified example, the surface of the capacitor is roughened to improve the adhesion to the resin. Alternatively, the surface of the capacitor can be subjected to a silane coupling treatment.
[0095]
Next, the configuration of the printed wiring board according to the second embodiment of the present invention will be described with reference to FIG.
The configuration of the printed wiring board of the second embodiment is substantially the same as that of the first embodiment described above. However, the chip capacitor 20 accommodated in the core substrate 30 is different.
FIG. 18 is a plan view of the chip capacitor. FIG. 18A shows a chip capacitor before cutting for multi-piece cutting, and a one-dot chain line in the drawing indicates a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are disposed on the side edge of the chip capacitor as shown in the plan view of FIG. FIG. 18C shows the chip capacitor before cutting for multi-piece fabrication according to the second embodiment, and the alternate long and short dash line in the drawing indicates the cutting line. In the printed wiring board of the second embodiment, the first electrode 21 and the second electrode 22 are disposed inside the side edge of the chip capacitor as shown in a plan view in FIG.
In the printed wiring board according to the second embodiment, since the chip capacitor 20 in which the electrode is formed inside the outer edge is used, a chip capacitor having a large capacity can be used.
[0096]
Subsequently, a printed wiring board according to a first modification of the second embodiment will be described with reference to FIG.
FIG. 19 is a plan view of the chip capacitor 20 accommodated in the core substrate of the printed wiring board according to the first modification. In the first embodiment described above, a plurality of small-capacity chip capacitors are accommodated in the core substrate. However, in the first modification, a large-capacity large-sized chip capacitor 20 is accommodated in the core substrate. Here, the chip capacitor 20 includes a first electrode 21, a second electrode 22, a dielectric 23, a first conductive film 24 connected to the first electrode 21, and a second electrode connected to the second electrode 22 side. The conductive film 25 and the connection electrodes 27 on the upper and lower surfaces of the chip capacitor not connected to the first conductive film 24 and the second conductive film 25 are formed. The IC chip side and the daughter board side are connected via this electrode 27.
[0097]
Since the large-sized chip capacitor 20 is used in the printed wiring board of the first modified example, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated.
[0098]
A printed wiring board according to a second modification will be described with reference to FIG. FIG. 20A shows a chip capacitor before cutting for multi-piece production. In the drawing, a one-dot chain line shows a normal cutting line, and FIG. 20B shows a plan view of the chip capacitor. . As shown in FIG. 20B, in this second modified example, a plurality of chip capacitors (three in the example in the figure) are connected and used in a large format.
[0099]
In the second modified example, since a large chip capacitor 20 is used, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated.
[0100]
In the embodiment described above, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, a plate-like capacitor in which a conductive film is provided on a ceramic plate can be used. The configuration for covering the copper plating of the fourth modification and the configuration for roughening the surface of the chip capacitor are applicable to the first embodiment, the first, second, third modification, and the second embodiment. Needless to say.
[0101]
Here, regarding the printed wiring board of the fourth modified example of the first embodiment, the inductance of the chip capacitor 20 embedded in the core substrate, the inductance of the chip capacitor mounted on the back surface (surface on the daughter board side) of the printed wiring board, and The measured value is shown.
In the case of a single capacitor, embedded type 137pH
Back mounting type 287pH
Embedded type 60pH when 8 capacitors are connected in parallel
Back mounting type 72pH
As described above, even when the capacitor is used alone, the inductance can be reduced by incorporating the chip capacitor even when they are connected in parallel to increase the capacitance.
[0102]
Next, the results of the reliability test will be described. Here, in the printed wiring board of the fourth modified example, the change rate of the capacitance of one chip capacitor was measured.

[0103]
The steam test was kept at 100% humidity by exposure to steam. In the HAST test, the sample was left for 100 hours at a relative humidity of 100%, an applied voltage of 1.3 V, and a temperature of 121 ° C. In the TS test, a test that was allowed to stand at -125 ° C for 30 minutes and 55 ° C for 30 minutes was repeated 1000 lines.
[0104]
In the above reliability test, it was found that a printed wiring board with a built-in chip capacitor can achieve the same reliability as the existing capacitor surface mount type. Further, as described above, in the TS test, even if internal stress occurs due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and the interlayer resin insulation layer, the chip capacitor terminals and via holes It was proved that high reliability can be achieved over a long period of time without disconnection, peeling between the chip capacitor and the interlayer resin insulation layer, and no crack in the interlayer resin insulation layer.
[0105]
【The invention's effect】
With the structure of the present invention, the electrical characteristics due to inductance are not deteriorated.
In addition, since the resin is filled between the core substrate and the capacitor, even if stress caused by the capacitor or the like is generated, the stress is alleviated and no migration occurs.
Therefore, there is no influence of peeling or dissolution on the connection portion between the capacitor electrode and the via hole. Therefore, the desired performance can be maintained even if the reliability test is performed.
Also, migration can be prevented when the capacitor electrode is covered with copper.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a printed wiring board according to a first embodiment of the present invention.
FIG. 2 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 3 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 4 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 5 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of the printed wiring board according to the first embodiment.
FIG. 7 is a cross-sectional view of the printed wiring board according to the first embodiment.
FIG. 8 is a cross-sectional view of a printed wiring board according to a first modification of the first embodiment.
FIG. 9 is a manufacturing process diagram of the printed wiring board according to the second modified example of the first embodiment.
FIG. 10 is a manufacturing process diagram of the printed wiring board according to the second modified example of the first embodiment.
FIG. 11 is a cross-sectional view of a printed wiring board according to a second modification of the first embodiment.
FIG. 12 is a manufacturing process diagram of the printed wiring board according to the third modified example of the first embodiment.
FIG. 13 is a cross-sectional view of a printed wiring board according to a third modification of the first embodiment.
FIG. 14 is a cross-sectional view of a chip capacitor.
FIG. 15 is a graph showing changes in supply voltage to IC chip and time.
FIG. 16 is a cross-sectional view of a printed wiring board according to a fourth modification of the first embodiment.
FIG. 17 is a cross-sectional view of a chip capacitor of a fourth modified example.
18A, 18B, 18C and 18D are plan views of a chip capacitor of a printed wiring board according to a second embodiment.
FIG. 19 is a plan view of a chip capacitor of a printed wiring board according to a first modification of the second embodiment.
FIG. 20 is a plan view of a chip capacitor of a printed wiring board according to a second modification of the second embodiment.
FIGS. 21A and 21B are explanatory diagrams of loop inductance of a printed wiring board according to the related art.
[Explanation of symbols]
10 Printed Wiring Board 20 Chip Capacitor 21 First Electrode 22 Second Electrode 30 Core Substrate 31 Housing Layer 36 Through Hole 37 Through Hole 39 Through Hole 40 Connection Layer 43 Non-Through Hole 46 Via Hole 48 Conductor Circuit 60 Interlayer Resin Insulating Layer 66 Via Hall 68 Conductor circuit 84 Conductive pin 90 IC chip 94 Daughter board

Claims (19)

A printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate,
The core substrate is composed of a connection layer formed of an insulating resin layer that is at least one layer, and a containing layer that contains a capacitor and contains two or more resin layers ,
The connection layer is disposed on the housing layer and the capacitor,
In the connection layer, a via hole reaching the electrode of the capacitor is formed,
The connecting layer and the printed wiring board characterized that you have through-holes are formed to penetrate the accommodating layer. A printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate,
The core substrate includes a connection layer formed of at least one insulating resin layer and a storage layer that stores a capacitor and includes two or more resin layers, and via holes that connect the capacitor to both surfaces are provided. Formed ,
The connection layer is disposed on the housing layer and the capacitor,
The connecting layer and the printed wiring board characterized that you have through-holes are formed to penetrate the accommodating layer.   The printed wiring board according to claim 2, wherein the via hole formed in the core substrate is made of a metal film selected from plating, sputtering, and vapor deposition.   The printed wiring board according to claim 1, wherein the housing layer and the capacitor are joined with an insulating adhesive. The printed wiring board according to claim 1, wherein a plurality of the capacitors are accommodated, and the through holes are disposed between the capacitors. The printed wiring board according to claim 1, wherein a chip capacitor is mounted on a surface of the printed wiring board. The capacitance of the chip capacitor of the surface, the printed wiring board according to claim 6, characterized in that at least the capacitance of the inner layer of the capacitor. Inductance of the chip capacitor of the surface, the printed wiring board according to claim 6, characterized in that at least the inductance of the inner layer of the capacitor.   The printed wiring board according to claim 1, wherein a metal film is formed on the electrode of the capacitor, and electrical connection is established by plating to the electrode on which the metal film is formed.   The printed wiring board according to claim 9, wherein the metal film formed on the capacitor electrode is a plating film mainly composed of copper.   9. The capacitor electrode according to claim 1, wherein at least part of the coating layer of the electrode of the capacitor is exposed, and the electrode exposed from the coating layer is electrically connected by plating. Printed wiring board.   The printed wiring board according to claim 1, wherein a chip capacitor having an electrode formed inside an outer edge is used as the capacitor.   13. The printed wiring board according to claim 1, wherein a chip capacitor having electrodes formed in a matrix is used as the capacitor.   14. The printed wiring board according to claim 1, wherein a plurality of chip capacitors for connection are used as the capacitor.   The printed wiring board according to claim 4, wherein the insulating adhesive has a smaller coefficient of thermal expansion than the encasing layer. A method for producing a printed wiring board comprising at least the following steps (a) to ( f ):
(A) forming a capacitor-accommodating through hole in a first resin material containing a resin in the core;
(B) a step of attaching a second resin material to the first resin material in which the through-holes are formed to form an accommodation layer having a capacitor accommodation portion;
(C) storing the capacitor in the storage layer;
(D) A step of attaching a third insulating resin layer to the containing layer in the step (c) to form a core substrate;
(E) forming a via hole by providing an opening to the capacitor electrode in the third insulating resin layer ;
(F) A step of forming a through hole by providing a through hole penetrating the third insulating resin layer and the containing layer . A method for producing a printed wiring board comprising at least the following steps (a) to ( f ):
(A) forming a capacitor-accommodating through hole in a first resin material containing a resin in the core;
(B) a step of disposing a capacitor at a position corresponding to the capacitor housing portion of the first resin material in the second resin material;
(C) a step of forming a housing layer containing a capacitor by attaching the first resin material that has undergone the step (a) and the second resin material that has undergone the step (b);
(D) attaching a third insulating resin layer to the containing layer to form a core substrate;
(E) forming a via hole by providing an opening to the capacitor electrode in the third insulating resin layer ;
(F) A step of forming a through hole by providing a through hole penetrating the third insulating resin layer and the containing layer . A method for producing a printed wiring board, comprising at least the following steps (a) to ( g ):
(A) forming a capacitor-accommodating through hole in a first resin material containing a resin in the core;
(B) providing a through hole serving as a via hole in the second resin material and disposing the capacitor at a position corresponding to the capacitor housing portion of the first resin material;
(C) a step of forming a housing layer containing a capacitor by attaching the first resin material that has undergone the step (a) and the second resin material that has undergone the step (b);
(D) attaching a third insulating resin layer to the containing layer to form a core substrate;
(E) providing an opening to the capacitor electrode in the third insulating resin layer;
(F) forming a via film by forming a conductor film in the through hole of the first resin material and the opening of the third resin material ;
(G) A step of forming a through hole by providing a through hole penetrating the third insulating resin layer and the containing layer .   19. The method for manufacturing a printed wiring board according to claim 16, wherein pressure is applied from both sides of the substrate at the time of attaching in the step (d).

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