JP4646371B2 - Printed wiring board and printed wiring board manufacturing method - Google Patents

Description

【００６５】
（１５）めっきレジスト６４を５％ＮａＯＨで剥離除去した後、そのめっきレジスト下のＮｉ／Ｃｕ金属層６２を硝酸および硫酸と過酸化水素の混合液を用いるエッチングにて溶解除去し、Ｎｉ／Ｃｕ金属層６２と電解めっき膜６６からなる導体回路６８およびビア５２上に接続した複数個の相対的に小さなビア６９を形成する（図５（Ｂ）参照）。本実施形態では、ビア５２をフィルドビア構造にすることにより、ビア５２に複数個のビア６９を直接接続することが可能となる。
【００６６】
（１６）次に、基板を水洗いし、乾燥した後、エッチング液を基板の両面にスプレイで吹きつけて、導体回路６８の表面をエッチングすることにより、導体回路６８の全表面に粗化面６８αを形成する（図５（Ｃ）参照）。エッチング液として、イミダゾール銅（ＩＩ）錯体１０重量部、グリコール酸７重量部、塩化カリウム５重量部およびイオン交換水７８重量部を混合したものを使用する。
【００６７】
（１７）次いで、上記（１０）〜（１６）の工程を、繰り返すことにより、さらに上層の層間樹脂絶縁層１６０及び導体回路１６８（ビア１６９を含む）を形成する（図５（Ｄ）参照）。
【００６８】
（１８）次に、ジエチレングリコールジメチルエーテル（ＤＭＤＧ）に６０重量％の濃度になるように溶解させた、クレゾールノボラック型エポキシ樹脂（日本化薬社製）のエポキシ基５０％をアクリル化した感光性付与のオリゴマー（分子量４０００）４６．６７重量部、メチルエチルケトンに溶解させた８０重量％のビスフェノールＡ型エポキシ樹脂（油化シェル社製、商品名：エピコート１００１）１５重量部、イミダゾール硬化剤（四国化成社製、商品名：２Ｅ４ＭＺ−ＣＮ）１．６重量部、感光性モノマーである多官能アクリルモノマー（共栄化学社製、商品名：Ｒ６０４）３重量部、同じく多価アクリルモノマー（共栄化学社製、商品名：ＤＰＥ６Ａ）１．５重量部、分散系消泡剤（サンノプコ社製、商品名：Ｓ−６５）０．７１重量部を容器にとり、攪拌、混合して混合組成物を調整し、この混合組成物に対して光重量開始剤としてベンゾフェノン（関東化学社製）２．０重量部、光増感剤としてのミヒラーケトン（関東化学社製）０．２重量部を加えて、粘度を２５℃で２．０Ｐａ・ｓに調整したソルダーレジスト組成物（有機樹脂絶縁材料）を得る。
なお、粘度測定は、Ｂ型粘度計（東京計器社製、ＤＶＬ−Ｂ型）で６０ｒｐｍの場合はローターNo.４、６ｒｐｍの場合はローターNo.３によった。
【００６９】
（１９）次に、基板３０の両面に、上記ソルダーレジスト組成物を２０μｍの厚さで塗布し、７０℃で２０分間、７０℃で３０分間の条件で乾燥処理を行った後、ソルダーレジストレジスト開口部のパターンが描画された厚さ５ｍｍのフォトマスクをソルダーレジスト層７０に密着させて１０００ｍＪ／ｃｍ²の紫外線で露光し、ＤＭＴＧ溶液で現像処理し、開口７１Ｕ、７１Ｄを形成する（図６（Ａ）参照）。また、ＬＰＳＲなどの市販のソルダーレジストを用いてもよい。
【００７０】
（２０）次に、ソルダーレジスト層（有機樹脂絶縁層）７０を形成した基板を、塩化ニッケル（２．３×１０^-1ｍｏｌ／ｌ）、次亞リン酸ナトリウム（２．８×１０^-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．６×１０^-1ｍｏｌ／ｌ）を含むｐＨ＝４．５の無電解ニッケルめっき液に２０分間浸漬して、開口部７１Ｕ、７１Ｄに厚さ５μｍのニッケルめっき層７２を形成する。さらに、その基板を、シアン化金カリウム（７．６×１０^-3ｍｏｌ／ｌ）、塩化アンモニウム（１．９×１０^-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．２×１０^-1ｍｏｌ／ｌ）、次亜リン酸ナトリウム（１．７×１０^-1ｍｏｌ／ｌ）を含む無電解めっき液に８０℃の条件で７．５分間浸漬して、ニッケルめっき層７２上に厚さ０．０３μｍの金めっき層７４を形成する（図６（Ｂ）参照）。
【００７１】
（２１）この後、ソルダーレジスト層７０の開口部７１Ｕ、７１Ｄに、はんだペーストを印刷して、２００℃でリフローすることにより、はんだバンプ（半田体）７６Ｕ、７６Ｄを形成する。これにより、半田バンプ７６Ｕ、７６Ｄを有するプリント配線板１０を得ることができる（図７参照）。
【００７２】
次に、上述した工程で完成したプリント配線板１０へのＩＣチップの載置および、ドータボードへの取り付けについて、図８を参照して説明する。完成したプリント配線板１０の半田バンプ７６ＵにＩＣチップ９０の半田パッド９２が対応するように、ＩＣチップ９０を載置し、リフローを行うことでＩＣチップ９０の取り付けを行う。同様に、プリント配線板１０の半田バンプ７６Ｄにドータボード９５のパッド９４が対応するように、リフローすることで、ドータボード９５へプリント配線板１０を取り付ける。
【００７３】
上述した樹脂フィルムには、難溶性樹脂、可溶性粒子、硬化剤、その他の成分が含有されている。それぞれについて以下に説明する。
【００７４】
本発明の製造方法において使用する樹脂フィルムは、酸または酸化剤に可溶性の粒子（以下、可溶性粒子という）が酸または酸化剤に難溶性の樹脂（以下、難溶性樹脂という）中に分散したものである。
なお、本発明で使用する「難溶性」「可溶性」という語は、同一の酸または酸化剤からなる溶液に同一時間浸漬した場合に、相対的に溶解速度の早いものを便宜上「可溶性」と呼び、相対的に溶解速度の遅いものを便宜上「難溶性」と呼ぶ。
【００７５】
上記可溶性粒子としては、例えば、酸または酸化剤に可溶性の樹脂粒子（以下、可溶性樹脂粒子）、酸または酸化剤に可溶性の無機粒子（以下、可溶性無機粒子）、酸または酸化剤に可溶性の金属粒子（以下、可溶性金属粒子）等が挙げられる。これらの可溶性粒子は、単独で用いても良いし、２種以上併用してもよい。
【００７６】
上記可溶性粒子の形状は特に限定されず、球状、破砕状等が挙げられる。また、上記可溶性粒子の形状は、一様な形状であることが望ましい。均一な粗さの凹凸を有する粗化面を形成することができるからである。
【００７７】
上記可溶性粒子の平均粒径としては、０．１〜１０μｍが望ましい。この粒径の範囲であれば、２種類以上の異なる粒径のものを含有してもよい。すなわち、平均粒径が０．１〜０．５μｍの可溶性粒子と平均粒径が１〜３μｍの可溶性粒子とを含有する等である。これにより、より複雑な粗化面を形成することができ、導体回路との密着性にも優れる。なお、本発明において、可溶性粒子の粒径とは、可溶性粒子の一番長い部分の長さである。
【００７８】
上記可溶性樹脂粒子としては、熱硬化性樹脂、熱可塑性樹脂等からなるものが挙げられ、酸あるいは酸化剤からなる溶液に浸漬した場合に、上記難溶性樹脂よりも溶解速度が速いものであれば特に限定されない。
上記可溶性樹脂粒子の具体例としては、例えば、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン樹脂、フッ素樹脂等からなるものが挙げられ、これらの樹脂の一種からなるものであってもよいし、２種以上の樹脂の混合物からなるものであってもよい。
【００７９】
また、上記可溶性樹脂粒子としては、ゴムからなる樹脂粒子を用いることもできる。上記ゴムとしては、例えば、ポリブタジエンゴム、エポキシ変性、ウレタン変性、（メタ）アクリロニトリル変性等の各種変性ポリブタジエンゴム、カルボキシル基を含有した（メタ）アクリロニトリル・ブタジエンゴム等が挙げられる。これらのゴムを使用することにより、可溶性樹脂粒子が酸あるいは酸化剤に溶解しやすくなる。つまり、酸を用いて可溶性樹脂粒子を溶解する際には、強酸以外の酸でも溶解することができ、酸化剤を用いて可溶性樹脂粒子を溶解する際には、比較的酸化力の弱い過マンガン酸塩でも溶解することができる。また、クロム酸を用いた場合でも、低濃度で溶解することができる。そのため、酸や酸化剤が樹脂表面に残留することがなく、後述するように、粗化面形成後、塩化パラジウム等の触媒を付与する際に、触媒が付与されなたかったり、触媒が酸化されたりすることがない。
【００８０】
上記可溶性無機粒子としては、例えば、アルミニウム化合物、カルシウム化合物、カリウム化合物、マグネシウム化合物およびケイ素化合物からなる群より選択される少なくとも一種からなる粒子等が挙げられる。
【００８１】
上記アルミニウム化合物としては、例えば、アルミナ、水酸化アルミニウム等が挙げられ、上記カルシウム化合物としては、例えば、炭酸カルシウム、水酸化カルシウム等が挙げられ、上記カリウム化合物としては、炭酸カリウム等が挙げられ、上記マグネシウム化合物としては、マグネシア、ドロマイト、塩基性炭酸マグネシウム等が挙げられ、上記ケイ素化合物としては、シリカ、ゼオライト等が挙げられる。これらは単独で用いても良いし、２種以上併用してもよい。
【００８２】
上記可溶性金属粒子としては、例えば、銅、ニッケル、鉄、亜鉛、鉛、金、銀、アルミニウム、マグネシウム、カルシウムおよびケイ素からなる群より選択される少なくとも一種からなる粒子等が挙げられる。また、これらの可溶性金属粒子は、絶縁性を確保するために、表層が樹脂等により被覆されていてもよい。
【００８３】
上記可溶性粒子を、２種以上混合して用いる場合、混合する２種の可溶性粒子の組み合わせとしては、樹脂粒子と無機粒子との組み合わせが望ましい。両者とも導電性が低くいため樹脂フィルムの絶縁性を確保することができるとともに、難溶性樹脂との間で熱膨張の調整が図りやすく、樹脂フィルムからなる層間樹脂絶縁層にクラックが発生せず、層間樹脂絶縁層と導体回路との間で剥離が発生しないからである。
【００８４】
上記難溶性樹脂としては、層間樹脂絶縁層に酸または酸化剤を用いて粗化面を形成する際に、粗化面の形状を保持できるものであれば特に限定されず、例えば、熱硬化性樹脂、熱可塑性樹脂、これらの複合体等が挙げられる。また、これらの樹脂に感光性を付与した感光性樹脂であってもよい。感光性樹脂を用いることにより、層間樹脂絶縁層に露光、現像処理を用いてビア用開口を形成することできる。
これらのなかでは、熱硬化性樹脂を含有しているものが望ましい。それにより、めっき液あるいは種々の加熱処理によっても粗化面の形状を保持することができるからである。
【００８５】
上記難溶性樹脂の具体例としては、例えば、エポキシ樹脂、フェノール樹脂、フェノキシ樹脂、ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン樹脂、フッ素樹脂等が挙げられる。これらの樹脂は単独で用いてもよいし、２種以上を併用してもよい。
さらには、１分子中に、２個以上のエポキシ基を有するエポキシ樹脂がより望ましい。前述の粗化面を形成することができるばかりでなく、耐熱性等にも優れてるため、ヒートサイクル条件下においても、金属層に応力の集中が発生せず、金属層の剥離などが起きにくいからである。
【００８６】
上記エポキシ樹脂としては、例えば、クレゾールノボラック型エポキシ樹脂、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、アルキルフェノールノボラック型エポキシ樹脂、ビフェノールＦ型エポキシ樹脂、ナフタレン型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂、フェノール類とフェノール性水酸基を有する芳香族アルデヒドとの縮合物のエポキシ化物、トリグリシジルイソシアヌレート、脂環式エポキシ樹脂等が挙げられる。これらは、単独で用いてもよく、２種以上を併用してもよい。それにより、耐熱性等に優れるものとなる。
【００８７】
本発明で用いる樹脂フィルムにおいて、上記可溶性粒子は、上記難溶性樹脂中にほぼ均一に分散されていることが望ましい。均一な粗さの凹凸を有する粗化面を形成することができ、樹脂フィルムにビアやスルーホールを形成しても、その上に形成する導体回路の金属層の密着性を確保することができるからである。また、粗化面を形成する表層部だけに可溶性粒子を含有する樹脂フィルムを用いてもよい。それによって、樹脂フィルムの表層部以外は酸または酸化剤にさらされることがないため、層間樹脂絶縁層を介した導体回路間の絶縁性が確実に保たれる。
【００８８】
上記樹脂フィルムにおいて、難溶性樹脂中に分散している可溶性粒子の配合量は、樹脂フィルムに対して、３〜４０重量％が望ましい。可溶性粒子の配合量が３重量％未満では、所望の凹凸を有する粗化面を形成することができない場合があり、４０重量％を超えると、酸または酸化剤を用いて可溶性粒子を溶解した際に、樹脂フィルムの深部まで溶解してしまい、樹脂フィルムからなる層間樹脂絶縁層を介した導体回路間の絶縁性を維持できず、短絡の原因となる場合がある。
【００８９】
上記樹脂フィルムは、上記可溶性粒子、上記難溶性樹脂以外に、硬化剤、その他の成分等を含有していることが望ましい。
上記硬化剤としては、例えば、イミダゾール系硬化剤、アミン系硬化剤、グアニジン系硬化剤、これらの硬化剤のエポキシアダクトやこれらの硬化剤をマイクロカプセル化したもの、トリフェニルホスフィン、テトラフェニルホスフォニウム・テトラフェニルボレート等の有機ホスフィン系化合物等が挙げられる。
【００９０】
上記硬化剤の含有量は、樹脂フィルムに対して０．０５〜１０重量％であることが望ましい。０．０５重量％未満では、樹脂フィルムの硬化が不十分であるため、酸や酸化剤が樹脂フィルムに侵入する度合いが大きくなり、樹脂フィルムの絶縁性が損なわれることがある。一方、１０重量％を超えると、過剰な硬化剤成分が樹脂の組成を変性させることがあり、信頼性の低下を招いたりしてしまうことがある。
【００９１】
上記その他の成分としては、例えば、粗化面の形成に影響しない無機化合物あるいは樹脂等のフィラーが挙げられる。上記無機化合物としては、例えば、シリカ、アルミナ、ドロマイト等が挙げられ、上記樹脂としては、例えば、ポリイミド樹脂、ポリアクリル樹脂、ポリアミドイミド樹脂、ポリフェニレン樹脂、メラニン樹脂、オレフィン系樹脂等が挙げられる。これらのフィラーを含有させることによって、熱膨脹係数の整合や耐熱性、耐薬品性の向上などを図りプリント配線板の性能を向上させることができる。
【００９２】
また、上記樹脂フィルムは、溶剤を含有していてもよい。上記溶剤としては、例えば、アセトン、メチルエチルケトン、シクロヘキサノン等のケトン類、酢酸エチル、酢酸ブチル、セロソルブアセテートやトルエン、キシレン等の芳香族炭化水素等が挙げられる。これらは単独で用いてもよいし、２種類以上併用してもよい。
【００９３】
引き続き、本発明の第２実施形態に係るプリント配線板１１０について、図１７を参照して説明する。上述した第１実施形態では、ＢＧＡを配設した場合で説明した。第２実施形態では、第１実施形態とほぼ同様であるが、図１７に示すように導電性接続ピン９６を介して接続を取るＰＧＡ方式に構成されている。
【００９４】
続いて、図１７を参照して上述したプリント配線板の製造方法について、図１０〜図１７を参照して説明する。
【００９５】
（１）先ず、エポキシ樹脂を含浸させたプリプレク３１を４枚積層してなる積層板３０αに、チップコンデンサ収容用の通孔３３ａを形成する。また、その一方で、プリプレク３１を２枚積層してなる積層板３０βを用意する（図１０（Ａ）参照）。ここで、プリプレク３１としては、エポキシ以外にも、ＢＴ、フェノール樹脂、あるいはガラスクロスなどの補強材を含有したものを用い得る。
【００９６】
（２）次に、積層板３０αと積層板３０βとを圧着し、加熱して硬化させることで、複数個のチップコンデンサ２０を収容可能な凹部３３を備えた、コア基板３０を形成する（図１０（Ｂ）参照）。
【００９７】
（３）そして、凹部３３のコンデンサ配設位置にポッテング（ディスペンサー）を用いて接着材料３４を塗布する（図１０（Ｃ）参照）。あるいは、印刷、ダイボンディグ、接着シートを貼り付けるなどの方法によって凹部に接着材料を塗ることができる。その後、凹部３３内にセラミックから成る複数個のチップコンデンサ２０を接着材料３４を介して収容する（図１０（Ｄ）参照）。
【００９８】
（４）その後、凹部３３内のチップコンデンサ２０間に、熱硬化性樹脂を充填し、加熱硬化して樹脂層３６を形成する（図１１（Ａ）参照）。このとき、熱硬化性樹脂としては、エポキシ、フェノール、ポリイミド、トリアジンが好ましい。
これにより、凹部３３内のチップコンデンサ２０を固定することができる。
【００９９】
（５）さらに、その上から前述したエポキシ系もしくはポリオレフィン系からなる樹脂を印刷機を用いて塗布し樹脂絶縁層４０を形成する（図１１（Ｂ）参照）。なお、樹脂を塗布する代わりに、樹脂フィルムを貼り付けてもよい。
【０１００】
（６）次に、露光・現像処理又はレーザにより樹脂絶縁層４０に相対的に大きなビア用開口４２を形成する（図１１（Ｃ）参照）。その大きなビア径は、１００〜６００μｍの範囲であることが望ましい。特に、１２５〜３５０μｍであることが望ましい。この場合は、１６５μｍで形成させた。そして、樹脂層３６にドリルまたはレーザにより、２５０μｍ径のスルーホール用の通孔４４を形成し、加熱硬化する（図１１（Ｄ）参照）。
【０１０１】
（７）そして、基板３０にパラジウム触媒を付与してから、無電解めっき液にコア基板を浸漬し、均一に無電解めっき膜４５を析出させる（図１２（Ａ）参照）。
その後、無電解めっき膜４５を形成した開口４２の内部に樹脂充填剤を充填し、乾燥する。これにより、開口４２の内部に樹脂層４７を形成する（図１２（Ｂ）参照）。
【０１０２】
（８）その後、無電解めっき膜４５の表面に感光性ドライフィルムを貼り付け、マスクを載置して、露光・現像処理し、所定パターンのレジスト４８を形成する。そして、無電解めっき液にコア基板３０を浸漬し、無電解めっき膜から成る蓋めっき５１を形成する（図１２（Ｃ）参照）。
【０１０３】
（９）上記工程の後、レジスト４８を５％のＮａＯＨで剥離した後、レジスト４８下の無電解めっき膜４５を硫酸と過酸化水素混合液でエッチングをして除去し、フィルドビア構造である相対的に大きなビア５３及びスルーホール５４を形成する（図１２（Ｄ）参照）。ビア５３をフィルドビア構造にすることにより、後述する工程で１のビア５３に複数個のビア６９を直接接続することが可能となる。
【０１０４】
（１０）そして、基板３０を水洗、酸性脱脂した後、ソフトエッチングし、次いで、エッチング液を基板３０の両面にスプレイで吹きつけて、ビア５３の表面とスルーホール５４のランド表面と内壁とをエッチングして、ビア５３及びスルーホール５４の全表面に粗化面５３αを形成する（図１３（Ａ）参照）。エッチング液としては、イミダゾール銅（ＩＩ）錯体１０重量部、グリコール酸７重量部、塩化カリウム５重量部からなるエッチング液（メック社製、メックエッチボンド）を使用する。
【０１０５】
（１１）次に、ビスフェノールＦ型エポキシモノマー（油化シェル社製、分子量：３１０、ＹＬ９８３Ｕ）１００重量部、表面にシランカップリング剤がコーティングされた平均粒径が１．６μｍで、最大粒子の直径が１５μｍ以下のＳｉＯ₂ 球状粒子（アドテック社製、ＣＲＳ １１０１−ＣＥ）１７０重量部およびレベリング剤（サンノプコ社製 ペレノールＳ４）１．５重量部を容器にとり、攪拌混合することにより、その粘度が２３±１℃で４５〜４９Ｐａ・ｓの樹脂充填剤６２を調製する。なお、硬化剤として、イミダゾール硬化剤（四国化成社製、２Ｅ４ＭＺ−ＣＮ）６．５重量部を用いた。
その後、スルーホール５４内に樹脂充填剤５６を充填して、乾燥する（図１３（Ｂ）参照）。
【０１０６】
（１２）次に、ビスフェノールＡ型エポキシ樹脂（エポキシ当量４６９，油化シェルエポキシ社製エピコート１００１）３０重量部、クレゾールノボラック型エポキシ樹脂（エポキシ当量２１５，大日本インキ化学工業社製 エピクロンＮ−６７３）４０重量部、トリアジン構造含有フェノールノボラック樹脂（フェノール性水酸基当量１２０，大日本インキ化学工業社製 フェノライトＫＡ−７０５２）３０重量部をエチルジグリコールアセテート２０重量部、ソルベントナフサ２０重量部に攪拌しながら加熱溶解させ、そこへ末端エポキシ化ポリブタジエンゴム（ナガセ化成工業社製 デナレックスＲ−４５ＥＰＴ）１５重量部と２−フェニル−４、５−ビス（ヒドロキシメチル）イミダゾール粉砕品１．５重量部、微粉砕シリカ２重量部、シリコン系消泡剤０．５重量部を添加しエポキシ樹脂組成物を調製する。
得られたエポキシ樹脂組成物を厚さ３８μｍのＰＥＴフィルム上に乾燥後の厚さが５０μｍとなるようにロールコーターを用いて塗布した後、８０〜１２０℃で１０分間乾燥させることにより、層間樹脂絶縁層用樹脂フィルムを作製する。
【０１０７】
（１３）基板の両面に、（１２）で作製した基板３０より少し大きめの層間樹脂絶縁層用樹脂フィルムを基板３０上に載置し、圧力４ｋｇｆ／ｃｍ² 、温度８０℃、圧着時間１０秒の条件で仮圧着して裁断した後、さらに、以下の方法により真空ラミネーター装置を用いて貼り付けることにより層間樹脂絶縁層６０を形成する（図１３（Ｃ）参照）。すなわち、層間樹脂絶縁層用樹脂フィルムを基板３０上に、真空度０．５Ｔｏｒｒ、圧力４ｋｇｆ／ｃｍ² 、温度８０℃、圧着時間６０秒の条件で本圧着し、その後、１７０℃で３０分間熱硬化させる。
【０１０８】
（１４）次に、層間樹脂絶縁層６０上に、厚さ１．２ｍｍの貫通孔５７ａが形成されたマスク５７を介して、ＣＯ₂ ガスレーザで層間樹脂絶縁層６０に、６５μｍの相対的に小さなビア用開口６１を形成する（図１３（Ｄ）参照）。相対的に小さなビア径は、２５〜１００μｍの範囲であることが望ましい。
【０１０９】
（１５）ビア用開口６１を形成した基板３０を、６０ｇ／ｌの過マンガン酸を含む８０℃の溶液に１０分間浸漬し、層間樹脂絶縁層６０の表面に存在するエポキシ樹脂粒子を溶解除去することにより、ビア用開口６１の内壁を含む層間樹脂絶縁層６０の表面を粗化面６０αとする（図１４（Ａ）参照）。酸あるいは酸化剤によって粗化処理を施してもよい。また、粗化層は、０．１〜５μｍが望ましい。
【０１１０】
（１６）次に、上記処理を終えた基板３０を、中和溶液（シプレイ社製）に浸漬してから水洗いする。さらに、粗面化処理（粗化深さ３μｍ）した該基板３０の表面に、パラジウム触媒を付与することにより、層間樹脂絶縁層６０の表面およびビア用開口６１の内壁面に触媒核を付着させる。
【０１１１】
（１７）次に、以下の組成の無電解銅めっき水溶液中に基板３０を浸漬して、粗化面６０α全体に厚さ０．６〜３．０μｍの無電解銅めっき膜６３を形成する（図１４（Ｂ）参照）。
〔無電解めっき水溶液〕
ＮｉＳＯ₄ ０．００３ ｍｏｌ／ｌ
酒石酸 ０．２００ ｍｏｌ／ｌ
硫酸銅 ０．０３０ ｍｏｌ／ｌ
ＨＣＨＯ ０．０５０ ｍｏｌ／ｌ
ＮａＯＨ ０．１００ ｍｏｌ／ｌ
α、α′−ビピリジル ４０ ｍｇ／ｌ
ポリエチレングリコール（ＰＥＧ） ０．１０ ｇ／ｌ
〔無電解めっき条件〕
３５℃の液温度で４０分
【０１１２】
（１８）市販の感光性ドライフィルムを無電解銅めっき膜６３に貼り付け、マスクを載置して、１００ｍＪ／ｃｍ² で露光し、０．８％炭酸ナトリウム水溶液で現像処理することにより、厚さ３０μｍのめっきレジスト６４を設ける。次いで、基板３０を５０℃の水で洗浄して脱脂し、２５℃の水で水洗後、さらに硫酸で洗浄してから、以下の条件で電解めっきを施し、厚さ２０μｍの電解銅めっき膜６６を形成する（図１４（Ｃ）参照）。
〔電解めっき水溶液〕
硫酸 ２．２４ ｍｏｌ／ｌ
硫酸銅 ０．２６ ｍｏｌ／ｌ
添加剤 １９．５ ｍｌ／ｌ
（アトテックジャパン社製、カパラシドＨＬ）
〔電解めっき条件〕
電流密度 １ Ａ／ｄｍ²
時間 ６５ 分
温度 ２２±２ ℃
【０１１３】
（１９）めっきレジスト６４を５％ＮａＯＨで剥離除去した後、そのめっきレジスト６４下の無電解銅めっき膜６３を硫酸と過酸化水素の混合液でエッチング処理して溶解除去し、無電解銅めっき膜６３と電解銅めっき膜６６からなる厚さ１８μｍの導体回路６８および相対的に小さなビア６９を形成する（図１４（Ｄ）参照）。その後、（１０）と同様の処理を行い、第二銅錯体と有機酸とを含有するエッチング液によって、粗化面６８αを形成する（図１５（Ａ）参照）。
【０１１４】
（２０）続いて、上記（１３）〜（１９）の工程を繰り返すことにより、さらに上層の層間樹脂絶縁層１６０及び導体回路１６８およびビア１６９を形成する（図１５（Ｂ）参照）。
【０１１５】
（２１）次に、ジエチレングリコールジメチルエーテル（ＤＭＤＧ）に６０重量％の濃度になるように溶解させた、クレゾールノボラック型エポキシ樹脂（日本化薬社製）のエポキシ基５０％をアクリル化した感光性付与のオリゴマー（分子量４０００）４６．６７重量部、メチルエチルケトンに溶解させた８０重量％のビスフェノールＡ型エポキシ樹脂（油化シェル社製、商品名：エピコート１００１）１５重量部、イミダゾール硬化剤（四国化成社製、商品名：２Ｅ４ＭＺ−ＣＮ）１．６重量部、感光性モノマーである２官能アクリルモノマー（共栄化学社製、商品名：Ｒ６０４）４．５重量部、同じく多価アクリルモノマー（共栄化学社製、商品名：ＤＰＥ６Ａ）１．５重量部、分散系消泡剤（サンノプコ社製、商品名：Ｓ−６５）０．７１重量部を容器にとり、攪拌、混合して混合組成物を調整し、この混合組成物に対して光重量開始剤としてベンゾフェノン（関東化学社製）２．０重量部、光増感剤としてのミヒラーケトン（関東化学社製）０．２重量部を加えて、粘度を２５℃で２．０Ｐａ・ｓに調整したソルダーレジスト組成物（有機樹脂絶縁材料）を得る。
なお、粘度測定は、Ｂ型粘度計（東京計器社製、ＤＶＬ−Ｂ型）で６０ｒｐｍの場合はローターNo.４、６ｒｐｍの場合はローターNo.３によった。
【０１１６】
（２２）次に、多層配線基板の両面に、（２１）で調製したソルダーレジスト組成物を２０μｍの厚さで塗布する。その後、７０℃で２０分間、７０℃で３０分間の条件で乾燥処理を行った後、ソルダーレジスト開口部のパターンが描画された厚さ５ｍｍのフォトマスクをソルダーレジスト組成物に密着させて１０００ｍＪ／ｃｍ² の紫外線で露光し、ＤＭＴＧ溶液で現像処理し、開口７１Ｕ、７１Ｄを形成する。
そして、さらに、８０℃で１時間、１００℃で１時間、１２０℃で１時間、１５０℃で３時間の条件でそれぞれ加熱処理を行ってソルダーレジスト組成物を硬化させ、開口７１Ｕ、７１Ｄを有する、厚さ２０μｍのソルダーレジスト層７０を形成する（図１６（Ａ）参照）。上記ソルダーレジスト組成物としては、市販のソルダーレジスト組成物を使用することもできる。
【０１１７】
（２３）次に、ソルダーレジスト層７０を形成した基板を、塩化ニッケル（２．３×１０^-1ｍｏｌ／ｌ）、次亜リン酸ナトリウム（２．８×１０^-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．６×１０^-1ｍｏｌ／ｌ）を含むｐＨ＝４．５の無電解ニッケルめっき液に２０分間浸漬して、開口部７１Ｕ、７１Ｄに厚さ５μｍのニッケルめっき層７２を形成する。さらに、その基板をシアン化金カリウム（７．６×１０^-3ｍｏｌ／ｌ）、塩化アンモニウム（１．９×１０^-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．２×１０^-1ｍｏｌ／ｌ）、次亜リン酸ナトリウム（１．７×１０^-1ｍｏｌ／ｌ）を含む無電解金めっき液に８０℃の条件で７．５分間浸漬して、ニッケルめっき層７２上に、厚さ０．０３μｍの金めっき層７４を形成する（図１６（Ｂ）参照）。
【０１１８】
（２４）この後、基板のＩＣチップを載置する面のソルダーレジスト層７０の開口７１Ｕにスズ−鉛を含有する半田ペーストを印刷する。さらに、他方の面の開口部７１Ｄ内に導電性接着剤９７として半田ペーストを印刷する。次に、導電性接続ピン９６を適当なピン保持装置に取り付けて支持し、導電性接続ピン９６の固定部９８を開口部７１Ｄ内の導電性接着剤９７に当接させる。そしてリフローを行い、導電性接続ピン９６を導電性接着剤９７に固定する。また、導電性接続ピン９６の取り付け方法としては、導電性接着剤９７をボール状等に形成したものを開口部７１Ｄ内に入れる、あるいは、固定部９８に導電性接着剤９７を接合させて導電性接続ピン９６を取り付け、その後にリフローさせてもよい。
【０１１９】
その後、プリント配線板１１０の開口７１Ｕ側の半田バンプ７６にＩＣチップ９０の半田パッド９２が対応するように、ＩＣチップ９０を載置し、リフローを行うことでＩＣチップ９０の取り付けを行う（図１７参照）。
【０１２０】
引き続き、本発明の第３実施形態に係るプリント配線板について、図１８を参照して説明する。第３実施形態のプリント配線板２１０は、上述した第１実施形態とほぼ同様である。但し、この第３実施形態のプリント配線板２１０では、コア基板３０に形成された凹部３５に一個のチップコンデンサ２０が収容されている。コア基板３０内にチップコンデンサ２０を配置するため、ＩＣチップ９０とチップコンデンサ２０との距離が短くなり、ループインダクタンスを低減することが可能となる。
【０１２１】
引き続き、本発明の第４実施形態に係るプリント配線板について、図２０を参照して説明する。上述した第１実施形態では、コア基板３０に収容されるチップコンデンサ２０のみを備えていたが、第４実施形態では、表面及び裏面に大容量のチップコンデンサ９８が実装されている。
【０１２２】
ＩＣチップは、瞬時的に大電力を消費して複雑な演算処理を行う。ここで、ＩＣチップ側に大電力を供給するために、改変例では、プリント配線板に電源用のチップコンデンサ２０及びチップコンデンサ９８を備えてある。このチップコンデンサによる効果について、図２１を参照して説明する。
【０１２３】
図２１は、縦軸にＩＣチップへ供給される電圧を、横軸に時間を取ってある。
ここで、二点鎖線Ｃは、電源用コンデンサを備えないプリント配線板の電圧変動を示している。電源用コンデンサを備えない場合には、大きく電圧が減衰する。破線Ａは、表面にチップコンデンサを実装したプリント配線板の電圧変動を示している。上記二点鎖線Ｃと比較して電圧は大きく落ち込まないが、ループ長さが長くなるので、律速の電源供給が十分に行えていない。即ち、電力の供給開始時に電圧が降下している。また、二点鎖線Ｂは、図７を参照して上述したチップコンデンサを内蔵するプリント配線板の電圧降下を示している。ループ長さは短縮できているが、コア基板３０に容量の大きなチップコンデンサを収容することができないため、電圧が変動している。ここで、実線Ｅは、図２０を参照して上述したコア基板内のチップコンデンサ２０を、また表面に大容量のチップコンデンサ９８を実装する第４実施形態のプリント配線板の電圧変動を示している。ＩＣチップの近傍にチップコンデンサ２０を、また、大容量（及び相対的に大きなインダクタンス）のチップコンデンサ９８を備えることで、電圧変動を最小に押さえている。
【０１２４】
引き続き、本発明の第５実施形態に係るプリント配線板の構成について図２２を参照して説明する。
この第５実施形態のプリント配線板の構成は、上述した第１実施形態とほぼ同様である。但し、コア基板３０への収容されるチップコンデンサ２０が異なる。図２２は、チップコンデンサの平面図を示している。図２２（Ａ）は、多数個取り用の裁断前のチップコンデンサを示し、図中で一点鎖線は、裁断線を示している。上述した第１実施形態のプリント配線板では、図２２（Ｂ）に平面図を示すようにチップコンデンサの側縁に第１電極２１及び第２電極２２を配設してある。図２２（Ｃ）は、第５実施形態の多数個取り用の裁断前のチップコンデンサを示し、図中で一点鎖線は、裁断線を示している。第５実施形態のプリント配線板では、図２２（Ｄ）に平面図を示すようにチップコンデンサの側縁の内側に第１電極２１及び第２電極２２を配設してある。
【０１２５】
この第５実施形態のプリント配線板では、外縁の内側に電極の形成されたチップコンデンサ２０を用いるため、容量の大きなチップコンデンサを用いることができる。
引き続き、第５実施形態の第１改変例に係るプリント配線板について図２３を参照して説明する。
図２３は、第１改変例に係るプリント配線板のコア基板に収容されるチップコンデンサ２０の平面図を示している。上述した第１実施形態では、複数個の小容量のチップコンデンサをコア基板に収容したが、第１改変例では、大容量の大判のチップコンデンサ２０をコア基板に収容してある。ここで、チップコンデンサ２０は、第１電極２１と第２電極２２と、誘電体２３と、第１電極２１へ接続された第１導電膜２４と、第２電極２２側に接続された第２導電膜２５と、第１導電膜２４及び第２導電膜２５へ接続されていないチップコンデンサの上下面の接続用の電極２７とから成る。この電極２７を介してＩＣチップ側とドータボード側とが接続されている。
【０１２６】
この第１改変例のプリント配線板では、大判のチップコンデンサ２０を用いるため、容量の大きなチップコンデンサを用いることができる。また、大判のチップコンデンサ２０を用いるため、ヒートサイクルを繰り返してもプリント配線板に反りが発生することがない。
【０１２７】
図２４を参照して第２改変例に係るプリント配線板について説明する。図２４（Ａ）は、多数個取り用の裁断前のチップコンデンサを示し、図中で一点鎖線は、通常の裁断線を示し、図２４（Ｂ）は、チップコンデンサの平面図を示している。図２４（Ｂ）に示すように、この第２改変例では、多数個取り用のチップコンデンサを複数個（図中の例では３枚）連結させて大判で用いている。
【０１２８】
この第２改変例では、大判のチップコンデンサ２０を用いるため、容量の大きなチップコンデンサを用いることができる。また、大判のチップコンデンサ２０を用いるため、ヒートサイクルを繰り返してもプリント配線板に反りが発生することがない。
【０１２９】
上述した第５実施形態では、チップコンデンサをプリント配線板に内蔵させたが、チップコンデンサの代わりに、セラミック板に導電体膜を設けてなる板状のコンデンサを用いることも可能である。
【０１３０】
ここで、第１実施形態のプリント配線板について、コア基板内に埋め込んだチップコンデンサ２０のインダクタンスと、プリント配線板の裏面（ドータボード側の面）に実装したチップコンデンサのインダクタンスとを測定した値を以下に示す。
コンデンサ単体の場合
埋め込み形 １３７pH
裏面実装形 ２８７pH
コンデンサを８個並列に接続した場合
埋め込み形 ６０pH
裏面実装形 ７２pH
以上のように、コンデンサを単体で用いても、容量を増大させるため並列に接続した場合にも、チップコンデンサを内蔵することでインダクタンスを低減できる。
【０１３１】
次に、信頼性試験を行った結果について説明する。ここでは、第１実施形態のプリント配線板において、１個のチップコンデンサの静電容量の変化率を測定した。

【０１３２】
Steam試験は、蒸気に当て湿度１００％に保った。また、ＨＡＳＴ試験では、相対湿度１００％、印加電圧１．３Ｖ、温度１２１℃で１００時間放置した。ＴＳ試験では、−１２５℃で３０分、５５℃で３０分放置する試験を１０００回線り返した。
【０１３３】
上記信頼性試験において、チップコンデンサを内蔵するプリント配線板においても、既存のコンデンサ表面実装形と同等の信頼性が達成できていることが分かった。また、上述したように、ＴＳ試験において、セラミックから成るコンデンサと、樹脂からなるコア基板及び層間樹脂絶縁層の熱膨張率の違いから、内部応力が発生しても、チップコンデンサの端子とビアとの間に断線、チップコンデンサと層間樹脂絶縁層との間で剥離、層間樹脂絶縁層にクラックが発生せず、長期に渡り高い信頼性を達成できることが判明した。
【０１３４】
【発明の効果】
本発明の構成では、導体回路とコンデンサの間に、本願発明のビアが形成されているので、電源供給不足による動作の遅延をすることがなく、所望の性能を保つことができ、信頼性試験を行っても問題を引き起こさなかった。
また、該ビアにより、層間絶縁層のバイアホールを形成しても、位置ずれを引き起こしても、その許容範囲が広くなるために、電気接続性が確保される。
【図面の簡単な説明】
【図１】図１（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）、（Ｅ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図２】図２（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図３】図３（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図４】図４（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図５】図５（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図６】図６（Ａ）、（Ｂ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図７】本発明の第１実施形態に係るプリント配線板の断面図である。
【図８】本発明の第１実施形態に係るプリント配線板にＩＣチップを搭載した状態を示す断面図である。
【図９】図９（Ａ）は、図７中のビア５２の拡大図であり、図９（Ｂ）は、図９（Ａ）のＢ矢印図である。
【図１０】図１０（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１１】図１１（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１２】図１２（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１３】図１３（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１４】図１４（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１５】図１５（Ａ）、（Ｂ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１６】図１６（Ａ）、（Ｂ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１７】本発明の第２実施形態に係るプリント配線板にＩＣチップを搭載した状態を示す断面図である。
【図１８】本発明の第３実施形態に係るプリント配線板にＩＣチップを搭載した状態を示す断面図である。
【図１９】本発明の第１実施形態に係るプリント配線板のチップコンデンサの断面図である。
【図２０】本発明の第４実施形態に係るプリント配線板を示す断面図である。
【図２１】ＩＣチップへの供給電圧と時間との変化を示すグラフである。
【図２２】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第５実施形態のプリント配線板のチップコンデンサの平面図である。
【図２３】第５実施形態に係るプリント配線板のチップコンデンサの平面図である。
【図２４】第５実施形態の改変例に係るプリント配線板のチップコンデンサの平面図である。
【符号の説明】
２０ チップコンデンサ
２１ 第１端子
２２ 第２端子
３０ コア基板
３２ 凹部
３３ 凹部
３５ 凹部
３６ 樹脂層
４０ 樹脂絶縁層
５２ ビア
５３ ビア
６０ 層間樹脂絶縁層
６８ 導体回路
６９ ビア
７０ ソルダーレジスト層
７１Ｕ、７１Ｄ 開口部
７２ ニッケルめっき層
７４ 金めっき層
７６ 半田バンプ
９０ ＩＣチップ
９２ 半田パッド（ＩＣチップ側）
９４ ドータボード
９５ 半田パッド（ドータボード側）
９６ 導電性接続ピン
９７ 導電性接着剤
９８ 固定部
１６０ 層間樹脂絶縁層
１６８ 導体回路
１６９ ビア[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed circuit board on which an electronic component such as an IC chip is placed, and more particularly to a printed wiring board with a built-in capacitor.
[0002]
[Prior art]
Currently, in a printed wiring board for a package substrate, a chip capacitor is sometimes surface-mounted for the purpose of facilitating power supply to an IC chip.
[0003]
Since the reactance of the wiring from the chip capacitor to the IC chip depends on the frequency, a sufficient effect cannot be obtained even if the chip capacitor is surface-mounted as the driving frequency of the IC chip increases. For this reason, the present applicant has proposed, in Japanese Patent Application No. 11-248311, a technique of forming a recess in the core substrate and accommodating a chip capacitor in the recess. As a technique for embedding a capacitor in a substrate, JP-A-6-326472, JP-A-7-263619, JP-A-10-256429, JP-A-11-45955, JP-A-11-126978, JP-A-11- No. 31868 etc.
[0004]
Japanese Patent Application Laid-Open No. 6-326472 discloses a technique of embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, it is possible to reduce power supply noise, eliminate the need for a space for mounting a chip capacitor, and reduce the size of the insulating substrate. Japanese Patent Application Laid-Open No. 7-263619 discloses a technique for embedding a capacitor in a substrate such as ceramic or alumina. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.
[0005]
[Problems to be solved by the invention]
However, the above-mentioned Japanese Patent Laid-Open Nos. 6-326472 and 7-263619 cannot reduce the distance from the IC chip to the capacitor so much, and in the higher frequency region of the IC chip, the inductance is required as it is currently required. Could not be reduced. In particular, in multilayer build-up wiring boards made of resin, disconnection occurs between the chip capacitor terminals and vias due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and interlayer resin insulation layer. Peeling occurs between the capacitor and the interlayer resin insulation layer, and cracks occur in the interlayer resin insulation layer, and high reliability cannot be achieved over a long period of time.
[0006]
On the other hand, in the invention of Japanese Patent Application No. 11-248311, when there is a displacement in the position of the capacitor, the connection between the capacitor terminal and the via cannot be made accurately, and the power supply from the capacitor to the IC chip may not be possible. was there.
[0007]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board having a built-in capacitor and improved connection reliability, and a method for manufacturing the printed wiring board.
[Means for Solving the Problems]
[0008]
  In order to achieve the above object, the invention according to claim 1 is a printed wiring board in which a capacitor is built in a core substrate and a resin insulating layer, an interlayer resin insulating layer, and a conductor circuit are laminated thereon,
In the resin insulation layer, connected to the terminal of the capacitor, filled with plating to form a lower via with a flat surface, the interlayer resin insulation layer on the upper surface of the resin insulation layer,1'sLower layer viaMultiple connected toAn upper via that is relatively smaller than the lower via is disposed.,
An upper interlayer resin insulation layer having a plurality of vias is provided on the interlayer resin insulation layer, and each upper via is connected to a via in the upper interlayer resin insulation layer, and a lower via and each upper layer are connected. Vias and vias in the upper interlayer resin insulation layer connected to each upper via constitute a plurality of power supply linesThis is a technical feature.
[0009]
  Claim1, 2Then, a capacitor is built in the core substrate, a relatively large lower via connected to the capacitor terminal is formed on the capacitor, and a plurality of lower vias connected to one lower via are formed in the interlayer resin insulating layer on the upper surface of the core substrate. The relatively small upper layer via is disposed. Accordingly, it is possible to connect the capacitor terminal and the lower layer via corresponding to the displacement of the capacitor arrangement, and it is possible to reliably supply power from the capacitor to the IC chip. In addition, by arranging a plurality of relatively small upper layer vias, it is possible to obtain the same effect as when the inductance components are connected in parallel, so that the high frequency characteristics of the power supply line and the ground line are enhanced, power supply is insufficient, or the ground level It is possible to prevent the malfunction of the IC chip due to the fluctuation of the. Furthermore, since the wiring length can be shortened, the loop inductance can be reduced.
[0010]
It is desirable to fill the recess with resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if stress originating from the capacitor is generated, it can be relaxed by the filled resin. The resin also has an effect of reducing adhesion and migration between the capacitor and the core substrate.
[0011]
  Claim1, 2In this case, a filled via having a flat surface is used as the lower layer via. As a result, a plurality of upper layer vias can be directly connected to one lower layer via. Therefore, the connectivity between the lower layer via and the upper layer via can be improved, and the power can be reliably supplied from the capacitor to the IC chip.
[0012]
  Claim4Then, one capacitor is accommodated in a recess formed in the core substrate. Thereby, since the capacitor is arranged in the core substrate, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced.
[0013]
  Claim5Then, since a large number of capacitors can be accommodated in the recesses, the capacitors can be highly integrated.
[0014]
  Claim6, 7Then, electrical connection is made to the electrode of the chip capacitor formed with the metal film by a via made by plating. Here, the electrode of the chip capacitor is made of metallization and the surface has irregularities, but the surface is smoothed by the metal film, and a via is formed, so when forming a through hole in the resin coated on the electrode, Resin residue does not remain, and the connection reliability between the via and the electrode can be improved. Furthermore, since vias are formed by plating on the plated electrodes, the connectivity between the electrodes and vias is high, and disconnection between the electrodes and vias does not occur even when a heat cycle test is performed.
[0015]
The surface of the chip capacitor may be roughened. As a result, the adhesion between the ceramic chip capacitor and the adhesive layer made of resin and the interlayer resin insulation layer is high, and even if the heat cycle test is performed, the adhesion layer and the interlayer resin insulation layer peel off at the interface. There is no.
[0016]
  Claim8Then, resin is filled between the core substrate and the capacitor, and the thermal expansion coefficient of the resin is set to be smaller than that of the core substrate, that is, close to a capacitor made of ceramic. For this reason, in the heat cycle test, even if an internal stress occurs due to a difference in thermal expansion coefficient between the core substrate and the capacitor, cracks, peeling, and the like hardly occur in the core substrate, and high reliability can be achieved.
[0017]
  Claim9Then, in addition to the capacitor accommodated in the substrate, a capacitor is provided on the surface. Since the capacitor is accommodated in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance can be reduced, and the power can be supplied instantaneously. Since the capacitor is disposed, a large-capacity capacitor can be attached, and a large amount of power can be easily supplied to the IC chip.
[0018]
  Claim10Then, since the capacitance of the capacitor on the surface is equal to or greater than the capacitance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and the desired operation of the IC chip is ensured.
[0019]
  Claim11Then, since the inductance of the capacitor on the surface is equal to or higher than the inductance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and the desired operation of the IC chip is ensured.
[0020]
  Claim12In this case, at least a portion of the chip capacitor electrode coating layer is exposed and accommodated in the printed wiring board, and electrical connection is made to the electrode exposed from the coating layer. At this time, it is desirable that the metal exposed from the coating layer is mainly composed of Cu. This is because the connection resistance can be reduced.
[0021]
  Claim13Then, since a chip capacitor having an electrode formed inside the outer edge is used, even if conduction is made through a via hole, the external electrode can be made large, and the allowable range of alignment is widened.
[0022]
  Claim14Then, since a capacitor having electrodes formed in a matrix is used, a large chip capacitor can be easily accommodated in the core substrate. As a result, the capacitance can be increased, and the electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is hardly warped.
[0023]
  Claim15Then, a plurality of chip capacitors may be connected to the capacitor. Thereby, the capacitance can be adjusted as appropriate, and the IC chip can be operated appropriately.
[0024]
  Claim17In the method for producing a printed wiring board of (a) to (t) Comprising the steps of:
(A) forming a core substrate having a recess by forming a through hole in the resin plate and attaching the resin plate to the resin plate having the through hole;
(B) A step of accommodating a capacitor in the recess of the core substrate via an adhesive material;
(C) A step of filling a thermosetting resin between the capacitors accommodated in the recesses of the core substrate to form a resin layer;
(D) a step of aligning the terminal surface of the capacitor and the upper surface of the core substrate on the same surface;
(E) forming a resin insulating layer on the upper surface of the core substrate containing the capacitor;
(F) An interlayer connected to the terminal of the capacitor on the resin insulation layerresinForming a lower via opening relatively larger than a via between insulating layers;
(G) forming through holes for through-holes in the resin layer and the resin insulating layer on the upper surface thereof, and heat-curing;
(H) forming a copper plating film on the resin insulating layer and the through-hole wall for the through hole by electroless plating;
(I) A step of applying a photosensitive dry film on the surface of the copper plating film, placing the mask on the surface, exposing and developing, and forming a resist having a predetermined pattern;
(J) filling the non-resist forming portion with electrolytic plating, and forming a relatively large via and through-hole having a filled via structure including a copper plating film and electrolytic copper plating;
(K) The resin insulation layer40On top of the interlayer resin insulation layer60Forming a step;
(L) The interlayer resin insulation layer60Relatively smaller than lower layer viasTo the bottom viaMultiple via openingsOne by oneProviding step;
(M) The via opening and the interlayerresinInsulation layer60Forming an electroless copper plating layer on the surface of
(N) A step of applying a photosensitive dry film on the electroless copper plating layer, placing a photomask film, exposing and developing, and providing a plating resist;
(O) Filling the resist non-formed portion with electrolytic plating, and forming a plurality of vias relatively smaller than the lower via made of a copper plating film and electrolytic copper plating;
(P) forming an interlayer resin insulation layer 160 on the lower via and the interlayer resin insulation layer surface 60;
(Q) providing a via opening that connects to each of a plurality of vias relatively smaller than the lower-layer via;
(R) forming an electroless copper plating layer on the via opening and the surface of the interlayer resin insulation layer 160;
(S) A step of applying a photosensitive dry film on the electroless copper plating layer, placing a photomask film, exposing and developing, and providing a plating resist;
(T) One in which the resist non-formed portion is filled with electrolytic plating and connected to each of a plurality of vias relatively smaller than a lower via formed in the interlayer resin insulating layer 60 made of a copper plating film and electrolytic copper plating. Forming a plurality of vias in the interlayer resin insulation layer 160;
[0025]
  Claim17Then, a capacitor is built in the core substrate, a relatively large lower via connected to the capacitor terminal is formed on the capacitor, and a plurality of lower vias connected to one lower via are formed in the interlayer resin insulating layer on the upper surface of the core substrate. The relatively small upper layer via is disposed. Accordingly, it is possible to connect the capacitor terminal and the lower layer via corresponding to the displacement of the capacitor arrangement, and it is possible to reliably supply power from the capacitor to the IC chip. In addition, by arranging a plurality of relatively small upper layer vias, it is possible to obtain the same effect as when the inductance components are connected in parallel, so that the high frequency characteristics of the power supply line and the ground line are enhanced, power supply is insufficient, or the ground level It is possible to prevent the malfunction of the IC chip due to the fluctuation of the. Furthermore, since the wiring length can be shortened, the loop inductance can be reduced.
[0026]
  Claim20Then, one capacitor is accommodated in a recess formed in the core substrate. As a result, since the capacitor is arranged in the core substrate, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced.
[0027]
  Claim21Then, since a large number of capacitors can be accommodated in the recesses, the capacitors can be highly integrated.
[0028]
  Claim17Then, a through hole is formed in a resin material containing a resin as a core material, and the resin material is attached to the resin material in which the through hole is formed to form a core substrate having a recess. As a result, a core substrate having a concave portion with a flat bottom can be formed.
[0029]
  Claim22, Claims23In this case, a filled via having a flat surface is used as the lower layer via. As a result, a plurality of upper layer vias can be directly connected to one lower layer via. Therefore, the connectivity between the lower layer via and the upper layer via can be improved, and the power can be reliably supplied from the capacitor to the IC chip.
[0030]
  Claim24In this invention, the heights of the upper surfaces of the capacitors are made uniform by applying pressure to or tapping the upper surfaces of the plurality of capacitors in the recesses. Thereby, when the capacitors are disposed in the recesses, the heights can be made uniform even if the sizes of the plurality of capacitors vary, and the core substrate can be made smooth. Therefore, the smoothness of the core substrate is not impaired, and the upper interlayer resin insulation layer and the conductor circuit can be appropriately formed, so that the defective product occurrence rate of the printed wiring board can be reduced.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board 10, and FIG. 8 shows a state in which the IC chip 90 is mounted on the printed wiring board 10 shown in FIG. 9A is an enlarged view of the via 52 in FIG. 7, and FIG. 9B shows a state in which a plurality of vias 69 are arranged in the via 52 in FIG. 9A. It is a schematic diagram which shows the state seen from.
[0032]
As shown in FIG. 7, the printed wiring board 10 includes a core substrate 30 that houses a plurality of chip capacitors 20, and build-up wiring layers 80A and 80B. A relatively large via 52 is connected to the terminals 21 and 22 of the plurality of chip capacitors 20 accommodated in the core substrate 30. The build-up wiring layers 80A and 80B are composed of interlayer resin insulation layers 60 and 160. Conductor circuit 68 and relatively small via 69 are formed in interlayer resin insulation layer 60, and conductor circuit 168 and relatively small via 169 are formed in interlayer resin insulation layer 160. A solder resist layer 70 is disposed on the interlayer resin insulating layer 160.
[0033]
As shown in FIG. 19A, the chip capacitor 20 includes a first terminal 21, a second terminal 22, and a dielectric 23 sandwiched between the first and second terminals. A plurality of first conductive films 24 connected to the terminal 21 side and second conductive films 25 connected to the second terminal 22 side are arranged to face each other.
[0034]
As shown in FIG. 8, solder bumps 76U for connection to the pads 92 of the IC chip 90 are formed in the vias 169 of the upper buildup wiring layer 80A. On the other hand, a solder bump 76D for connection to the pad 94 of the daughter board 95 is formed in the via 169 of the lower buildup wiring layer 80B.
[0035]
As the core substrate, one made of resin was used. For example, a resin material used in a general printed wiring board such as a glass epoxy resin-impregnated base material or a phenol resin-impregnated base material can be used. However, a substrate such as ceramic or AIN cannot be used as the core substrate. This is because the substrate has poor outer formability and cannot accommodate a capacitor, and even if it is filled with a resin, voids are generated.
[0036]
Further, since a plurality of chip capacitors 20 are accommodated in the recesses 32 formed in the core substrate 30, the chip capacitors 20 can be arranged at a high density. Further, since the plurality of chip capacitors 20 are accommodated in the recess 32, the height of the chip capacitors 20 can be made uniform. For this reason, since the resin layer 40 on the chip capacitor 20 can be made to have a uniform thickness, the via 52 can be appropriately formed. In addition, since the distance between the IC chip 90 and the chip capacitor 20 is shortened, the loop inductance can be reduced.
[0037]
Further, as shown in FIG. 7 and FIG. 9A which is an enlarged view of the via 52 of FIG. 7, a plurality of vias 69 of the upper buildup wiring layer 80A are connected to one via 52. As shown in FIG. 9B, the large via 52 has an inner diameter of 125 μm and a land diameter of 165 μm, and the small via 69 has an inner diameter of 25 μm and a land diameter of 65 μm. On the other hand, the chip capacitor 20 is formed in a rectangular shape, and the first terminal 21 and the second terminal 21 are also formed in a rectangular shape with a side of 250 μm. For this reason, even if the arrangement position of the chip capacitor 20 is shifted by several tens of μm, the first terminal 21 and the second terminal 22 of the chip capacitor 20 and the via 52 can be connected. It is possible to reliably supply power to the chip 90. In addition, since a plurality of vias 69 are provided, the same effect as when the inductance components are connected in parallel can be obtained. Therefore, the high frequency characteristics of the power supply line and the ground line are enhanced, and the IC is caused by insufficient power supply or ground level fluctuation. It is possible to prevent malfunction of the chip. Furthermore, since the wiring length from the IC chip to the chip capacitor 20 can be shortened, the loop inductance can be reduced.
[0038]
As shown in FIG. 7, the via 52 is formed as a filled via filled with plating and having a flat surface. As a result, a plurality of vias 69 can be directly connected on the via 52. Therefore, the connectivity between the via 52 and the via 69 can be improved, and the power supply from the chip capacitor 20 to the IC chip 90 can be reliably performed. In the present embodiment, the filled via is formed by plating filling, but instead, as the via 52, a filled via having a metal film disposed on the surface after filling the resin inside may be used.
[0039]
The thermal expansion coefficients of the resin filler 36 and the adhesive material 34 under the chip capacitor 20 are set to be smaller than that of the core substrate 30 and the resin insulating layer 40, that is, close to the chip capacitor 20 made of ceramic. For this reason, in the heat cycle test, even if an internal stress occurs due to a difference in thermal expansion coefficient between the core substrate 30 and the resin insulating layer 40 and the chip capacitor 20, the core substrate 30 and the resin insulating layer 40 are cracked, peeled off, etc. It is difficult to occur and high reliability can be achieved.
[0040]
Further, since the through hole 46 is formed in the resin layer 36 between the chip capacitors 20, the signal line does not pass through the ceramic chip capacitor 20, so that reflection due to impedance discontinuity due to the high dielectric and passage through the high dielectric Propagation delay does not occur.
[0041]
In the chip capacitor 20, as shown in FIG. 19A, the surface of the metal layer 26 that constitutes the first electrode 21 and the second electrode 22 is covered with a copper plating film 29. The coating of the plating film is formed by plating such as electrolytic plating or electroless plating. Then, as shown in FIG. 7, the first and second electrodes 21 and 22 coated with the copper plating film 29 are electrically connected by vias 52 made of copper plating. Here, the electrodes 21 and 22 of the chip capacitor are made of metallization and have irregularities on the surface. For this reason, if the metal layer 26 is used in a state where the metal layer 26 is exposed, the resin may remain on the unevenness in the step of forming the opening 42 in the resin insulating layer 40 described later. At this time, the resin residue may cause a connection failure between the first and second electrodes 21 and 22 and the via 52. On the other hand, in this embodiment, the surfaces of the first and second electrodes 21 and 22 are smoothed by the copper plating film 29, and the opening 42 is formed in the resin insulating layer 40 covered on the electrodes. The resin residue does not remain, and the connection reliability with the electrodes 21 and 22 when the via 52 is formed can be improved.
[0042]
Furthermore, since the via 52 is formed by plating on the electrodes 21 and 22 on which the copper plating film 29 is formed, the connectivity between the electrodes 21 and 22 and the via 52 is high, and even if a heat cycle test is performed, the electrode 21 , 22 and the via 52 are not disconnected.
[0043]
The copper plating film 29 is provided after the nickel / tin layer coated on the surface of the metal layer 26 at the manufacturing stage of the chip capacitor is peeled off at the mounting stage on the printed wiring board. Alternatively, the copper plating film 29 can be directly coated on the metal layer 26 at the manufacturing stage of the chip capacitor 20. That is, in this embodiment, after providing an opening to the copper plating film 29 of the electrode with a laser, desmear processing or the like is performed, and the via is formed by copper plating. Therefore, even if an oxide film is formed on the surface of the copper plating film 29, the oxide film can be removed by the laser and desmear treatment, so that a proper connection can be established.
[0044]
Further, as shown in FIG. 19B, the first electrode 21 and the second electrode 22 of the chip capacitor 20 are exposed from the covering layer 28 of the first electrode 21 and accommodated in the printed wiring board and exposed from the covering layer 28. Electrical connection can also be made to the electrode 21 and the second electrode 22. At this time, it is desirable that the metal exposed from the coating layer 28 is mainly composed of Cu. This is because the connection resistance can be reduced.
[0045]
Furthermore, a roughened layer 23 a may be provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. Thereby, the adhesiveness between the chip capacitor 20 made of ceramic and the resin insulating layer 40 made of resin is high, and even if the heat cycle test is performed, the resin insulating layer 40 does not peel off at the interface. The roughened layer 23a can be formed by polishing the surface of the chip capacitor 20 after firing, or by performing a roughening treatment before firing. In this embodiment, the surface of the capacitor is roughened to improve the adhesion with the resin. Alternatively, a silane coupling treatment can be applied to the surface of the capacitor.
[0046]
Next, a method for manufacturing the printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.
[0047]
(1) First, a core substrate 30 made of an insulating resin substrate is used as a starting material (see FIG. 1A). Next, a concave portion 32 for disposing the capacitor is formed on one surface of the core substrate 30 by counterboring or providing a through hole in an insulating resin and pressing and bonding (see FIG. 1B). At this time, the concave portion 32 is formed wider and larger than an area where a plurality of capacitors can be disposed. As a result, a plurality of capacitors can be reliably disposed on the core substrate 30.
[0048]
(2) Thereafter, the adhesive material 34 is applied to the recess 32 using a printing machine (see FIG. 1C). Alternatively, the adhesive material can be applied to the concave portion by a method such as potting, die bonding, or attaching an adhesive sheet. As the adhesive material 34, a material having a thermal expansion coefficient smaller than that of the core substrate is used. Next, a plurality of chip capacitors 20 made of ceramic are bonded to the recesses 32 via an adhesive material 34 (see FIG. 1D). Here, by arranging the plurality of chip capacitors 20 in the recesses 32 having a smooth bottom, the heights of the plurality of chip capacitors 20 are aligned. Therefore, the resin insulating layer 40 can be formed on the core substrate 30 with a uniform thickness and the vias 52 can be appropriately formed in the process described later.
[0049]
Then, the top surfaces of the chip capacitors 20 are pushed or hit so that the top surfaces of the plurality of chip capacitors 20 have the same height (see FIG. 1E). With this process, when the plurality of chip capacitors 20 are disposed in the recesses 32, the heights can be completely aligned even if the sizes of the plurality of chip capacitors 20 vary. Can be smoothed.
[0050]
(3) Thereafter, a thermosetting resin is filled between the chip capacitors 20 in the recess 32, and the resin layer 36 is formed by heat curing (see FIG. 2A). At this time, epoxy, phenol, polyimide, and triazine are preferable as the thermosetting resin. Thereby, the chip capacitor 20 in the recess 32 can be fixed. The resin layer 36 has a thermal expansion coefficient smaller than that of the core substrate.
[0051]
In addition, a resin such as a thermoplastic resin may be used. Further, a filler may be impregnated in order to match the thermal expansion coefficient in the resin. Examples of the filler include an inorganic filler, a ceramic filler, and a metal filler.
[0052]
(4) Further, an epoxy resin or a polyolefin resin, which will be described later, is applied from above using a printing machine to form a resin insulation layer 40 (see FIG. 2B). In addition, you may affix a resin film instead of apply | coating resin.
[0053]
In addition, one or more resins such as a thermosetting resin, a thermoplastic resin, a photosensitive resin thermosetting resin / thermoplastic resin composite, and a photosensitive resin / thermoplastic resin composite can be used. . You may make them into 2 layer structure.
[0054]
(5) Next, a relatively large via opening 42 is formed in the resin insulating layer 40 by a laser (see FIG. 2C). Thereafter, desmear processing is performed. An exposure / development process can also be used instead of the laser. Then, through holes 44 for through holes are formed in the resin layer 36 with a drill or a laser, and are cured by heating (see FIG. 2D). In some cases, a roughening treatment with an acid, an oxidizing agent or a chemical solution, or a roughening treatment with a plasma treatment may be performed. Thereby, the adhesion of the roughened layer is ensured.
[0055]
(6) Thereafter, a copper plating film 46 is formed on the surface of the resin insulating layer 40 by electroless copper plating (see FIG. 3A). Instead of electroless plating, Ni / Cu metal layer may be formed by performing sputtering using Ni and Cu as targets. In some cases, the electroless plating film may be formed after the sputtering.
[0056]
(7) Next, a photosensitive dry film is affixed to the surface of the copper plating film 46, a mask is placed thereon, exposure and development are performed, and a resist 48 having a predetermined pattern is formed. Then, the core substrate 30 is immersed in the electrolytic plating solution, and a current is passed through the copper plating film 46, so that the electrolytic plating 50 is filled in the portions where the resist 48 is not formed (see FIG. 3B).
[0057]
(8) Next, after the plating resist 48 is peeled and removed with 5% NaOH, the copper plating film 46 under the plating resist 48 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. A relatively large via 52 and a through hole 54 having a filled via structure made of electrolytic copper plating 50 are formed. The large via diameter is desirably in the range of 100 to 600 μm. In particular, it is desirable that it is 125-350 micrometers. In this case, it was formed at 165 μm. The through hole was formed at 250 μm. Then, an etching solution is sprayed onto both surfaces of the substrate 30 to etch the surface of the via 52 and the land surface of the through hole 54, thereby forming a roughened surface 52α on the entire surface of the via 52 and the through hole 54. (See FIG. 3C).
[0058]
(9) Thereafter, the through hole 54 is filled with a resin filler 56 mainly composed of an epoxy resin and dried (see FIG. 3D).
[0059]
(10) A pressure of 5 kg / cm while heating a thermosetting epoxy resin sheet having a thickness of 50 μm to a temperature of 50 to 150 ° C. on both surfaces of the substrate 30 that has undergone the above-described steps.²And an interlayer resin insulating layer 60 made of an epoxy resin is provided (see FIG. 4A). The degree of vacuum at the time of vacuum bonding is 10 mmHg. A cycloolefin resin can be used in place of the epoxy resin.
[0060]
(11) Next, CO²A relatively small via opening 61 of 65 μm is provided in the interlayer resin insulating layer 60 by a gas laser (see FIG. 4B). The relatively small via diameter is preferably in the range of 25-100 μm. Thereafter, desmear treatment is performed using oxygen plasma.
[0061]
(12) Next, plasma processing is performed using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. to roughen the surface of the interlayer resin insulation layer 60 to form a roughened surface 60α (see FIG. 4C). . At this time, argon gas is used as the inert gas, and plasma treatment is performed for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, and temperature 70 ° C. You may roughen by an acid or an oxidizing agent. The roughened layer is preferably 0.1 to 5 μm.
[0062]
(13) Next, using the same apparatus, after replacing the argon gas inside, sputtering with Ni and Cu as targets was performed under conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, time 5 minutes, A Ni / Cu metal layer 62 is formed on the surface of the interlayer resin insulation layer 60. At this time, the thickness of the formed Ni / Cu metal layer 62 is 0.2 μm (see FIG. 4D). A plating film such as electroless plating or a plating film may be formed on the sputter.
[0063]
(14) A commercially available photosensitive dry film is pasted on both sides of the substrate 30 after the above treatment, and a photomask film is placed thereon, and 100 mJ / cm.²After the exposure, a development process is performed with 0.8% sodium carbonate to provide a plating resist 64 having a thickness of 15 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 66 having a thickness of 15 μm (see FIG. 5A). The additive in the electrolytic plating aqueous solution is Kaparaside HL manufactured by Atotech Japan.
[0064]

[0065]
(15) After stripping and removing the plating resist 64 with 5% NaOH, the Ni / Cu metal layer 62 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide. A plurality of relatively small vias 69 connected to the conductor circuit 68 and the via 52 made of the metal layer 62 and the electrolytic plating film 66 are formed (see FIG. 5B). In the present embodiment, the via 52 has a filled via structure, whereby a plurality of vias 69 can be directly connected to the via 52.
[0066]
(16) Next, the substrate is washed with water and dried, and then the surface of the conductor circuit 68 is etched by spraying an etching solution onto both surfaces of the substrate, thereby roughening the surface of the conductor circuit 68. (See FIG. 5C). As an etching solution, a mixture of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride and 78 parts by weight of ion-exchanged water is used.
[0067]
(17) Next, by repeating the above steps (10) to (16), an upper interlayer resin insulation layer 160 and a conductor circuit 168 (including via 169) are formed (see FIG. 5D). .
[0068]
(18) Next, the photosensitizing property obtained by acrylating 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 15 parts by weight of imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd.) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) which is a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.7 A weight part is put into a container, and a mixed composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator and Michler's ketone as a photosensitizer for the mixed composition. (Kanto Chemical Co., Ltd.) 0.2 part by weight is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured with a B type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3.
[0069]
(19) Next, the solder resist composition is applied to both surfaces of the substrate 30 at a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the solder resist resist is applied. A photomask having a thickness of 5 mm on which the pattern of the opening is drawn is brought into close contact with the solder resist layer 70 and 1000 mJ / cm.²Are exposed to UV light and developed with DMTG solution to form openings 71U and 71D (see FIG. 6A). A commercially available solder resist such as LPSR may also be used.
[0070]
(20) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed is made of nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphate (2.8 × 10 6)^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer 72 having a thickness of 5 μm is formed in the openings 71U and 71D by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1mol / l) is immersed in an electroless plating solution at 80 ° C. for 7.5 minutes to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72 (see FIG. 6B). ).
[0071]
(21) Thereafter, solder bumps (solder bodies) 76U and 76D are formed by printing solder paste on the openings 71U and 71D of the solder resist layer 70 and reflowing at 200 ° C. Thereby, the printed wiring board 10 having the solder bumps 76U and 76D can be obtained (see FIG. 7).
[0072]
Next, placement of the IC chip on the printed wiring board 10 completed in the above-described process and attachment to the daughter board will be described with reference to FIG. The IC chip 90 is mounted so that the solder pads 92 of the IC chip 90 correspond to the solder bumps 76U of the completed printed wiring board 10, and the IC chip 90 is attached by performing reflow. Similarly, the printed wiring board 10 is attached to the daughter board 95 by reflowing so that the pads 94 of the daughter board 95 correspond to the solder bumps 76 </ b> D of the printed wiring board 10.
[0073]
The resin film described above contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.
[0074]
The resin film used in the production method of the present invention is a resin film in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are dispersed in a resin that is hardly soluble in an acid or oxidizing agent (hereinafter referred to as a poorly soluble resin). It is.
As used herein, the terms “poorly soluble” and “soluble” refer to those having a relatively fast dissolution rate as “soluble” for convenience when immersed in a solution of the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as “slightly soluble” for convenience.
[0075]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
[0076]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0077]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present invention, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0078]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluorine resin, and the like, and may be composed of one of these resins. And it may consist of a mixture of two or more resins.
[0079]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, various modified polybutadiene rubbers such as (meth) acrylonitrile modification, (meth) acrylonitrile-butadiene rubber containing a carboxyl group, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.
[0080]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0081]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate and the like. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0082]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0083]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted between the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.
[0084]
The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via opening can be formed in the interlayer resin insulation layer using exposure and development processes.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.
[0085]
Specific examples of the hardly soluble resin include an epoxy resin, a phenol resin, a phenoxy resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more.
Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.
[0086]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0087]
In the resin film used in the present invention, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface having unevenness with a uniform roughness can be formed, and even when a via or a through hole is formed in a resin film, adhesion of a metal layer of a conductor circuit formed thereon can be secured. Because. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. As a result, since the portion other than the surface layer portion of the resin film is not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is reliably maintained.
[0088]
In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent In addition, the resin film is melted to the deep part of the resin film, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.
[0089]
The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0090]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0091]
Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By containing these fillers, it is possible to improve the performance of the printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0092]
Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more.
[0093]
The printed wiring board 110 according to the second embodiment of the present invention will be described with reference to FIG. In 1st Embodiment mentioned above, the case where BGA was arrange | positioned demonstrated. The second embodiment is substantially the same as the first embodiment, but is configured in a PGA system in which connection is established via conductive connection pins 96 as shown in FIG.
[0094]
Next, a method for manufacturing the printed wiring board described above with reference to FIG. 17 will be described with reference to FIGS.
[0095]
(1) First, a through hole 33a for accommodating a chip capacitor is formed in a laminate 30α obtained by laminating four prepregs 31 impregnated with an epoxy resin. On the other hand, a laminated plate 30β obtained by laminating two prepregs 31 is prepared (see FIG. 10A). Here, as the prepreg 31, in addition to epoxy, a material containing a reinforcing material such as BT, phenol resin, or glass cloth can be used.
[0096]
(2) Next, the laminated board 30α and the laminated board 30β are pressure-bonded and heated and cured to form the core substrate 30 having the recesses 33 that can accommodate the plurality of chip capacitors 20 (FIG. 10 (B)).
[0097]
(3) Then, an adhesive material 34 is applied to the capacitor placement position of the recess 33 using a potting (dispenser) (see FIG. 10C). Alternatively, the adhesive material can be applied to the recesses by a method such as printing, die bonding, or attaching an adhesive sheet. Thereafter, the plurality of chip capacitors 20 made of ceramic are accommodated in the recesses 33 through the adhesive material 34 (see FIG. 10D).
[0098]
(4) After that, a thermosetting resin is filled between the chip capacitors 20 in the recess 33, and the resin layer 36 is formed by heat curing (see FIG. 11A). At this time, epoxy, phenol, polyimide, and triazine are preferable as the thermosetting resin.
Thereby, the chip capacitor 20 in the recess 33 can be fixed.
[0099]
(5) Further, the above-described epoxy or polyolefin resin is applied using a printing machine to form the resin insulating layer 40 (see FIG. 11B). In addition, you may affix a resin film instead of apply | coating resin.
[0100]
(6) Next, a relatively large via opening 42 is formed in the resin insulating layer 40 by exposure / development processing or laser (see FIG. 11C). The large via diameter is desirably in the range of 100 to 600 μm. In particular, it is desirable that it is 125-350 micrometers. In this case, it was formed at 165 μm. Then, through holes 44 having a diameter of 250 μm are formed in the resin layer 36 with a drill or a laser, and are cured by heating (see FIG. 11D).
[0101]
(7) Then, after applying a palladium catalyst to the substrate 30, the core substrate is immersed in the electroless plating solution to deposit the electroless plating film 45 uniformly (see FIG. 12A).
Thereafter, the inside of the opening 42 in which the electroless plating film 45 is formed is filled with a resin filler and dried. Thereby, the resin layer 47 is formed inside the opening 42 (see FIG. 12B).
[0102]
(8) Thereafter, a photosensitive dry film is attached to the surface of the electroless plating film 45, a mask is placed, and exposure / development processing is performed to form a resist 48 having a predetermined pattern. Then, the core substrate 30 is immersed in an electroless plating solution to form a lid plating 51 made of an electroless plating film (see FIG. 12C).
[0103]
(9) After the above process, the resist 48 is peeled off with 5% NaOH, and then the electroless plating film 45 under the resist 48 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. Large vias 53 and through holes 54 are formed (see FIG. 12D). By making the via 53 have a filled via structure, a plurality of vias 69 can be directly connected to one via 53 in a process described later.
[0104]
(10) Then, the substrate 30 is washed with water, acid degreased, soft-etched, and then an etching solution is sprayed on both surfaces of the substrate 30 to spray the surface of the via 53, the land surface of the through hole 54, and the inner wall. Etching is performed to form a roughened surface 53α on the entire surface of the via 53 and the through hole 54 (see FIG. 13A). As an etching solution, an etching solution (MEC Etch Bond, manufactured by MEC) comprising 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride is used.
[0105]
(11) Next, 100 parts by weight of a bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310, YL983U), the average particle size of which the surface is coated with a silane coupling agent is 1.6 μm, SiO with a diameter of 15 μm or less₂ 170 parts by weight of spherical particles (manufactured by Adtech, CRS 1101-CE) and 1.5 parts by weight of a leveling agent (Perenol S4, manufactured by San Nopco) are placed in a container and mixed by stirring. A resin filler 62 of 49 Pa · s is prepared. As the curing agent, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) was used.
Thereafter, the resin filler 56 is filled into the through hole 54 and dried (see FIG. 13B).
[0106]
(12) Next, 30 parts by weight of bisphenol A type epoxy resin (epoxy equivalent 469, Epicoat 1001 manufactured by Yuka Shell Epoxy), cresol novolak type epoxy resin (epoxy equivalent 215, Epicron N-673 manufactured by Dainippon Ink & Chemicals, Inc.) 40 parts by weight, 30 parts by weight of triazine structure-containing phenol novolak resin (phenolic hydroxyl group equivalent 120, Phenolite KA-7052 made by Dainippon Ink & Chemicals, Inc.) to 20 parts by weight of ethyl diglycol acetate and 20 parts by weight of solvent naphtha Then, it was dissolved by heating, 15 parts by weight of terminal epoxidized polybutadiene rubber (Denalex R-45EPT manufactured by Nagase Kasei Kogyo Co., Ltd.) and 1.5 parts by weight of pulverized 2-phenyl-4,5-bis (hydroxymethyl) imidazole 2 parts by weight of finely pulverized silica It was added 0.5 part by weight of silicon antifoaming agent to prepare an epoxy resin composition.
The obtained epoxy resin composition was applied on a PET film having a thickness of 38 μm using a roll coater so that the thickness after drying was 50 μm, and then dried at 80 to 120 ° C. for 10 minutes, whereby an interlayer resin was obtained. A resin film for an insulating layer is prepared.
[0107]
(13) An interlayer resin insulation layer resin film slightly larger than the substrate 30 produced in (12) is placed on the substrate 30 on both sides of the substrate, and the pressure is 4 kgf / cm.² After the temporary pressure bonding and cutting under the conditions of a temperature of 80 ° C. and a pressure bonding time of 10 seconds, the interlayer resin insulating layer 60 is formed by further using a vacuum laminator device by the following method (FIG. 13C). reference). That is, the resin film for the interlayer resin insulation layer is placed on the substrate 30 with a vacuum degree of 0.5 Torr and a pressure of 4 kgf / cm.² The final pressure bonding is performed under the conditions of a temperature of 80 ° C. and a pressure bonding time of 60 seconds, and then heat-cured at 170 ° C. for 30 minutes.
[0108]
(14) Next, through the mask 57 in which the through-hole 57a having a thickness of 1.2 mm is formed on the interlayer resin insulating layer 60, the CO₂ A relatively small via opening 61 of 65 μm is formed in the interlayer resin insulating layer 60 with a gas laser (see FIG. 13D). The relatively small via diameter is preferably in the range of 25-100 μm.
[0109]
(15) The substrate 30 having the via openings 61 is immersed in an 80 ° C. solution containing 60 g / l permanganic acid for 10 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer 60. As a result, the surface of the interlayer resin insulation layer 60 including the inner wall of the via opening 61 is made roughened surface 60α (see FIG. 14A). You may roughen by an acid or an oxidizing agent. The roughened layer is preferably 0.1 to 5 μm.
[0110]
(16) Next, the substrate 30 after the above treatment is immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and then washed with water. Furthermore, a catalyst is attached to the surface of the interlayer resin insulation layer 60 and the inner wall surface of the via opening 61 by applying a palladium catalyst to the surface of the substrate 30 that has been roughened (roughening depth: 3 μm). .
[0111]
(17) Next, the substrate 30 is immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plating film 63 having a thickness of 0.6 to 3.0 μm over the entire roughened surface 60α ( (See FIG. 14B).
[Electroless plating aqueous solution]
NiSO_Four                   0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 40 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at 35 ° C liquid temperature
[0112]
(18) A commercially available photosensitive dry film is affixed to the electroless copper plating film 63, a mask is placed, and 100 mJ / cm² And a plating resist 64 having a thickness of 30 μm is provided by developing with a 0.8% aqueous sodium carbonate solution. Next, the substrate 30 is washed with 50 ° C. water for degreasing, washed with 25 ° C. water, and further washed with sulfuric acid, and then subjected to electrolytic plating under the following conditions, and an electrolytic copper plating film 66 having a thickness of 20 μm. (See FIG. 14C).
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside HL)
[Electrolytic plating conditions]
Current density 1 A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0113]
(19) After the plating resist 64 is peeled and removed with 5% NaOH, the electroless copper plating film 63 under the plating resist 64 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and electroless copper plating is performed. A conductor circuit 68 having a thickness of 18 μm and a relatively small via 69 formed of the film 63 and the electrolytic copper plating film 66 are formed (see FIG. 14D). Then, the process similar to (10) is performed and the roughening surface 68 (alpha) is formed with the etching liquid containing a cupric complex and an organic acid (refer FIG. 15 (A)).
[0114]
(20) Subsequently, by repeating the steps (13) to (19), an upper interlayer resin insulation layer 160, a conductor circuit 168 and a via 169 are formed (see FIG. 15B).
[0115]
(21) Next, a photosensitizing agent obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 15 parts by weight of imidazole curing agent (manufactured by Shikoku Chemicals) , Trade name: 2E4MZ-CN) 1.6 parts by weight, bifunctional acrylic monomer as a photosensitive monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604), 4.5 parts by weight, also polyacrylic monomer (manufactured by Kyoei Chemical Co., Ltd.) , Trade name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0 71 parts by weight is placed in a container, and the mixture composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator for this mixture composition, and as a photosensitizer 0.2 parts by weight of Michler's ketone (manufactured by Kanto Chemical Co., Inc.) is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured with a B type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3.
[0116]
(22) Next, the solder resist composition prepared in (21) is applied to both surfaces of the multilayer wiring board to a thickness of 20 μm. Then, after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a photomask having a thickness of 5 mm on which the pattern of the opening of the solder resist was drawn was brought into close contact with the solder resist composition and 1000 mJ / cm² Are exposed to UV light and developed with DMTG solution to form openings 71U and 71D.
Further, the solder resist composition is cured by heating at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours, and has openings 71U and 71D. Then, a 20 μm thick solder resist layer 70 is formed (see FIG. 16A). A commercially available solder resist composition can also be used as the solder resist composition.
[0117]
(23) Next, the substrate on which the solder resist layer 70 is formed is nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphite (2.8 × 10^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer 72 having a thickness of 5 μm is formed in the openings 71U and 71D by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1The gold plating layer 74 having a thickness of 0.03 μm is formed on the nickel plating layer 72 by immersing in an electroless gold plating solution containing (mol / l) at 80 ° C. for 7.5 minutes (FIG. 16B). )reference).
[0118]
(24) Thereafter, a solder paste containing tin-lead is printed in the opening 71U of the solder resist layer 70 on the surface on which the IC chip of the substrate is placed. Further, a solder paste is printed as the conductive adhesive 97 in the opening 71D on the other surface. Next, the conductive connection pin 96 is attached to and supported by an appropriate pin holding device, and the fixing portion 98 of the conductive connection pin 96 is brought into contact with the conductive adhesive 97 in the opening 71D. Then, reflow is performed to fix the conductive connection pin 96 to the conductive adhesive 97. As a method for attaching the conductive connection pin 96, a conductive adhesive 97 formed in a ball shape or the like is put into the opening 71D, or the conductive adhesive 97 is joined to the fixing portion 98 to conduct the conductive. May be attached and then reflowed.
[0119]
Thereafter, the IC chip 90 is mounted so that the solder pads 92 of the IC chip 90 correspond to the solder bumps 76 on the opening 71U side of the printed wiring board 110, and the IC chip 90 is attached by performing reflow (FIG. 17).
[0120]
Next, a printed wiring board according to the third embodiment of the present invention will be described with reference to FIG. The printed wiring board 210 of the third embodiment is almost the same as that of the first embodiment described above. However, in the printed wiring board 210 of the third embodiment, one chip capacitor 20 is accommodated in the recess 35 formed in the core substrate 30. Since the chip capacitor 20 is disposed in the core substrate 30, the distance between the IC chip 90 and the chip capacitor 20 is shortened, and the loop inductance can be reduced.
[0121]
Next, a printed wiring board according to the fourth embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, only the chip capacitor 20 accommodated in the core substrate 30 is provided, but in the fourth embodiment, a large-capacity chip capacitor 98 is mounted on the front surface and the back surface.
[0122]
An IC chip consumes a large amount of power instantaneously and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in the modified example, a chip capacitor 20 for power supply and a chip capacitor 98 are provided on the printed wiring board. The effect of this chip capacitor will be described with reference to FIG.
[0123]
In FIG. 21, the vertical axis represents voltage supplied to the IC chip, and the horizontal axis represents time.
Here, an alternate long and two short dashes line C indicates a voltage fluctuation of a printed wiring board that does not include a power supply capacitor. When the power supply capacitor is not provided, the voltage is greatly attenuated. A broken line A indicates voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. The voltage does not drop much as compared with the two-dot chain line C, but the loop length becomes long, so the rate-determining power supply cannot be sufficiently performed. That is, the voltage drops at the start of power supply. A two-dot chain line B indicates a voltage drop of the printed wiring board containing the chip capacitor described above with reference to FIG. Although the loop length can be shortened, the voltage fluctuates because a large-capacity chip capacitor cannot be accommodated in the core substrate 30. Here, the solid line E shows the voltage fluctuation of the printed wiring board according to the fourth embodiment in which the chip capacitor 20 in the core substrate described above with reference to FIG. 20 and the large-capacity chip capacitor 98 are mounted on the surface. Yes. By providing the chip capacitor 20 in the vicinity of the IC chip and the chip capacitor 98 having a large capacity (and relatively large inductance), voltage fluctuation is minimized.
[0124]
Subsequently, the configuration of the printed wiring board according to the fifth embodiment of the present invention will be described with reference to FIG.
The configuration of the printed wiring board of the fifth embodiment is substantially the same as that of the first embodiment described above. However, the chip capacitor 20 accommodated in the core substrate 30 is different. FIG. 22 is a plan view of the chip capacitor. FIG. 22A shows a chip capacitor before cutting for multi-piece cutting, and a one-dot chain line in the drawing indicates a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are disposed on the side edge of the chip capacitor as shown in the plan view of FIG. FIG. 22C shows the chip capacitor before cutting for multi-piece fabrication according to the fifth embodiment, and the alternate long and short dash line in the drawing indicates the cutting line. In the printed wiring board of the fifth embodiment, the first electrode 21 and the second electrode 22 are disposed inside the side edge of the chip capacitor as shown in the plan view of FIG.
[0125]
In the printed wiring board of the fifth embodiment, since the chip capacitor 20 having electrodes formed inside the outer edge is used, a chip capacitor having a large capacity can be used.
Next, a printed wiring board according to a first modification of the fifth embodiment will be described with reference to FIG.
FIG. 23 is a plan view of the chip capacitor 20 accommodated in the core substrate of the printed wiring board according to the first modification. In the first embodiment described above, a plurality of small-capacity chip capacitors are accommodated in the core substrate. However, in the first modification, a large-capacity large-sized chip capacitor 20 is accommodated in the core substrate. Here, the chip capacitor 20 includes a first electrode 21, a second electrode 22, a dielectric 23, a first conductive film 24 connected to the first electrode 21, and a second electrode connected to the second electrode 22 side. The conductive film 25 and the connection electrodes 27 on the upper and lower surfaces of the chip capacitor not connected to the first conductive film 24 and the second conductive film 25 are formed. The IC chip side and the daughter board side are connected via this electrode 27.
[0126]
Since the large-sized chip capacitor 20 is used in the printed wiring board of the first modified example, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated.
[0127]
A printed wiring board according to a second modification will be described with reference to FIG. FIG. 24A shows a chip capacitor before cutting for multi-piece cutting, in which a one-dot chain line shows a normal cutting line, and FIG. 24B shows a plan view of the chip capacitor. . As shown in FIG. 24B, in the second modified example, a plurality of chip capacitors (three in the example in the figure) are used in a large format.
[0128]
In the second modified example, since a large chip capacitor 20 is used, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated.
[0129]
In the fifth embodiment described above, the chip capacitor is built in the printed wiring board, but it is also possible to use a plate-like capacitor in which a conductive film is provided on a ceramic plate instead of the chip capacitor.
[0130]
Here, with respect to the printed wiring board of the first embodiment, values obtained by measuring the inductance of the chip capacitor 20 embedded in the core substrate and the inductance of the chip capacitor mounted on the back surface (surface on the daughter board side) of the printed wiring board are as follows. It is shown below.
In the case of a single capacitor
Embedded type 137pH
Back mounting type 287pH
When 8 capacitors are connected in parallel
Embedded type 60pH
Back mounting type 72pH
As described above, even when the capacitor is used alone, the inductance can be reduced by incorporating the chip capacitor even when they are connected in parallel to increase the capacitance.
[0131]
Next, the results of the reliability test will be described. Here, in the printed wiring board of the first embodiment, the change rate of the capacitance of one chip capacitor was measured.

[0132]
The steam test was kept at 100% humidity by exposure to steam. In the HAST test, the sample was left for 100 hours at a relative humidity of 100%, an applied voltage of 1.3 V, and a temperature of 121 ° C. In the TS test, a test that was allowed to stand at -125 ° C for 30 minutes and at 55 ° C for 30 minutes was repeated 1000 lines.
[0133]
In the above reliability test, it was found that a printed wiring board with a built-in chip capacitor could achieve the same reliability as the existing capacitor surface mount type. Further, as described above, in the TS test, even if internal stress occurs due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and the interlayer resin insulation layer, the chip capacitor terminals and vias It was proved that high reliability can be achieved over a long period of time without disconnection, peeling between the chip capacitor and the interlayer resin insulation layer, and no cracking in the interlayer resin insulation layer.
[0134]
【The invention's effect】
In the configuration of the present invention, since the via according to the present invention is formed between the conductor circuit and the capacitor, the operation can be maintained without delay due to insufficient power supply, and the reliability test can be performed. Did not cause any problems.
In addition, even if a via hole in the interlayer insulating layer is formed or a positional shift is caused by the via, the allowable range is widened, so that electrical connectivity is ensured.
[Brief description of the drawings]
FIGS. 1A, 1B, 1C, 1D and 1E are manufacturing process diagrams of a printed wiring board according to a first embodiment of the present invention.
FIGS. 2A, 2B, 2C and 2D are manufacturing process diagrams of a printed wiring board according to the first embodiment of the present invention.
3A, 3B, 3C, and 3D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
FIGS. 4A, 4B, 4C, and 4D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
5A, 5B, 5C, and 5D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
6A and 6B are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view of the printed wiring board according to the first embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a state where an IC chip is mounted on the printed wiring board according to the first embodiment of the present invention.
9A is an enlarged view of the via 52 in FIG. 7, and FIG. 9B is a B arrow diagram of FIG. 9A.
FIGS. 10A, 10B, 10C, and 10D are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
11 (A), (B), (C), and (D) are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
12A, 12B, 12C, and 12D are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
13A, 13B, 13C, and 13D are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
FIGS. 14A, 14B, 14C, and 14D are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
FIGS. 15A and 15B are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
16A and 16B are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
FIG. 17 is a cross-sectional view showing a state where an IC chip is mounted on a printed wiring board according to a second embodiment of the present invention.
FIG. 18 is a cross-sectional view showing a state where an IC chip is mounted on a printed wiring board according to a third embodiment of the present invention.
FIG. 19 is a cross-sectional view of the chip capacitor of the printed wiring board according to the first embodiment of the present invention.
FIG. 20 is a cross-sectional view showing a printed wiring board according to a fourth embodiment of the present invention.
FIG. 21 is a graph showing changes in supply voltage to IC chip and time.
22A, 22B, 22C, and 22D are plan views of chip capacitors of a printed wiring board according to a fifth embodiment.
FIG. 23 is a plan view of a chip capacitor of the printed wiring board according to the fifth embodiment.
FIG. 24 is a plan view of a chip capacitor of a printed wiring board according to a modification of the fifth embodiment.
[Explanation of symbols]
20 chip capacitors
21 1st terminal
22 Second terminal
30 core substrate
32 recess
33 recess
35 recess
36 Resin layer
40 Resin insulation layer
52 Via
53 Via
60 Interlayer resin insulation layer
68 Conductor circuit
69 Via
70 Solder resist layer
71U, 71D opening
72 Nickel plating layer
74 Gold plating layer
76 Solder bump
90 IC chip
92 Solder pads (IC chip side)
94 Daughter Board
95 Solder pad (Daughter board side)
96 Conductive connection pins
97 Conductive adhesive
98 fixed part
160 Interlayer resin insulation layer
168 Conductor circuit
169 Via

Claims (25)

A printed wiring board in which a capacitor is built in a core substrate and a resin insulation layer, an interlayer resin insulation layer and a conductor circuit are laminated on top of the capacitor,
It said resin insulating layer, and connected to the terminals of the capacitor, the surface is filled with a plating to form a flat lower-layer via the interlayer resin insulating layer of the upper surface of the resin insulating layer, with respect to 1 of the lower-layer via An upper layer via that is relatively smaller than the plurality of lower layer vias connected is disposed ,
An upper interlayer resin insulation layer having a plurality of vias is provided on the interlayer resin insulation layer, and each upper via is connected to a via in the upper interlayer resin insulation layer, and a lower via and each upper layer are connected. A printed wiring board , wherein a plurality of power supply lines are formed by vias and vias of an upper interlayer resin insulation layer connected to each upper via . A printed wiring board in which a capacitor is built in a core substrate and a resin insulation layer, an interlayer resin insulation layer and a conductor circuit are laminated on top of the capacitor,
The resin insulating layer is connected to the capacitor terminal, and a lower via formed of a filled via formed by filling a resin inside and forming a metal film having a flat surface is formed on the resin insulating layer. the interlayer resin insulating layer of the top surface, disposed a relatively small upper vias than the lower-layer via which the plurality connected to one of said lower-layer via,
An upper interlayer resin insulation layer having a plurality of vias is provided on the interlayer resin insulation layer, and each upper via is connected to a via in the upper interlayer resin insulation layer, and a lower via and each upper layer are connected. A printed wiring board , wherein a plurality of power supply lines are formed by vias and vias of an upper interlayer resin insulation layer connected to each upper via . 3. The printed wiring board according to claim 1, wherein a terminal surface of the capacitor built in the core substrate is flush with the surface of the core substrate. The capacitor, printed wiring board according to one of claims 1 to 3, characterized in that it is one contained in a recess formed in the core substrate. The capacitor, printed wiring board according to one of claims 1 to 3, characterized in that it is a plurality accommodated in a recess formed in the core substrate. Wherein a metal film is formed on the electrode of the capacitor, the first printed wiring board of claims 1 to 5, characterized in that took electrical connection by plating to the metal film was formed electrode. The metal film formed on electrodes of the capacitor, a printed wiring board according to one of claims 1 to 6, characterized in that the plating film composed mainly of copper. Wherein between the core substrate and the capacitor, the printed wiring board according to one of claims 1 to 7, characterized in that filled with resin having a low thermal expansion coefficient than the core substrate. Printed circuit board according to one of claims 1 to 8, characterized in that mounting the capacitor on the surface of the printed wiring board. Capacitance of the capacitor of the surface, the printed wiring board according to one of claims 1 to 9, characterized in that at least the capacitance of the inner layer of the capacitor. Inductance of the capacitor of the surface, the printed wiring board according to one of claims 1 to 10, characterized in that at inductance than the inner layer of the capacitor. Wherein exposing the at least a portion of the coating layer of the capacitor electrodes, according to claim 1 to claim 5, characterized in that it took electrical connection by plating on the exposed electrodes from the coating layer, according to claim 9 to claim Item 12. The printed wiring board according to item 1 of item 11 . As the capacitor, printed wiring board according to one of claims 1 to 12, characterized in that using a chip capacitor that is inside electrode is formed of the outer edge. As the capacitor, printed wiring board according to one of claims 1 to 1 3, characterized in that using a chip capacitor formed of the electrode in a matrix As the capacitor, printed wiring board according to one of claims 1 to 14, the chip capacitor was plurality ligated characterized by using in for multi-piece. The interlayer resin insulating layer or the resin insulating layer, a printed wiring board according to one of claims 1 to 15, characterized in that a resin made of an epoxy-based or polyolefin-based. A method for producing a printed wiring board comprising at least the following steps (a) to ( t ):
(A) forming a core substrate having a recess by forming a through hole in the resin plate and attaching the resin plate to the resin plate having the through hole;
(B) A step of accommodating a capacitor in the recess of the core substrate via an adhesive material;
(C) A step of filling a thermosetting resin between the capacitors accommodated in the recesses of the core substrate to form a resin layer;
(D) a step of aligning the terminal surface of the capacitor and the upper surface of the core substrate on the same surface;
(E) forming a resin insulating layer on the upper surface of the core substrate containing the capacitor;
(F) forming a lower via hole relatively larger than a via between interlayer resin insulating layers connected to the terminal of the capacitor in the resin insulating layer;
(G) forming through holes for through-holes in the resin layer and the resin insulating layer on the upper surface thereof, and heat-curing;
(H) forming a copper plating film on the resin insulating layer and the through-hole wall for the through hole by electroless plating;
(I) A step of applying a photosensitive dry film on the surface of the copper plating film, placing the mask on the surface, exposing and developing, and forming a resist having a predetermined pattern;
(J) filling the non-resist forming portion with electrolytic plating, and forming a relatively large via and through-hole having a filled via structure including a copper plating film and electrolytic copper plating;
(K) forming an interlayer resin insulation layer 60 on the upper surface of the resin insulation layer 40 ;
(L) the interlayer resin insulating layer 60 relatively smaller than the lower-layer via, providing a via opening leading to the lower-layer via the said 1 by a multi-step;
(M) forming an electroless copper plating layer on the via opening and the surface of the interlayer resin insulation layer 60 ;
(N) A step of applying a photosensitive dry film on the electroless copper plating layer, placing a photomask film, exposing and developing, and providing a plating resist;
(O) filling the non-resist forming part with electrolytic plating, and forming a plurality of vias relatively smaller than a lower via made of a copper plating film and electrolytic copper plating ;
(P) forming an interlayer resin insulation layer 160 on the lower via and the interlayer resin insulation layer surface 60;
(Q) providing a via opening that connects to each of a plurality of vias relatively smaller than the lower-layer via;
(R) forming an electroless copper plating layer on the via opening and the surface of the interlayer resin insulation layer 160;
(S) A step of applying a photosensitive dry film on the electroless copper plating layer, placing a photomask film, exposing and developing, and providing a plating resist;
(T) One in which the resist non-formed portion is filled with electrolytic plating and connected to each of a plurality of vias relatively smaller than a lower via formed in the interlayer resin insulating layer 60 made of a copper plating film and electrolytic copper plating. Forming a plurality of vias in the interlayer resin insulation layer 160; The method for manufacturing a printed wiring board according to claim 17 , wherein the interlayer resin insulation layer is an epoxy resin or a polyolefin resin. The method for manufacturing a printed wiring board according to claim 17 or 18 , wherein the concave portion of the core substrate is formed by counterboring on one surface of the core substrate. Method for manufacturing a printed wiring board according to one of claims 1 7 to claim 19, characterized in that it comprises a step of one accommodating the capacitor in said concave portion. Wherein a recess in the core substrate, a method for manufacturing a printed wiring board according to one of claims 17 to claim 19, characterized in that it comprises the step of plurality accommodating the capacitor in said concave portion. The method for manufacturing a printed wiring board according to any one of claims 17 to 21 , wherein when forming the lower layer via, a filled via having a flat surface is formed by filling with plating. When forming the lower-layer via, after filling the resin in the interior, of claims 17 to claim 21 in which the surface on the surface and forming a filled via made by disposing a flat metal film 1 The manufacturing method of the printed wiring board as described in 1 .. The print according to claim 21 , further comprising a step of applying pressure from above to the upper surfaces of the plurality of capacitors in the recess in the step (d) to align the heights of the upper surfaces of the capacitors. A method for manufacturing a wiring board. The method of manufacturing a printed wiring board according to claim 17, further comprising a step of forming solder bumps in a plurality of vias formed in the interlayer resin insulation layer 160.

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