JP4697828B2 - Printed wiring board and printed wiring board manufacturing method - Google Patents

Printed wiring board and printed wiring board manufacturing method Download PDF

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Publication number
JP4697828B2
JP4697828B2 JP2001070229A JP2001070229A JP4697828B2 JP 4697828 B2 JP4697828 B2 JP 4697828B2 JP 2001070229 A JP2001070229 A JP 2001070229A JP 2001070229 A JP2001070229 A JP 2001070229A JP 4697828 B2 JP4697828 B2 JP 4697828B2
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Prior art keywords
wiring board
printed wiring
capacitor
resin
board according
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JP2002271025A (en
Inventor
克敏 伊藤
誠二 白井
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イビデン株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed circuit board on which an electronic component such as an IC chip is placed, and more particularly to a printed wiring board having a capacitor built therein.
[0002]
[Prior art]
Currently, in a printed wiring board for a package substrate, a chip capacitor is sometimes surface-mounted for the purpose of facilitating power supply to an IC chip.
[0003]
Since the reactance of the wiring from the chip capacitor to the IC chip depends on the frequency, a sufficient effect cannot be obtained even if the chip capacitor is surface-mounted as the driving frequency of the IC chip increases. For this reason, the present applicant has proposed, in Japanese Patent Application No. 11-248311, a technique of forming a recess in the core substrate and accommodating a chip capacitor in the recess. Further, as a technique for embedding a capacitor in a substrate, JP-A-6-326472, JP-A-7-263619, JP-A-10-256429, JP-A-11-45955, JP-A-11-126978, JP-A-11- No. 31868 etc.
[0004]
Japanese Patent Application Laid-Open No. 6-326472 discloses a technique of embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, it is possible to reduce power supply noise, eliminate the need for a space for mounting a chip capacitor, and reduce the size of the insulating substrate. Japanese Patent Application Laid-Open No. 7-263619 discloses a technique for embedding a capacitor in a substrate such as ceramic or alumina. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.
[0005]
[Problems to be solved by the invention]
However, the above-mentioned Japanese Patent Laid-Open Nos. 6-326472 and 7-263619 cannot reduce the distance from the IC chip to the capacitor so much, and in the higher frequency region of the IC chip, the inductance is required as it is currently required. Could not be reduced. In particular, in multilayer build-up wiring boards made of resin, disconnection occurs between the chip capacitor terminals and vias due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and interlayer resin insulation layer. Peeling occurs between the capacitor and the interlayer resin insulation layer, and cracks occur in the interlayer resin insulation layer, and high reliability cannot be achieved over a long period of time.
[0006]
On the other hand, in the invention of Japanese Patent Application No. 11-248311, when there is a displacement in the position of the capacitor, the connection between the capacitor terminal and the via cannot be made accurately, and the power supply from the capacitor to the IC chip cannot be performed. was there.
[0007]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board having a built-in capacitor and improved connection reliability and a method for manufacturing the printed wiring board.
[0008]
[Means for Solving the Problems]
  In order to achieve the above object, the invention according to claim 1 is a printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate,
  Capacitor is built in the core substrate, and a relatively large lower layer via connected to the capacitor terminal is formed,
  A plurality of relatively small upper vias connected to one lower via are disposed in the interlayer resin insulation layer on the upper surface of the core substrate,
  A conductive paste is applied to the surface of the electrode made of metallization of the capacitor.And
The plurality of upper layer vias are respectively connected to a plurality of external connection terminals.This is a technical feature.
[0009]
According to the first aspect of the present invention, a capacitor is built in the core substrate, a relatively large lower via connected to the capacitor terminal is formed on the capacitor, and one lower via is connected to the interlayer resin insulating layer on the upper surface of the core substrate. A plurality of relatively small upper layer vias are provided. Accordingly, it is possible to connect the capacitor terminal and the lower layer via corresponding to the displacement of the capacitor arrangement, and it is possible to reliably supply power from the capacitor to the IC chip. In addition, by arranging a plurality of relatively small upper layer vias, it is possible to obtain the same effect as when the inductance components are connected in parallel, so that the high frequency characteristics of the power supply line and the ground line are enhanced, power supply is insufficient, or the ground level It is possible to prevent the malfunction of the IC chip due to the fluctuation of the. Furthermore, since the wiring length can be shortened, the loop inductance can be reduced.
[0010]
It is desirable to fill the recess with resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if stress originating from the capacitor is generated, it can be relaxed by the filled resin. The resin also has an effect of reducing adhesion and migration between the capacitor and the core substrate.
[0011]
Further, since the conductive paste is applied to the surface of the electrode made of metallization of the capacitor, the surface becomes completely flat. For this reason, when an opening is made in the resin layer with a laser, the resin does not remain on the surface of the electrode, and the connection reliability between the electrode and the via via plating can be improved.
[0012]
According to the second aspect, since the metal layer is provided on the conductive paste of the electrode of the capacitor, it is possible to prevent migration at the electrode and to further reduce the connection resistance.
[0013]
  Claim13Then, since the inductance of the capacitor on the surface is equal to or higher than the inductance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and the desired operation of the IC chip is ensured.
[0014]
According to a fourth aspect of the present invention, the surface of the capacitor is subjected to a wettability improving process such as silane coupling or resin coating. As a result, the adhesion between the ceramic chip capacitor and the connection layer and the interlayer resin insulation layer is improved, and even if the heat cycle test is performed, the connection layer and the interlayer resin insulation layer are not peeled off at the interface. .
[0015]
In the fifth and sixth aspects, a filled via having a flat surface is used as the lower layer via. As a result, a plurality of upper layer vias can be directly connected to one lower layer via. Therefore, the connectivity between the lower layer via and the upper layer via can be improved, and the power can be reliably supplied from the capacitor to the IC chip.
[0016]
According to a seventh aspect of the present invention, one capacitor is accommodated in the recess formed in the core substrate. Thereby, since the capacitor is arranged in the core substrate, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced.
[0017]
According to the eighth aspect of the present invention, since a large number of capacitors can be accommodated in the recesses, the capacitors can be highly integrated.
[0018]
According to a ninth aspect of the present invention, the resin is filled between the core substrate and the capacitor, and the thermal expansion coefficient of the resin is set smaller than that of the core substrate, that is, close to the capacitor made of ceramic. For this reason, in the heat cycle test, even if an internal stress occurs due to a difference in thermal expansion coefficient between the core substrate and the capacitor, cracks, peeling, and the like hardly occur in the core substrate, and high reliability can be achieved.
[0019]
  Claim11Then, in addition to the capacitor accommodated in the substrate, a capacitor is provided on the surface. Since the capacitor is accommodated in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance can be reduced, and the power can be supplied instantaneously. Since the capacitor is disposed, a large-capacity capacitor can be attached, and a large amount of power can be easily supplied to the IC chip.
[0020]
  Claim12Then, since the capacitance of the capacitor on the surface is equal to or greater than the capacitance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and the desired operation of the IC chip is ensured.
[0021]
According to the twelfth aspect, since the inductance of the capacitor on the surface is equal to or larger than the inductance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and a desired operation of the IC chip is ensured.
[0022]
  Claim14Then, since a chip capacitor having an electrode formed inside the outer edge is used, even if conduction is made through a via, the external electrode can be made large and the allowable range of alignment is widened, so that connection failure is eliminated.
[0023]
  Claim15Then, since a capacitor having electrodes formed in a matrix is used, a large chip capacitor can be easily accommodated in the core substrate. As a result, the capacitance can be increased, and the electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is hardly warped.
[0024]
  Claim16Then, a plurality of chip capacitors may be connected to the capacitor. Thereby, the capacitance can be adjusted as appropriate, and the IC chip can be operated appropriately.
[0025]
  Claim17In the method for producing a printed wiring board of (a) to (f) Has the technical feature:
(A) a step of incorporating a capacitor in which a conductive paste is applied on a metallized electrode on a core substrate;
(B) forming a resin insulating layer on the upper surface of the capacitor;
(C) forming a relatively large lower via connected to the capacitor terminal in the resin insulating layer;
(D) forming an interlayer resin insulation layer on the upper surface of the core substrate;
(E) Disposing a plurality of relatively small upper layer vias connected to one lower layer via in the interlayer resin insulation layer;
(F) A step of providing a plurality of external connection terminals respectively connected to the plurality of upper layer vias..
[0026]
  Claim17Then, a capacitor is built in the core substrate, a relatively large lower via connected to the capacitor terminal is formed on the capacitor, and a plurality of lower vias connected to one lower via are formed in the interlayer resin insulating layer on the upper surface of the core substrate. The relatively small upper layer via is disposed. Accordingly, it is possible to connect the capacitor terminal and the lower layer via corresponding to the displacement of the capacitor arrangement, and it is possible to reliably supply power from the capacitor to the IC chip. In addition, by arranging a plurality of relatively small upper layer vias, it is possible to obtain the same effect as when the inductance components are connected in parallel, so that the high frequency characteristics of the power supply line and the ground line are enhanced, power supply is insufficient, or the ground level It is possible to prevent the malfunction of the IC chip due to the fluctuation of the. Furthermore, since the wiring length can be shortened, the loop inductance can be reduced.
[0027]
Further, since the conductive paste is applied to the surface of the capacitor electrode, the surface becomes completely flat. For this reason, when an opening is made in the resin layer with a laser, the resin does not remain on the surface of the electrode, and the connection reliability between the electrode and the via via plating can be improved.
[0028]
  Claim18Then, one capacitor is accommodated in a recess formed in the core substrate. Thereby, since the capacitor is arranged in the core substrate, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced.
[0029]
  Claim19Then, since a large number of capacitors can be accommodated in the recesses, the capacitors can be highly integrated.
[0030]
  Claim20Then, a through hole is formed in a resin material containing a resin as a core material, and the resin material is attached to the resin material in which the through hole is formed to form a core substrate having a recess. As a result, a core substrate having a concave portion with a flat bottom can be formed.
[0031]
  Claim21, Claims22In this case, a filled via having a flat surface is used as the lower layer via. As a result, a plurality of upper layer vias can be directly connected to one lower layer via. Therefore, the connectivity between the lower layer via and the upper layer via can be improved, and the power can be reliably supplied from the capacitor to the IC chip.
[0032]
  Claim23In this invention, the heights of the upper surfaces of the capacitors are made uniform by applying pressure to or tapping the upper surfaces of the plurality of capacitors in the recesses. Thereby, when the capacitors are disposed in the recesses, the heights can be made uniform even if the sizes of the plurality of capacitors vary, and the core substrate can be made smooth. Therefore, the smoothness of the core substrate is not impaired, and the upper interlayer resin insulation layer and the conductor circuit can be appropriately formed, so that the defective product occurrence rate of the printed wiring board can be reduced.
[0033]
The thermosetting resin film used in the interlayer resin insulation layer and the connection layer of the present invention is a resin in which particles soluble in an acid or an oxidant (hereinafter referred to as soluble particles) are hardly soluble in an acid or an oxidant (hereinafter, poorly soluble). Resin).
As used herein, the terms “poorly soluble” and “soluble” refer to those having a relatively fast dissolution rate as “soluble” for convenience when immersed in a solution of the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as “slightly soluble” for convenience.
[0034]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
[0035]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0036]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present invention, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0037]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluorine resin, and the like, and may be composed of one of these resins. And it may consist of a mixture of two or more resins.
[0038]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified various modified polybutadiene rubber, carboxyl group-containing (meth) acrylonitrile-butadiene rubber, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.
[0039]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0040]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0041]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0042]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted between the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.
[0043]
The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via opening can be formed in the interlayer resin insulation layer using exposure and development processes.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.
[0044]
Specific examples of the hardly soluble resin include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more.
Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.
[0045]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0046]
In the resin film used in the present invention, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface having unevenness of uniform roughness can be formed, and even if a via or a through hole is formed in a resin film, adhesion of a metal layer of a conductor circuit formed thereon can be secured. Because. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. As a result, since the portion other than the surface layer portion of the resin film is not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is reliably maintained.
[0047]
In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin film is melted to the deep part of the resin film, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.
[0048]
The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0049]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0050]
Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By containing these fillers, it is possible to improve the performance of the printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0051]
Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more.
[0052]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board 10, and FIG. 8 shows a state in which the IC chip 90 is mounted on the printed wiring board 10 shown in FIG. 9A is an enlarged view of the via 52 in FIG. 7, and FIG. 9B shows a state in which a plurality of vias 69 are arranged in the via 52 in FIG. 9A. It is a schematic diagram which shows the state seen from.
[0053]
As shown in FIG. 7, the printed wiring board 10 includes a core substrate 30 that houses a plurality of chip capacitors 20, and build-up wiring layers 80A and 80B. A relatively large via 52 is connected to the terminals 21 and 22 of the plurality of chip capacitors 20 accommodated in the core substrate 30. The build-up wiring layers 80A and 80B are composed of interlayer resin insulation layers 60 and 160. Conductor circuit 68 and relatively small via 69 are formed in interlayer resin insulation layer 60, and conductor circuit 168 and relatively small via 169 are formed in interlayer resin insulation layer 160. A solder resist layer 70 is disposed on the interlayer resin insulating layer 160.
[0054]
As shown in FIG. 10A, the chip capacitor 20 includes a first electrode 21, a second electrode 22, and a dielectric 23 sandwiched between the first and second electrodes. A plurality of first conductive films 24 connected to the electrode 21 side and second conductive films 25 connected to the second electrode 22 side are arranged to face each other. The surface of the first electrode 21 and the second electrode 22 is covered with a conductive paste 26.
[0055]
Here, the 1st electrode 21 and the 2nd electrode 22 consist of metallization of Ni, Pb, or Ag metal. The conductive paste 26 is made of a paste containing metal particles such as Cu, Ni, or Ag. Here, the particle diameter of the metal particles is desirably 0.1 to 10 μm, and particularly 1 to 5 μm is optimal. As the conductive paste, an organic conductive paste in which a thermosetting resin such as an epoxy resin or a polyphenylene sulfide (PPS) resin is added to metal particles is desirable. The thickness of the conductive paste 26 is desirably 1 to 30 μm. If the thickness is less than 1 μm, the unevenness of the electrode surface cannot be eliminated. On the other hand, if the thickness exceeds 30 μm, the effect is not particularly improved. Here, a thickness of 5 to 20 μm is most desirable. In addition, it is possible to use a paste in which particles having two or more types of different diameters are blended, and it is also possible to coat a metal paste having two or more types of different diameters.
[0056]
The electrodes 21 and 22 of the chip capacitor are made of metallization and have irregularities on the surface. For this reason, if the metal layer is used in a state where it is exposed, the resin may remain on the unevenness in the step of forming the opening 42 in the resin insulating layer 40 with a laser. At this time, poor connection between the first and second electrodes 21 and 22 and the via 52 occurs due to the resin residue. In the present embodiment, the surfaces of the first and second electrodes 21 and 22 are smoothed by the conductive paste 26, and when the opening 42 covered on the electrodes is drilled, no resin residue remains, and the via 52 The connection reliability with the electrodes 21 and 22 can be improved when the is formed.
[0057]
Further, a roughened layer 23 a is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. Therefore, the adhesiveness between the ceramic chip capacitor 20 and the resin adhesive material 34 and the resin insulating layer 40 is high, and the resin adhesive material 34 and the resin insulating layer 40 at the interface even when the heat cycle test is performed. No peeling occurs. The roughened layer 23a can be formed by polishing the surface of the chip capacitor 20 after firing, or by performing a roughening treatment before firing.
[0058]
  As shown in FIG. 8, the solder bumps 76U for connection to the pads 92 of the IC chip 90 are formed in the vias 169 of the upper buildup wiring layer 80A.(External connection terminal)Is formed. On the other hand, a solder bump 76D for connection to the pad 95 of the daughter board 94 is formed in the via 169 of the lower buildup wiring layer 80B.
[0059]
As the core substrate, one made of resin was used. For example, a resin material used in a general printed wiring board such as a glass epoxy resin-impregnated base material or a phenol resin-impregnated base material can be used. However, a substrate such as ceramic or AIN cannot be used as the core substrate. This is because the substrate has poor outer formability and cannot accommodate a capacitor, and even if it is filled with a resin, voids are generated.
[0060]
Further, since a plurality of chip capacitors 20 are accommodated in the recesses 32 formed in the core substrate 30, the chip capacitors 20 can be arranged with high density. Further, since the plurality of chip capacitors 20 are accommodated in the recess 32, the height of the chip capacitors 20 can be made uniform. For this reason, since the resin layer 40 on the chip capacitor 20 can be made to have a uniform thickness, the via 52 can be appropriately formed. In addition, since the distance between the IC chip 90 and the chip capacitor 20 is shortened, the loop inductance can be reduced.
[0061]
Further, as shown in FIG. 7 and FIG. 9A which is an enlarged view of the via 52 of FIG. 7, a plurality of vias 69 of the upper buildup wiring layer 80A are connected to one via 52. As shown in FIG. 9B, the large via 52 has an inner diameter of 125 μm and a land diameter of 165 μm, and the small via 69 has an inner diameter of 25 μm and a land diameter of 65 μm. On the other hand, the chip capacitor 20 is formed in a rectangular shape, and the first terminal 21 and the second terminal 21 are also formed in a rectangular shape with a side of 250 μm. For this reason, even if the arrangement position of the chip capacitor 20 is shifted by several tens of μm, the first terminal 21 and the second terminal 22 of the chip capacitor 20 and the via 52 can be connected. It is possible to reliably supply power to the chip 90. Further, by providing a plurality of vias 69, it is possible to obtain the same effect as when the inductance components are connected in parallel. Therefore, the high frequency characteristics of the power supply line and the ground line are enhanced, and the IC due to insufficient power supply or ground level fluctuations. It is possible to prevent malfunction of the chip. Furthermore, since the wiring length from the IC chip to the chip capacitor 20 can be shortened, the loop inductance can be reduced.
[0062]
As shown in FIG. 7, the via 52 is formed as a filled via filled with plating and having a flat surface. As a result, a plurality of vias 69 can be directly connected on the via 52. Therefore, the connectivity between the via 52 and the via 69 can be improved, and the power supply from the chip capacitor 20 to the IC chip 90 can be reliably performed. In the present embodiment, the filled via is formed by plating filling. Instead, as the via 52, a filled via in which a metal film is disposed on the surface after filling the resin inside may be used.
[0063]
The thermal expansion coefficients of the resin filler 36 and the adhesive material 34 under the chip capacitor 20 are set to be smaller than that of the core substrate 30 and the resin insulating layer 40, that is, close to the chip capacitor 20 made of ceramic. For this reason, in the heat cycle test, even if an internal stress occurs due to a difference in thermal expansion coefficient between the core substrate 30 and the resin insulating layer 40 and the chip capacitor 20, the core substrate 30 and the resin insulating layer 40 are cracked, peeled off, etc. It is difficult to occur and high reliability can be achieved.
[0064]
Further, since the through hole 54 is formed in the resin layer 36 between the chip capacitors 20, the signal line does not pass through the ceramic chip capacitor 20, so that reflection due to impedance discontinuity due to the high dielectric material and passage through the high dielectric material are possible. Propagation delay does not occur.
[0065]
Next, a method for manufacturing the printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.
[0066]
(1) First, a core substrate 30 made of an insulating resin substrate is used as a starting material (see FIG. 1A). Next, a concave portion 32 for disposing the capacitor is formed on one surface of the core substrate 30 by counterboring or providing a through hole in an insulating resin and pressing and bonding (see FIG. 1B). At this time, the concave portion 32 is formed wider and larger than an area where a plurality of capacitors can be disposed. Thereby, a plurality of capacitors can be reliably disposed on the core substrate 30.
[0067]
(2) Thereafter, the adhesive material 34 is applied to the recess 32 using a printing machine (see FIG. 1C). Alternatively, the adhesive material can be applied to the concave portion by a method such as potting, die bonding, or attaching an adhesive sheet. As the adhesive material 34, a material having a thermal expansion coefficient smaller than that of the core substrate is used. Next, a plurality of chip capacitors 20 made of ceramic are bonded to the recesses 32 via an adhesive material 34 (see FIG. 1D). Here, by arranging the plurality of chip capacitors 20 in the recesses 32 having a smooth bottom, the heights of the plurality of chip capacitors 20 are aligned. Therefore, the resin insulating layer 40 can be formed on the core substrate 30 with a uniform thickness and the vias 52 can be appropriately formed in the process described later.
[0068]
Then, the top surfaces of the chip capacitors 20 are pushed or hit so that the top surfaces of the plurality of chip capacitors 20 have the same height (see FIG. 1E). With this process, when the plurality of chip capacitors 20 are disposed in the recesses 32, the heights can be completely aligned even if the sizes of the plurality of chip capacitors 20 vary. Can be smoothed.
[0069]
(3) Thereafter, a thermosetting resin is filled between the chip capacitors 20 in the recess 32, and the resin layer 36 is formed by heat curing (see FIG. 2A). At this time, epoxy, phenol, polyimide, and triazine are preferable as the thermosetting resin. Thereby, the chip capacitor 20 in the recess 32 can be fixed. The resin layer 36 has a thermal expansion coefficient smaller than that of the core substrate.
[0070]
In addition, a resin such as a thermoplastic resin may be used. Further, a filler may be impregnated in order to match the thermal expansion coefficient in the resin. Examples of the filler include an inorganic filler, a ceramic filler, and a metal filler.
[0071]
(4) Further, the above-described epoxy resin or polyolefin resin is applied from above using a printing machine to form the resin insulating layer 40 (see FIG. 2B). In addition, you may affix a resin film instead of apply | coating resin.
[0072]
In addition, one or more resins such as a thermosetting resin, a thermoplastic resin, a photosensitive resin thermosetting resin / thermoplastic resin composite, and a photosensitive resin / thermoplastic resin composite can be used. . You may make them into 2 layer structure.
[0073]
(5) Next, a relatively large via opening 42 is formed in the resin insulating layer 40 by a laser (see FIG. 2C). At this time, since the surfaces of the electrodes 21 and 22 of the chip capacitor 20 are smooth by the conductive paste 26, the resin does not remain on the electrodes. Thereafter, desmear processing is performed. An exposure / development process can be used instead of the laser. Then, through holes 44 for through holes are formed in the resin layer 36 with a drill or a laser, and are cured by heating (see FIG. 2D). In some cases, a roughening treatment with an acid, an oxidizing agent or a chemical solution, or a roughening treatment with a plasma treatment may be performed. Thereby, the adhesion of the roughened layer is ensured.
[0074]
(6) Thereafter, a copper plating film 46 is formed on the surface of the resin insulating layer 40 by electroless copper plating (see FIG. 3A). Instead of electroless plating, Ni / Cu metal layer may be formed by performing sputtering using Ni and Cu as targets. In some cases, the electroless plating film may be formed after the sputtering. At this time, since no resin remains on the surfaces of the electrodes 21 and 22 of the chip capacitor 20, the copper plating film 46 can be appropriately formed on the electrodes 21 and 22.
[0075]
(7) Next, a photosensitive dry film is affixed to the surface of the copper plating film 46, a mask is placed thereon, exposure and development are performed, and a plating resist 48 having a predetermined pattern is formed. Then, the core substrate 30 is immersed in the electrolytic plating solution, and a current is passed through the copper plating film 46, so that the electrolytic plating 50 is filled in the portion where the plating resist 48 is not formed (see FIG. 3B).
[0076]
(8) Next, after the plating resist 48 is peeled and removed with 5% NaOH, the copper plating film 46 under the plating resist 48 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. A relatively large via 52 and a through hole 54 having a filled via structure made of electrolytic copper plating 50 are formed. The large via diameter is desirably in the range of 100 to 600 μm. In particular, it is desirable that it is 125-350 micrometers. In this case, it was formed at 165 μm. The through hole was formed at 250 μm. Then, an etching solution is sprayed onto both surfaces of the substrate 30 to etch the surface of the via 52 and the land surface of the through hole 54, thereby forming a roughened surface 52α on the entire surface of the via 52 and the through hole 54. (See FIG. 3C).
[0077]
(9) Thereafter, the through hole 54 is filled with a resin filler 56 mainly composed of an epoxy resin and dried (see FIG. 3D).
[0078]
(10) A pressure of 5 kg / cm while heating a thermosetting resin film having a thickness of 50 μm to a temperature of 50 to 150 ° C. on both surfaces of the substrate 30 that has undergone the above-described steps.2Then, an interlayer resin insulation layer 60 is provided by vacuum compression lamination (see FIG. 4A). The degree of vacuum at the time of vacuum bonding is 10 mmHg. As the resin film, an epoxy resin or an olefin resin can be used.
[0079]
(11) Next, CO2A relatively small via opening 61 of 65 μm is provided in the interlayer resin insulating layer 60 by a gas laser (see FIG. 4B). The relatively small via diameter is preferably in the range of 25-100 μm. Thereafter, desmear treatment is performed using oxygen plasma.
[0080]
(12) Next, plasma processing is performed using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. to roughen the surface of the interlayer resin insulation layer 60 to form a roughened surface 60α (see FIG. 4C). . At this time, argon gas is used as the inert gas, and plasma treatment is performed for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, and temperature 70 ° C. You may roughen by an acid or an oxidizing agent. The roughened layer is preferably 0.1 to 5 μm.
[0081]
(13) Next, using the same apparatus, after replacing the argon gas inside, sputtering with Ni and Cu as targets was performed under conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, time 5 minutes, A Ni / Cu metal layer 62 is formed on the surface of the interlayer resin insulation layer 60. At this time, the thickness of the formed Ni / Cu metal layer 62 is 0.2 μm (see FIG. 4D). A plating film such as electroless plating or a plating film may be formed on the sputter.
[0082]
(14) A commercially available photosensitive dry film is pasted on both sides of the substrate 30 after the above treatment, and a photomask film is placed thereon, and 100 mJ / cm.2After the exposure, a development process is performed with 0.8% sodium carbonate to provide a plating resist 64 having a thickness of 15 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 66 having a thickness of 15 μm (see FIG. 5A). The additive in the electrolytic plating aqueous solution is Kaparaside HL manufactured by Atotech Japan.
[0083]
[0084]
(15) After stripping and removing the plating resist 64 with 5% NaOH, the Ni / Cu metal layer 62 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide. A plurality of relatively small vias 69 connected to the conductor circuit 68 and the via 52 made of the metal layer 62 and the electrolytic plating film 66 are formed (see FIG. 5B). In the present embodiment, the via 52 has a filled via structure, whereby a plurality of vias 69 can be directly connected to the via 52.
[0085]
(16) Next, the substrate is washed with water and dried, and then the surface of the conductor circuit 68 is etched by spraying an etching solution onto both surfaces of the substrate, thereby roughening the surface of the conductor circuit 68. (See FIG. 5C). As an etching solution, a mixture of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride and 78 parts by weight of ion-exchanged water is used.
[0086]
(17) Next, by repeating the above steps (10) to (16), an upper interlayer resin insulation layer 160 and a conductor circuit 168 (including via 169) are formed (see FIG. 5D). .
[0087]
(18) Next, the photosensitizing property obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 15 parts by weight of imidazole curing agent (manufactured by Shikoku Chemicals) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) which is a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.7 A weight part is put into a container, and a mixed composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator and Michler's ketone as a photosensitizer for the mixed composition. (Kanto Chemical Co., Ltd.) 0.2 part by weight is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured using a B-type viscometer (manufactured by Tokyo Keiki Co., Ltd., DVL-B type) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3.
[0088]
(19) Next, the solder resist composition is applied to both surfaces of the substrate 30 to a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes, the opening of the solder resist is performed. A photomask having a thickness of 5 mm on which the pattern of the portion is drawn is brought into close contact with the solder resist layer 70 to 1000 mJ / cm2Are exposed to UV light and developed with DMTG solution to form openings 71U and 71D (see FIG. 6A). A commercially available solder resist such as LPSR may also be used.
[0089]
(20) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed is made of nickel chloride (2.3 × 10-1mol / l), sodium hypophosphate (2.8 × 10 6)-1mol / l), sodium citrate (1.6 × 10-1The nickel plating layer 72 having a thickness of 5 μm is formed in the openings 71U and 71D by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6-3mol / l), ammonium chloride (1.9 × 10-1mol / l), sodium citrate (1.2 × 10-1mol / l), sodium hypophosphite (1.7 × 10-1mol / l) for 7.5 minutes at 80 ° C. to form a 0.03 μm thick gold plating layer 74 on the nickel plating layer 72 (see FIG. 6B). ).
[0090]
(21) Thereafter, solder bumps (solder bodies) 76U and 76D are formed by printing solder paste on the openings 71U and 71D of the solder resist layer 70 and reflowing at 200 ° C. Thereby, the printed wiring board 10 having the solder bumps 76U and 76D can be obtained (see FIG. 7).
[0091]
Next, placement of the IC chip on the printed wiring board 10 completed in the above-described process and attachment to the daughter board will be described with reference to FIG. The IC chip 90 is mounted so that the solder pads 92 of the IC chip 90 correspond to the solder bumps 76U of the completed printed wiring board 10, and the IC chip 90 is attached by performing reflow. Similarly, the printed wiring board 10 is attached to the daughter board 94 by reflowing so that the pads 95 of the daughter board 94 correspond to the solder bumps 76 </ b> D of the printed wiring board 10.
[0092]
Next, a printed wiring board according to a modification of the first embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, only the chip capacitor 20 accommodated in the core substrate 30 is provided. However, in the modified example, large-capacity chip capacitors 98 are mounted on the front surface and the back surface.
[0093]
FIG. 10B shows a cross section of the chip capacitor 20 according to the first modification of the first embodiment. In the first embodiment, the surface of the capacitor is roughened to improve the adhesion with the resin. However, in the first modified example, the surface wettability is obtained by forming the polyimide film 23b instead. Has been improved. Instead of the polyimide film, a silane coupling process can be applied to the surface of the capacitor.
[0094]
In the first modified example, a composite metal film 28 composed of an electroless copper plating film 28 a and an electrolytic copper plating film 28 b is formed on the conductive paste 26. The thickness of the composite metal film 28 is desirably 0.1 to 10 μm, and optimally 1 to 5 μm. Instead of the composite metal film, it is also possible to form a single-layer metal film.
[0095]
In the first modified example, since the metal layer 28 is provided on the conductive paste 26 of the electrodes 21 and 22 of the capacitor 20, the occurrence of migration at the electrodes 21 and 22 can be prevented, and the connection resistance is reduced. Further reduction can be achieved. The electrodes 21 and 22 made of metallized have irregularities on the surface, but by applying the conductive paste 26 and further providing the metal layer 28, the irregularities can be completely eliminated and the adhesion to the via 52 is improved. The connection resistance can be lowered.
[0096]
An IC chip consumes a large amount of power instantaneously and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in the modified example, a chip capacitor 20 for power supply and a chip capacitor 98 are provided on the printed wiring board. The effect of this chip capacitor will be described with reference to FIG.
[0097]
In FIG. 12, the vertical axis represents voltage supplied to the IC chip, and the horizontal axis represents time. Here, an alternate long and two short dashes line C indicates a voltage fluctuation of a printed wiring board that does not include a power supply capacitor. When the power supply capacitor is not provided, the voltage is greatly attenuated. A broken line A indicates voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. The voltage does not drop much as compared with the two-dot chain line C, but the loop length becomes long, so the rate-determining power supply cannot be sufficiently performed. That is, the voltage drops at the start of power supply. A two-dot chain line B indicates a voltage drop of the printed wiring board containing the chip capacitor described above with reference to FIG. Although the loop length can be shortened, the voltage fluctuates because a large-capacity chip capacitor cannot be accommodated in the core substrate 30. Here, the solid line E indicates the voltage fluctuation of the modified printed wiring board in which the chip capacitor 20 in the core substrate described above with reference to FIG. 11 and the large-capacity chip capacitor 98 are mounted on the surface. By providing a chip capacitor 20 in the vicinity of the IC chip, a chip capacitor 20 having a large capacity (and relatively large inductance), and a chip capacitor 98 having a large capacity (and relatively large inductance), a voltage can be obtained. Minimizes fluctuations.
[0098]
The printed wiring board 110 according to the second embodiment of the present invention will be described with reference to FIG. In 1st Embodiment mentioned above, the case where BGA was arrange | positioned demonstrated. The second embodiment is substantially the same as the first embodiment, but is configured in a PGA system in which connection is made via a conductive pin 96 as shown in FIG. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0099]
Then, the manufacturing method of the printed wiring board mentioned above with reference to FIG. 20 is demonstrated with reference to FIGS.
[0100]
(1) First, a through hole 33a for accommodating a chip capacitor is formed in a laminate 30α obtained by laminating four prepregs 31 impregnated with an epoxy resin. On the other hand, a laminated plate 30β obtained by laminating two prepregs 31 is prepared (see FIG. 13A). Here, as the prepreg 31, in addition to epoxy, a material containing a reinforcing material such as BT, phenol resin, or glass cloth can be used.
[0101]
(2) Next, the laminated board 30α and the laminated board 30β are pressure-bonded and heated and cured to form the core substrate 30 having the recesses 33 that can accommodate the plurality of chip capacitors 20 (FIG. 13 (B)).
[0102]
(3) Then, the adhesive material 34 is applied to the capacitor placement position of the recess 33 using a potting (dispenser) (see FIG. 13C). Alternatively, the adhesive material can be applied to the recesses by a method such as printing, die bonding, or attaching an adhesive sheet. Thereafter, the plurality of chip capacitors 20 made of ceramic are accommodated in the recesses 33 through the adhesive material 34 (see FIG. 13D).
[0103]
(4) Thereafter, a thermosetting resin is filled between the chip capacitors 20 in the recesses 33, and heat-cured to form the resin layer 36 (see FIG. 14A). At this time, epoxy, phenol, polyimide, and triazine are preferable as the thermosetting resin. Thereby, the chip capacitor 20 in the recess 33 can be fixed.
[0104]
(5) Furthermore, the resin which consists of the epoxy type or polyolefin type mentioned above is apply | coated using the printing machine from there, and the resin insulating layer 40 is formed (refer FIG. 14 (B)). In addition, you may affix a resin film instead of apply | coating resin.
[0105]
(6) Next, a relatively large via opening 42 is formed in the resin insulating layer 40 by exposure / development processing or laser (see FIG. 14C). The large via diameter is desirably in the range of 100 to 600 μm. In particular, it is desirable that it is 125-350 micrometers. In this case, it was formed at 165 μm. Then, through holes 44 for 250 μm diameter through holes are formed in the resin layer 36 with a drill or a laser, and are cured by heating (see FIG. 14D).
[0106]
(7) Then, after a palladium catalyst is applied to the substrate 30, the core substrate is immersed in the electroless plating solution to deposit the electroless plating film 45 uniformly (see FIG. 15A). Thereafter, the inside of the opening 42 in which the electroless plating film 45 is formed is filled with a resin filler and dried. Thereby, the resin layer 47 is formed inside the opening 42 (see FIG. 15B).
[0107]
(8) Thereafter, a photosensitive dry film is attached to the surface of the electroless plating film 45, a mask is placed, and exposure / development processing is performed to form a plating resist 48 having a predetermined pattern. Then, the core substrate 30 is immersed in an electrolytic plating solution to form a lid plating 51 made of an electroless plating film (see FIG. 15C).
[0108]
(9) After the above step, the plating resist 48 is peeled off with 5% NaOH, and then the electroless plating film 45 under the plating resist 48 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, thereby providing a filled via structure. A certain relatively large via 53 and through hole 54 are formed (see FIG. 15D). By making the via 53 have a filled via structure, a plurality of vias 69 can be directly connected to one via 53 in a process described later.
[0109]
(10) Then, the substrate 30 is washed with water, acid degreased, soft-etched, and then an etching solution is sprayed on both surfaces of the substrate 30 to spray the surface of the via 53, the land surface of the through hole 54, and the inner wall. Etching is performed to form a roughened surface 53α on the entire surface of the via 53 and the through hole 54 (see FIG. 16A). As an etching solution, an etching solution (MEC Etch Bond, manufactured by MEC) comprising 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride is used.
[0110]
(11) Next, 100 parts by weight of a bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310, YL983U), the average particle size of which the surface is coated with a silane coupling agent is 1.6 μm, SiO with a diameter of 15 μm or less2 170 parts by weight of spherical particles (manufactured by Adtech, CRS 1101-CE) and 1.5 parts by weight of a leveling agent (Perenol S4, manufactured by San Nopco) are placed in a container and mixed by stirring. A 49 Pa · s resin filler 56 is prepared. As the curing agent, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) was used.
Thereafter, the resin filler 56 is filled into the through hole 54 and dried (see FIG. 16B).
[0111]
(12) Next, 30 parts by weight of bisphenol A type epoxy resin (epoxy equivalent 469, Epicoat 1001 manufactured by Yuka Shell Epoxy), cresol novolak type epoxy resin (epoxy equivalent 215, Epicron N-673 manufactured by Dainippon Ink & Chemicals, Inc.) 40 parts by weight, 30 parts by weight of triazine structure-containing phenol novolak resin (phenolic hydroxyl group equivalent 120, Phenolite KA-7052 made by Dainippon Ink & Chemicals, Inc.) is stirred into 20 parts by weight of ethyl diglycol acetate and 20 parts by weight of solvent naphtha. Then, it was dissolved by heating, 15 parts by weight of terminal epoxidized polybutadiene rubber (Denalex R-45EPT manufactured by Nagase Kasei Kogyo Co., Ltd.) and 1.5 parts by weight of pulverized 2-phenyl-4,5-bis (hydroxymethyl) imidazole, 2 parts by weight of finely pulverized silica It was added 0.5 part by weight of silicon antifoaming agent to prepare an epoxy resin composition.
The obtained epoxy resin composition was applied on a PET film having a thickness of 38 μm using a roll coater so that the thickness after drying was 50 μm, and then dried at 80 to 120 ° C. for 10 minutes, whereby an interlayer resin was obtained. A resin film for an insulating layer is prepared.
[0112]
(13) An interlayer resin insulation layer resin film slightly larger than the substrate 30 produced in (12) is placed on the substrate 30 on both sides of the substrate, and the pressure is 4 kgf / cm.2 Then, after temporarily crimping and cutting under conditions of a temperature of 80 ° C. and a crimping time of 10 seconds, an interlayer resin insulation layer 60 is formed by further bonding using a vacuum laminator apparatus by the following method (FIG. 16C). reference). That is, a resin film for an interlayer resin insulation layer is placed on the substrate 30 with a degree of vacuum of 0.5 Torr and a pressure of 4 kgf / cm.2 The final pressure bonding is performed under the conditions of a temperature of 80 ° C. and a pressure bonding time of 60 seconds, and then heat-cured at 170 ° C. for 30 minutes.
[0113]
(14) Next, through the mask 57 in which the through-hole 57a having a thickness of 1.2 mm is formed on the interlayer resin insulating layer 60, the CO2 A relatively small via opening 61 of 65 μm is formed in the interlayer resin insulating layer 60 with a gas laser (see FIG. 16D). The relatively small via diameter is preferably in the range of 25-100 μm.
[0114]
(15) The substrate 30 having the via openings 61 is immersed in an 80 ° C. solution containing 60 g / l permanganic acid for 10 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer 60. Thus, the surface of the interlayer resin insulating layer 60 including the inner wall of the via opening 61 is made a roughened surface 60α (see FIG. 17A). You may roughen by an acid or an oxidizing agent. The roughened layer is preferably 0.1 to 5 μm.
[0115]
(16) Next, the substrate 30 after the above treatment is immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and then washed with water. Furthermore, a catalyst is attached to the surface of the interlayer resin insulation layer 60 and the inner wall surface of the via opening 61 by applying a palladium catalyst to the surface of the substrate 30 that has been roughened (roughening depth: 3 μm). .
[0116]
(17) Next, the substrate 30 is immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plating film 63 having a thickness of 0.6 to 3.0 μm over the entire roughened surface 60α ( FIG. 17B).
[Electroless plating aqueous solution]
NiSOFour                  0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 40 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at 35 ° C liquid temperature
[0117]
(18) A commercially available photosensitive dry film is affixed to the electroless copper plating film 63, a mask is placed, and 100 mJ / cm2 And a plating resist 64 having a thickness of 30 μm is provided by developing with a 0.8% aqueous sodium carbonate solution. Next, the substrate 30 is washed and degreased with 50 ° C. water, washed with 25 ° C. water, further washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions, and an electrolytic copper plating film having a thickness of 20 μm. 66 is formed (see FIG. 17C).
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside HL)
[Electrolytic plating conditions]
Current density 1 A / dm2
65 minutes
Temperature 22 ± 2 ° C
[0118]
(19) After stripping and removing the plating resist 64 with 5% NaOH, the electroless plating film 63 under the plating resist 64 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the electroless copper plating film A conductive circuit 68 having a thickness of 18 μm and a relatively small via 69 are formed of 63 and an electrolytic copper plating film 66 (see FIG. 17D). Then, the process similar to (10) is performed and the roughening surface 68 (alpha) is formed with the etching liquid containing a cupric complex and an organic acid (refer FIG. 18 (A)).
[0119]
(20) Subsequently, by repeating the steps (13) to (19), an upper interlayer resin insulation layer 160, a conductor circuit 168 and a via 169 are formed (see FIG. 18B).
[0120]
(21) Next, a photosensitizing agent obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 15 parts by weight of imidazole curing agent (manufactured by Shikoku Chemicals) , Trade name: 2E4MZ-CN) 1.6 parts by weight, bifunctional acrylic monomer as a photosensitive monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604), 4.5 parts by weight, also polyacrylic monomer (manufactured by Kyoei Chemical Co., Ltd.) , Trade name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0 71 parts by weight is placed in a container, and the mixture composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator for this mixture composition, 0.2 parts by weight of Michler's ketone (manufactured by Kanto Chemical Co., Inc.) is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured using a B-type viscometer (manufactured by Tokyo Keiki Co., Ltd., DVL-B type) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3.
[0121]
(22) Next, the solder resist composition prepared in (21) is applied to both surfaces of the multilayer wiring board to a thickness of 20 μm. Then, after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a photomask having a thickness of 5 mm on which the pattern of the opening of the solder resist was drawn was brought into close contact with the solder resist composition and 1000 mJ / cm2Are exposed to UV light and developed with DMTG solution to form openings 71U and 71D.
Further, the solder resist composition is cured by heating at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours, and has openings 71U and 71D. Then, a 20 μm thick solder resist layer 70 is formed (see FIG. 19A). A commercially available solder resist composition can also be used as the solder resist composition.
[0122]
(23) Next, the substrate on which the solder resist layer 70 is formed is nickel chloride (2.3 × 10-1mol / l), sodium hypophosphate (2.8 × 10 6)-1mol / l), sodium citrate (1.6 × 10-1The nickel plating layer 72 having a thickness of 5 μm is formed in the openings 71U and 71D by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6-3mol / l), ammonium chloride (1.9 × 10-1mol / l), sodium citrate (1.2 × 10-1mol / l), sodium hypophosphite (1.7 × 10-1mol / l) is immersed in an electroless gold plating solution at 80 ° C. for 7.5 minutes to form a 0.03 μm thick gold plating layer 74 on the nickel plating layer 72 (FIG. 19B). reference).
[0123]
(24) Thereafter, a solder paste containing tin-lead is printed in the opening 71U of the solder resist layer 70 on the surface on which the IC chip of the substrate is placed. Further, a solder paste is printed as the conductive adhesive 97 in the opening 71D on the other surface. Next, the conductive connection pin 96 is attached to and supported by an appropriate pin holding device, and the fixing portion 98 of the conductive connection pin 96 is brought into contact with the conductive adhesive 97 in the opening 71D. Then, reflow is performed to fix the conductive connection pin 96 to the conductive adhesive 97. As a method for attaching the conductive connection pin 96, a conductive adhesive 97 formed in a ball shape or the like is put into the opening 71D, or the conductive adhesive 97 is joined to the fixing portion 98 to conduct the conductive. May be attached and then reflowed.
[0124]
Thereafter, the IC chip 90 is mounted so that the solder pads 92 of the IC chip 90 correspond to the solder bumps 76 on the opening 71U side of the printed wiring board 110, and the IC chip 90 is attached by performing reflow (FIG. 20).
[0125]
Next, a printed wiring board according to the third embodiment of the present invention will be described with reference to FIG. The printed wiring board 210 of the third embodiment is almost the same as that of the first embodiment described above. However, in the printed wiring board 210 of the third embodiment, one chip capacitor 20 is accommodated in the recess 35 formed in the core substrate 30. Since the chip capacitor 20 is disposed in the core substrate 30, the distance between the IC chip 90 and the chip capacitor 20 is shortened, and the loop inductance can be reduced. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0126]
Next, the configuration of the printed wiring board according to the fourth embodiment of the present invention will be described with reference to FIG.
The configuration of the printed wiring board of the fourth embodiment is substantially the same as that of the first embodiment described above. However, the chip capacitor 20 accommodated in the core substrate 30 is different. FIG. 22 is a plan view of the chip capacitor. FIG. 22A shows a chip capacitor before cutting for multi-piece cutting, and a one-dot chain line in the drawing indicates a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are disposed on the side edge of the chip capacitor as shown in the plan view of FIG. FIG. 22C shows the chip capacitor before cutting for multi-piece fabrication according to the fourth embodiment, and the alternate long and short dash line in the drawing indicates the cutting line. In the printed wiring board of the fourth embodiment, the first electrode 21 and the second electrode 22 are disposed inside the side edge of the chip capacitor as shown in the plan view of FIG. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0127]
In the printed wiring board according to the fourth embodiment, since the chip capacitor 20 having electrodes formed inside the outer edge is used, a chip capacitor having a large capacity can be used.
[0128]
Next, a printed wiring board according to a first modification of the fourth embodiment will be described with reference to FIG.
FIG. 23 is a plan view of the chip capacitor 20 accommodated in the core substrate of the printed wiring board according to the first modification. In the first embodiment described above, a plurality of small-capacity chip capacitors are accommodated in the core substrate. However, in the first modification, a large-capacity large-sized chip capacitor 20 is accommodated in the core substrate. Here, the chip capacitor 20 includes a first electrode 21, a second electrode 22, a dielectric 23, a first conductive film 24 connected to the first electrode 21, and a second electrode connected to the second electrode 22 side. The conductive film 25 and the connection electrodes 27 on the upper and lower surfaces of the chip capacitor not connected to the first conductive film 24 and the second conductive film 25 are formed. The IC chip side and the daughter board side are connected via this electrode 27. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0129]
Since the large-sized chip capacitor 20 is used in the printed wiring board of the first modified example, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated.
[0130]
A printed wiring board according to a second modification will be described with reference to FIG. FIG. 24A shows a chip capacitor before cutting for multi-piece cutting, in which a one-dot chain line shows a normal cutting line, and FIG. 24B shows a plan view of the chip capacitor. . As shown in FIG. 24B, in the second modified example, a plurality of chip capacitors (three in the example in the figure) are used in a large format. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0131]
In the second modified example, since a large chip capacitor 20 is used, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated.
[0132]
In the fourth embodiment described above, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, it is also possible to use a plate-like capacitor in which a conductive film is provided on a ceramic plate.
[0133]
Here, with respect to the printed wiring board of the first embodiment, values obtained by measuring the inductance of the chip capacitor 20 embedded in the core substrate and the inductance of the chip capacitor mounted on the back surface (surface on the daughter board side) of the printed wiring board are as follows. It is shown below.
In the case of a single capacitor
Embedded type 137pH
Back mounting type 287pH
When 8 capacitors are connected in parallel
Embedded type 60pH
Back mounting type 72pH
As described above, even when the capacitor is used alone, the inductance can be reduced by incorporating the chip capacitor even when they are connected in parallel to increase the capacitance.
[0134]
Next, the results of the reliability test will be described. Here, in the printed wiring board of the first embodiment, the change rate of the capacitance of one chip capacitor was measured.
[0135]
The steam test was kept at 100% humidity by exposure to steam. In the HAST test, the sample was left for 100 hours at a relative humidity of 100%, an applied voltage of 1.3 V, and a temperature of 121 ° C. In the TS test, a test that was allowed to stand at -125 ° C for 30 minutes and at 55 ° C for 30 minutes was repeated 1000 lines.
[0136]
In the above reliability test, it was found that a printed wiring board with a built-in chip capacitor can achieve the same reliability as the existing capacitor surface mount type. As described above, in the TS test, even if internal stress occurs due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and the interlayer resin insulation layer, the chip capacitor terminals and vias It was proved that high reliability can be achieved over a long period of time without disconnection, peeling between the chip capacitor and the interlayer resin insulation layer, and no cracking in the interlayer resin insulation layer.
[0137]
【The invention's effect】
In the configuration of the present invention, since the via of the present invention is formed between the conductor circuit and the capacitor, the operation can be maintained without delay due to insufficient power supply, and the reliability test can be performed. Did not cause any problems.
In addition, even if the vias of the interlayer insulating layer are formed or misalignment is caused by the vias, the allowable range is widened, so that electrical connectivity is ensured.
[0138]
Further, since the conductive paste is applied to the surface of the capacitor electrode, the surface becomes completely flat. For this reason, when an opening is made in the resin layer with a laser, the resin does not remain on the surface of the electrode, and the connectivity between the electrode and the via via plating can be improved.
[Brief description of the drawings]
FIGS. 1A, 1B, 1C, 1D and 1E are manufacturing process diagrams of a printed wiring board according to a first embodiment of the present invention.
FIGS. 2A, 2B, 2C, and 2D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. FIGS.
FIGS. 3A, 3B, 3C and 3D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. FIGS.
4A, 4B, 4C, and 4D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
5A, 5B, 5C, and 5D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
6A and 6B are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view of the printed wiring board according to the first embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a state where an IC chip is mounted on the printed wiring board according to the first embodiment of the present invention.
9A is an enlarged view of the via 52 in FIG. 7, and FIG. 9B is a B arrow view of FIG.
10A is a cross-sectional view of the chip capacitor of the first embodiment, and FIG. 10B is a cross-sectional view of the chip capacitor of the first modified example of the first embodiment.
FIG. 11 is a cross-sectional view of a printed wiring board according to a modification of the first embodiment of the present invention.
FIG. 12 is a graph showing changes in power supplied to an IC chip and time.
13A, 13B, 13C, and 13D are manufacturing process diagrams of the printed wiring board according to the second embodiment of the present invention.
14A, 14B, 14C, and 14D are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
15A, 15B, 15C, and 15D are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
16 (A), (B), (C), and (D) are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
17A, 17B, 17C, and 17D are manufacturing process diagrams of the printed wiring board according to the second embodiment of the present invention.
18A and 18B are manufacturing process diagrams of the printed wiring board according to the second embodiment of the present invention.
FIGS. 19A and 19B are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention. FIGS.
FIG. 20 is a cross-sectional view showing a state where an IC chip is mounted on a printed wiring board according to a second embodiment of the present invention.
FIG. 21 is a cross-sectional view showing a state where an IC chip is mounted on a printed wiring board according to a third embodiment of the present invention.
22A, 22B, 22C, and 22D are plan views of chip capacitors of a printed wiring board according to a fourth embodiment.
FIG. 23 is a plan view of a chip capacitor of the printed wiring board according to the fourth embodiment.
24A and 24B are plan views of a chip capacitor of a printed wiring board according to a modification of the fourth embodiment.
[Explanation of symbols]
  20 chip capacitors
  21 First electrode
  22 Second electrode
  23 Dielectric
  23a Roughened surface
  23b Polyimide membrane
  26 Conductive paste
  28a Electroless copper plating film
  28b Electrolytic copper plating film
  28 Composite metal membrane
  30 core substrate
  32 recess
  33 recess
  35 recess
  36 Resin layer
  40 Resin insulation layer
  52 Via
  53 Via
  60 Interlayer resin insulation layer
  68 Conductor circuit
  69 Via
  70 Solder resist layer
  71U, 71D opening
  72 Nickel plating layer
  74 Gold plating layer
  76 Solder bump(External connection terminal)
  90 IC chip
  92 Solder pads (IC chip side)
  94 Daughter Board
  95 Solder pad (Daughter board side)
  96 Conductive connection pins
  97 Conductive adhesive
  98 fixed part
  160 Interlayer resin insulation layer
  168 Conductor circuit
  169 Via

Claims (23)

  1. A printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate,
    Capacitor is built in the core substrate, and a relatively large lower layer via connected to the capacitor terminal is formed,
    A plurality of relatively small upper vias connected to one lower via are disposed in the interlayer resin insulation layer on the upper surface of the core substrate,
    On the surface of the electrode made of metallization of the capacitor, a conductive paste is applied ,
    The printed wiring board, wherein the plurality of upper layer vias are respectively connected to a plurality of external connection terminals .
  2.   The printed wiring board according to claim 1, wherein a metal layer is provided on the conductive paste of the capacitor electrode.
  3.   The printed wiring board according to claim 1, wherein a roughening process is performed on a surface of the capacitor.
  4.   The printed wiring board according to claim 1, wherein the surface of the capacitor is subjected to a surface wettability improving process.
  5.   The printed wiring board according to claim 1, wherein the lower-layer via is a filled via having a flat surface filled with plating.
  6.   2. The printed wiring board according to claim 1, wherein the lower via is a filled via having a resin film filled therein and a metal film formed on a surface thereof. 3.
  7.   5. The printed wiring board according to claim 1, wherein one capacitor is accommodated in a recess formed in the core substrate. 6.
  8.   5. The printed wiring board according to claim 1, wherein a plurality of the capacitors are accommodated in a recess formed in the core substrate. 6.
  9.   5. The printed wiring board according to claim 1, wherein a resin having a smaller coefficient of thermal expansion than that of the core substrate is filled between the core substrate and the capacitor.
  10. The printed wiring board according to claim 9, wherein the resin contains an inorganic filler.
  11. Printed circuit board according to one of claims 1 to 10, characterized in that mounting the capacitor on the surface of the printed wiring board.
  12. The printed wiring board according to claim 11 , wherein a capacitance of the chip capacitor on the surface is equal to or greater than a capacitance of the inner layer chip capacitor.
  13. 13. The printed wiring board according to claim 12 , wherein the inductance of the chip capacitor on the surface is equal to or greater than the inductance of the inner layer chip capacitor.
  14. As the capacitor, printed wiring board according to one of claims 1 to 13, characterized in that using a chip capacitor having electrodes formed inside of the outer edge.
  15. As the capacitor, printed wiring board according to one of claims 1 to 14, characterized by using a chip capacitor formed of the electrode in a matrix.
  16. The printed wiring board according to any one of claims 1 to 15 , wherein a plurality of chip capacitors for connection are used as the capacitor.
  17. A method for producing a printed wiring board, comprising at least the following steps (a) to ( f ):
    (A) a step of incorporating a capacitor in which a conductive paste is applied on a metallized electrode on a core substrate;
    (B) forming a resin insulating layer on the upper surface of the capacitor;
    (C) forming a relatively large lower via connected to the capacitor terminal in the resin insulating layer;
    (D) forming an interlayer resin insulation layer on the upper surface of the core substrate;
    (E) disposing a plurality of relatively small upper vias connected to one lower via in the interlayer resin insulation layer ;
    (F) A step of providing a plurality of external connection terminals respectively connected to the plurality of upper layer vias .
  18. The method for manufacturing a printed wiring board according to claim 17 , further comprising a step of forming a recess in the core substrate and accommodating one capacitor in the recess before the step (a). .
  19. The method for manufacturing a printed wiring board according to claim 17 , further comprising a step of forming a recess in the core substrate and storing a plurality of the capacitors in the recess before the step (a). .
  20. Before the step (a), the method includes a step of forming a through hole in the resin plate, and affixing the resin plate to the resin plate formed with the through hole to form a core substrate having a recess. The manufacturing method of the printed wiring board of Claim 17 .
  21. 18. The method for manufacturing a printed wiring board according to claim 17 , wherein when forming the lower layer via, a filled via having a flat surface is formed by filling with plating.
  22. 18. The method for manufacturing a printed wiring board according to claim 17 , wherein when forming the lower layer via, a filled via having a metal film disposed on a surface thereof is formed after filling the inside with a resin.
  23. 20. The method according to claim 19 , further comprising, after the step (a), applying a pressure from above to the upper surfaces of the plurality of capacitors in the recess to align the heights of the upper surfaces of the capacitors. Manufacturing method of printed wiring board.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7894203B2 (en) 2003-02-26 2011-02-22 Ibiden Co., Ltd. Multilayer printed wiring board
TWI396481B (en) 2005-06-03 2013-05-11 Ngk Spark Plug Co Wiring board and manufacturing method of wiring board
JP4497548B2 (en) * 2006-03-28 2010-07-07 日本特殊陶業株式会社 Wiring board
JP5136632B2 (en) * 2010-01-08 2013-02-06 大日本印刷株式会社 Electronic components

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JPS63209133A (en) * 1987-02-25 1988-08-30 Aisin Seiki Co Ltd Semiconductor chip
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JPH0737757A (en) * 1993-07-20 1995-02-07 Murata Mfg Co Ltd Capacitor array
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